TWI672776B - 晶片封裝結構及其製造方法 - Google Patents
晶片封裝結構及其製造方法 Download PDFInfo
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- TWI672776B TWI672776B TW107136588A TW107136588A TWI672776B TW I672776 B TWI672776 B TW I672776B TW 107136588 A TW107136588 A TW 107136588A TW 107136588 A TW107136588 A TW 107136588A TW I672776 B TWI672776 B TW I672776B
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Abstract
一種晶片封裝結構包括線路結構、線路重佈結構、導熱元件、晶片及散熱片。線路結構包括第一線路層。線路重佈結構設置於線路結構上,並包括第二線路層,其中線路重佈結構具有開口。導熱元件設置於線路結構上,並被線路重佈結構所覆蓋。導熱元件具有水平部分及垂直部分。水平部分朝向開口延伸直至超過開口,從而水平部分的一部分被開口所暴露。垂直部分接觸水平部分,並向上延伸直至超過線路重佈結構的頂表面。晶片設置於開口中,且晶片的底部接觸導熱元件的水平部分。散熱片設置於線路重佈結構及晶片之上,並接觸晶片及導熱元件的垂直部分。
Description
本揭示內容係關於一種晶片封裝結構,以及關於一種晶片封裝結構的製造方法。
隨著晶片效能的提升,晶片的功耗也隨之增加,使得晶片的廢熱積存問題更加明顯。為了確保晶片的運作順暢,晶片封裝結構通常包括設置於晶片上的散熱片。散熱片可將晶片積存的廢熱導出,以避免因廢熱囤積而產生的損害。
在傳統的晶片封裝結構中,散熱片與晶片之間通常包括其他層,例如封裝材料層或用以接合散熱片的黏膠材料層。因此,在這種設計中,晶片積存的廢熱須通過上述其他層才可到達散熱片,以至於散熱效果不佳。
本揭示內容的一態樣係提供一種晶片封裝結構,包括線路結構、線路重佈結構、導熱元件、晶片、以及散熱片。線路結構包括第一線路層。線路重佈結構設置於線
路結構上,並包括與第一線路層電性連接的第二線路層,其中線路重佈結構具有開口。導熱元件設置於線路結構上,並具有水平部分及垂直部分。水平部分具有第一部分嵌置於線路重佈結構中,以及第二部分被開口所暴露。垂直部分由水平部分的第一部分向上延伸至超過線路重佈結構的頂表面。晶片設置於開口中,並電性連接第一線路層,其中晶片的底部接觸導熱元件的水平部分的第二部分。散熱片設置於線路重佈結構及晶片之上,並接觸晶片的頂部及導熱元件的垂直部分的頂部。
在本揭示內容的一實施方式中,導熱元件為L型結構。
在本揭示內容的一實施方式中,散熱片係經由超音波熔接製程而黏接於晶片的頂部及導熱元件的垂直部分的頂部。
在本揭示內容的一實施方式中,導熱元件的垂直部分與晶片的側壁具有50微米的一水平距離。
在本揭示內容的一實施方式中,晶片封裝結構進一步包括連接墊,設置於線路重佈結構與散熱片之間,並接觸散熱片。連接墊與第二線路層電性連接。
在本揭示內容的一實施方式中,晶片封裝結構進一步包括保護材料覆蓋晶片的側壁,並填充線路結構與晶片之間的空隙。
本揭示內容的另一態樣係提供一種晶片封裝結構的製造方法,包括下列操作:(i)提供一前驅結構,其中
前驅結構包括:一線路結構,包括一第一線路層;一線路重佈前驅結構,設置於線路結構上,並包括與第一線路層電性連接的一第二線路層;一導熱元件,設置於線路結構上,並具有:一水平部分,嵌置於線路重佈結構中;以及一垂直部分,由水平部分向上延伸至超過線路重佈前驅結構的一頂表面;以及一圖案化離型膜,設置於線路結構上,並被線路重佈前驅結構所覆蓋,其中圖案化離型膜覆蓋導熱元件的水平部分的一部分及與第一線路層電性連接的一連接墊;(ii)移除圖案化離型膜及位於圖案化離型膜上方的線路重佈前驅結構的一部分,以形一開口,其中開口暴露出導熱元件的水平部分及連接墊;(iii)設置一晶片於開口中,其中晶片電性連接連接墊,且晶片的一底部接觸導熱元件的水平部分;以及(iv)黏接一散熱片於晶片及導熱元件的垂直部分上。
在本揭示內容的一實施方式中,操作(i)包括下列步驟:(v)形成導熱元件的水平部分於線路結構上;(vi)形成線路重佈前驅結構覆蓋導熱元件的水平部分;(vii)圖案化線路重佈前驅結構以形成一穿孔暴露出導熱元件的水平部分的一部分;以及(viii)形成導熱元件的垂直部分於穿孔中。
在本揭示內容的一實施方式中,操作(ii)包括下列步驟:(a)使用一雷射鑽孔製程移除位於圖案化離型膜的一周邊的一垂直投影方向上的線路重佈前驅結構的一部分;以及(b)撕除圖案化離型膜及位於圖案化離型膜上方的線路重佈前驅結構的部分。
在本揭示內容的一實施方式中,操作(iv)係經由一超音波熔接製程來執行。
以下將以實施方式對上述之說明作詳細的描述,並對本揭示內容的技術方案提供更進一步的解釋。
10‧‧‧晶片封裝結構
10a‧‧‧前驅結構
100‧‧‧保護基板
200‧‧‧線路結構
211‧‧‧第一線路層
212‧‧‧第一介電層
212a‧‧‧導通孔
213‧‧‧第一導電接觸件
300‧‧‧線路重佈結構
300a‧‧‧開口
300b‧‧‧線路重佈前驅結構
310、310a‧‧‧第一線路重佈層
311‧‧‧第二線路層
312、312b、312c、312d‧‧‧第二介電層
312a‧‧‧導通孔
313‧‧‧第二導電接觸件
314‧‧‧連接墊
320、320a‧‧‧第二線路重佈層
321‧‧‧第三線路層
322、322b、322c、322d‧‧‧第三介電層
322a‧‧‧導通孔
323‧‧‧第三導電接觸件
400‧‧‧導熱元件
410‧‧‧水平部分
420、420"‧‧‧垂直部分
500‧‧‧晶片
600‧‧‧散熱片
700‧‧‧保護材料
800‧‧‧連接墊
900‧‧‧防焊層
A1‧‧‧接觸面
RF'‧‧‧離型膜
RF‧‧‧圖案化離型膜
TH‧‧‧穿孔
D1‧‧‧水平距離
D2‧‧‧水平距離
L1、L2‧‧‧長度
W1、W2‧‧‧寬度
第1A圖為本揭示內容一實施方式之晶片封裝結構的剖面示意圖。
第1B圖為本揭示內容一實施方式之晶片封裝結構的晶片與導熱元件的俯視示意圖。
第1C圖為本揭示內容一實施方式之晶片封裝結構的晶片與導熱元件的接觸面示意圖。
第2圖~第12圖為本揭示內容一實施方式之晶片封裝結構的製造方法的各個階段的剖面示意圖。
為了使本揭示內容的敘述更加詳盡與完備,下文針對了本揭示內容的實施態樣與具體實施例提出了說明性的描述;但這並非實施或運用本揭示內容具體實施例的唯一形式。以下所揭露的各實施例,在有益的情形下可相互組合或取代,也可在一實施例中附加其他的實施例,而無須進一步的記載或說明。在以下描述中,將詳細敘述許多特定細節以使讀者能夠充分理解以下的實施例。然而,可在無此等
特定細節之情況下實踐本揭示內容的實施例。
再者,空間相對用語,例如「下方」、「之下」、「上方」、「之上」等,這是為了便於敘述一元件或特徵與另一元件或特徵之間的相對關係。這些空間上的相對用語的真實意義包含其他的方位。例如,當圖式上下翻轉180度時,一元件與另一元件之間的關係,可能從「下方」、「之下」變成「上方」、「之上」。此外,本文中所使用的空間上的相對敘述也應作同樣的解釋。
第1A圖繪示本揭示內容一實施方式之晶片封裝結構10的剖面示意圖。請參照第1A圖,晶片封裝結構10包括保護基板100、線路結構200、線路重佈結構300、導熱元件400、晶片500及散熱片600。
在一些實施例中,保護基板100為可撓性基板,例如聚醯亞胺(polyimide,PI)基板。在其他實施例中,保護基板100為剛性基板,例如玻璃基板或塑膠基板。
線路結構200設置於保護基板100上,並包括第一線路層211、第一介電層212及第一導電接觸件213。第一線路層211和第一導電接觸件213嵌置於第一介電層212中。詳細而言,第一線路層211的下表面與第一介電層212的下表面共平面。而第一導電接觸件213接觸第一線路層211,並且第一導電接觸件213的上表面暴露於第一介電層212外。在一些實施例中,第一線路層211包括任何導電材料,例如銅、鎳或銀等金屬。在一些實施例中,第一介電層212包括味之素構成膜(Ajinomoto Build-up Film,
ABF)、聚醯亞胺(Polyimide,PI)或光敏介電材料(photoimageable dielectric,PID)。在一些實施例中,第一導電接觸件213可為金屬柱,而金屬柱例如包括銅、鎳或銀等導電金屬。須說明的是,雖然第1A圖所繪示的線路結構200僅包括一層線路層(即第一線路層211),但在其他實施例中,線路結構200可包括兩層或兩層以上的線路層。
線路重佈結構300設置於線路結構200上,並包括第一線路重佈層310及設置於第一線路重佈層310上的第二線路重佈層320。
第一線路重佈層310包括第二線路層311、第二介電層312、第二導電接觸件313及連接墊314。第二線路層311和第二導電接觸件313嵌置於第二介電層312中。詳細而言,第二線路層311及連接墊314接觸第一導電接觸件213的暴露部分,從而第二線路層311及連接墊314與第一線路層211電性連接。第二線路層311的下表面與第二介電層312的下表面共平面。而第二導電接觸件313接觸第二線路層311,並且第二導電接觸件313的上表面暴露於第二介電層312外。在一些實施例中,第二線路層311及連接墊314包括任何導電材料,例如銅、鎳或銀等金屬。在一些實施例中,第二介電層312包括味之素構成膜、聚醯亞胺或光敏介電材料。在一些實施例中,第二導電接觸件313可為金屬柱,而金屬柱例如包括銅、鎳或銀等導電金屬。
第二線路重佈層320包括第三線路層321、第三
介電層322及第三導電接觸件323。第三線路層321和第三導電接觸件323嵌置於第三介電層322中。詳細而言,第三線路層321接觸第二導電接觸件313的暴露部分,從而第三線路層321與第二線路層311電性連接。第三線路層321的下表面與第三介電層322的下表面共平面。而第三導電接觸件323接觸第三線路層321,並且第三導電接觸件323的上表面暴露於第三介電層322外。在一些實施例中,第三線路層321包括任何導電材料,例如銅、鎳或銀等金屬。在一些實施例中,第三介電層322包括味之素構成膜、聚醯亞胺或光敏介電材料。在一些實施例中,第三導電接觸件323可為金屬柱,而金屬柱例如包括銅、鎳或銀等導電金屬。
如第1A圖所示,線路重佈結構300具有開口300a。具體地,第一線路重佈層310的一開口與第二線路重佈層320的一開口互相連通以形成開口300a,且開口300a暴露出連接墊314。須說明的是,雖然第1A圖所繪示的線路重佈結構300僅包括兩層線路層(即第二線路層311及第三線路層321),但在其他實施例中,線路重佈結構300可包括兩層以上的線路層。
導熱元件400設置於線路結構200上。具體地,導熱元件400具有水平部分410及垂直部分420。水平部分410的一部分嵌置於線路重佈結構300中,且水平部分410的另一部分被開口300a所暴露。垂直部分420由水平部分410嵌置於線路重佈結構300中的該部分向上延伸至超過線路重佈結構300的頂表面。在一實施方式中,導熱元件400
為一L型結構。關於導熱元件400的材料,可例如為任何導熱效果好的材料,例如銅、鎳或銀等金屬。
晶片500設置於開口300a中,並電性連接連接墊314。具體地,晶片500的下表面設置有多個金屬凸塊(例如晶片接腳),並且金屬凸塊經由焊接材料與連接墊314接合,從而晶片500與連接墊314電性連接。如第1A圖所示,晶片500的底部接觸導熱元件400的水平部分410的暴露部分,據此提供特定的技術效果,下文將詳細敘述。
散熱片600設置於線路重佈結構300及晶片500之上。具體地,散熱片600接觸晶片500的頂部。據此,當晶片500運作時,積存的廢熱可直接通過散熱片600導出,避免因廢熱囤積而產生的損害。在一實施方式中,散熱片600係經由一超音波熔接製程而黏接於晶片500的頂部。在此超音波熔接製程中,散熱片600的接觸面與晶片500的接觸面熔融而黏接,從而散熱片600與晶片500之間緊密接觸,提高了散熱效果。
如第1A圖所示,散熱片600還接觸導熱元件400的垂直部分420的頂部。如前所述,晶片500的底部接觸導熱元件400的水平部分410的暴露部分提供了特定的技術效果。具體而言,晶片積存的廢熱可通過導熱元件400而從晶片500的底部傳導到散熱片600,從而增加散熱效果。在一實施方式中,散熱片600係經由一超音波熔接製程而黏接於導熱元件400的垂直部分420的頂部。在此超音波熔接製程中,散熱片600的接觸面與導熱元件400的接觸面熔融
而黏接,從而散熱片600與導熱元件400之間緊密接觸,提高了散熱效果。
在一實施方式中,晶片封裝結構10進一步包括保護材料700。具體地,保護材料700覆蓋晶片500的側壁,並填充線路結構200與晶片500之間的空隙。因此,保護材料700可保護晶片500的金屬凸塊與第二線路層311之間的接合,從而避免剝離的情況發生。另一方面,保護材料700亦可阻隔水氣,並且避免金屬凸塊、焊接材料、以及第二線路層311的氧化。在一些實施例中,保護材料700包括樹脂,但不以此為限。
須說明的是,雖然第1A圖所繪示的晶片封裝結構10僅包括兩個導熱元件400,但應了解到在不同角度的其他視圖中,晶片封裝結構10可包括多個導熱元件400設置於晶片500的周圍。舉例來說,請同時參照第1B圖,第1B圖繪示本揭示內容一實施方式之晶片500與導熱元件400的俯視示意圖。在第1B圖的實施方式中,多個導熱元件400設置於晶片500的四個側邊,但不以此為限。例如,多個導熱元件400可僅設置於晶片500的兩個側邊或三個側邊。
導熱元件400的水平部分410與晶片500的接觸面A1如第1C圖所示。為了提供良好的散熱效果,所有接觸面A1的面積總和需5%晶片面積。
類似地,為了提供良好的散熱效果,導熱元件400的垂直部分420與散熱片600的接觸面具有一特定接觸面積(如第1B圖所示)。接觸總面積需接觸面A1的面積
總和。
值得一提的是,導熱元件400的垂直部分420與晶片500的一側壁具有一水平距離D1,且水平距離D1例如是50微米。當水平距離D1為50微米時,廢熱可橫向地直接穿透其他層(即保護材料700、第二介電層312或第三介電層322)傳導到導熱元件400,從而提高散熱效果。更具體地,晶片500的一側壁與第二介電層312及第三介電層322具有一水平距離D2,且水平距離D2<水平距離D1。
在一實施方式中,晶片封裝結構10進一步包括連接墊800。具體地,連接墊800設置於線路重佈結構300與散熱片600之間,並接觸散熱片600。此外,連接墊800接觸第三導電接觸件323的暴露部分,從而連接墊800與第三線路層321電性連接。在一些實施例中,連接墊800包括任何導電材料,例如銅、鎳或銀等金屬。
在一實施方式中,晶片封裝結構10進一步包括防焊層900。具體地,防焊層900設置於線路重佈結構300與散熱片600之間,並覆蓋連接墊800的側壁。在一些實施例中防焊層900包括綠漆,但不以此為限。
本揭示內容亦提供一種晶片封裝結構10的製造方法。第2圖~第10圖繪示本揭示內容一實施方式之晶片封裝結構10的製造方法的各個階段的剖面示意圖。
如第2圖所示,首先,形成第一線路層211於第基板100上。例如,形成導電材料於基板100上,並圖案化導電材料以形成第一線路層211。在一些實施例中,形成導
電材料的方式包括電鍍、化學氣相沉積、物理氣相沉積等,但不以此為限。接著,形成第一介電層212覆蓋第一線路層211,並且第一介電層212包括暴露出第一線路層211的一部分的導通孔212a。例如形成介電材料於第一線路層211上,並圖案化介電材料以形成導通孔212a。在一些實施例中,形成介電材料的方法包括化學氣相沉積、物理氣相沉積等,但不以此為限。在一些實施例中,圖案化導電材料和介電材料的方法包括沉積光阻於待圖案化層上,並經過曝光和顯影來形成圖案化光阻層。接著,使用此圖案化光阻層作為蝕刻遮罩來蝕刻待圖案化層。最後,移除圖案化光阻層。可代替地,在介電材料為光敏介電材料的實施例中,可藉由曝光和顯影來移除光敏介電材料的一部分以完成圖案化。
接下來,形成第二線路層311、連接墊314及導熱元件400的水平部分410於第一介電層212上,以及形成第一導電接觸件213於導通孔212a中。例如,形成導電材料於第一介電層212上,並填充於導通孔212a中。接著,圖案化導電材料以形成第二線路層311、連接墊314、導熱元件400的水平部分410及第一導電接觸件213。接下來,形成離型膜RF'覆蓋第二線路層311、連接墊314、導熱元件400的水平部分410及第一介電層212。
如第3圖所示,接著,對離型膜RF'進行圖案化以暴露出第二線路層311的一部分及導熱元件400的水平部分410的一部分,從而形成圖案化離型膜RF。
如第4圖所示,接著,形成第二介電層312c覆
蓋第二線路層311、導熱元件400的水平部分410及第一介電層212,並且第二介電層312c包括暴露出第二線路層311的一部分的導通孔312a。接下來,形成第三線路層321於第二介電層312c上,以及形成第二導電接觸件313於導通孔312a中。隨後,形成第三介電層322c覆蓋第三線路層321及第二介電層312c。
如第5圖所示,對第二介電層312c及第三介電層322c執行一圖案化製程,以形成第二介電層312b及第三介電層322b。具體地,第二介電層312b及第三介電層322b共同具有一穿孔TH暴露出導熱元件400的水平部分410。第三介電層322b還具有導通孔322a暴露出第三線路層321的一部分。
如第6圖所示,形成連接墊800於第三介電層322b上、形成第三導電接觸件323於導通孔322a中、以及形成導熱元件400的垂直部分420於穿孔TH中,從而形成前驅結構10a。例如,形成導電材料於第三介電層322b上,並填充於導通孔322a及穿孔TH中。接著,圖案化導電材料以形成連接墊800、第三導電接觸件323及導熱元件400的垂直部分420。具體地,前驅結構10a包括線路結構200、線路重佈前驅結構300b、導熱元件400及圖案化離型膜RF。
如第7圖所示,形成防焊層900'於第三介電層322b上,並且防焊層900'覆蓋連接墊800的側壁。
如第8圖所示,執行一雷射鑽孔製程,以移除位於圖案化離型膜RF的周邊的垂直投影方向上的第二介電層
312b的一部分及第三介電層322b的一部分,從而形成第二介電層312、第三介電層322及位於圖案化離型膜RF上方的介電層312d、322d。
如第9圖所示,撕除圖案化離型膜RF及位於圖案化離型膜RF上方的介電層312d、322d,從而形成開口300a,其中開口300a暴露出連接墊314及導熱元件400的水平部分410的一部分。
如第10圖所示,設置晶片500於開口300a中,使晶片500電性連接連接墊314,且晶片500的底部接觸導熱元件400的水平部分410的暴露部分。接著,形成保護材料700'覆蓋連接墊800、防焊層900'及晶片500的頂表面和側壁,並填充線路結構200與晶片500之間的空隙。
接下來,對保護材料700'及防焊層900'執行諸如化學機械研磨之一平坦化製程,以暴露出晶片500的頂部及導熱元件400的垂直部分420的頂部。接著,經由一超音波熔接製程來黏接散熱片600於晶片500及導熱元件400的垂直部分420上,從而形成第1A圖所示的晶片封裝結構10。
在一些實施例中,導熱元件400的垂直部分420可以兩段式方式來形成。具體而言,請參照第11圖~第12圖。第11圖接續第3圖,形成第二介電層312c覆蓋第二線路層311、導熱元件400的水平部分410及第一介電層212,並且第二介電層312c包括暴露出第二線路層311的一部分及導熱元件400的水平部分410的導通孔312a。接下來,形成第三線路層321於第二介電層312c上,以及形成第二導電接
觸件313及導熱元件400的垂直部分420"於導通孔312a中。隨後,形成第三介電層322c覆蓋第三線路層321、垂直部分420"及第二介電層312c。
如第12圖所示,對第三介電層322c執行一圖案化製程,以形成第三介電層322b。具體地,第三介電層322b具有一穿孔TH暴露出垂直部分420",且第三介電層322b還具有導通孔322a暴露出第三線路層321的一部分。接下來,形成導電材料於第三介電層322b上,並填充於導通孔322a及穿孔TH中,並圖案化導電材料以形成連接墊800、第三導電接觸件323及導熱元件400的垂直部分420,從而形成如第6圖所示的前驅結構10a。
由上述發明實施例可知,在此揭露的晶片封裝結構中,散熱片與晶片的頂部緊密接觸,提供良好的散熱效果。此外,晶片封裝結構還具有與散熱片緊密接觸的導熱元件,使得廢熱可從晶片底部通過導熱元件而傳導到散熱片,或者橫向地穿透其他層而通過導熱元件傳導到散熱片,從而提高散熱效果。
雖然本揭示內容已以實施方式揭露如上,但其他實施方式亦有可能。因此,所請請求項之精神與範圍並不限定於此處實施方式所含之敘述。
任何熟習此技藝者可明瞭,在不脫離本揭示內容的精神和範圍內,當可作各種之更動與潤飾,因此本揭示內容的保護範圍當視後附之申請專利範圍所界定者為準。
Claims (9)
- 一種晶片封裝結構,包括:一線路結構,包含一基板及一第一線路層,其中該基板具有相對的兩表面,該第一線路層設置於其中一表面上;一線路重佈結構,設置於該線路結構上,並包括與該第一線路層電性連接的一第二線路層,其中該線路重佈結構具有一開口;一導熱元件,設置於該線路結構上,並具有:一水平部分,具有一第一部分嵌置於該線路重佈結構中,以及一第二部分被該開口所暴露;以及一垂直部分,由該水平部分的該第一部分向上延伸至超過該線路重佈結構的一頂表面;一晶片,設置於該開口中,其中該晶片具有複數個電極墊,且該些電極墊設置於該晶片的一底部,並電性連接該第二線路層,其中該晶片的該底部接觸該導熱元件的該水平部分的該第二部分;以及一散熱片,設置於該線路重佈結構及該晶片之上,並接觸該晶片的一頂部及該導熱元件的該垂直部分的一頂部,其中該散熱片係經由一超音波熔接製程而黏接於該晶片的該頂部及該導熱元件的該垂直部分的該頂部。
- 如申請專利範圍第1項所述的晶片封裝結構,其中該導熱元件為一L型結構。
- 如申請專利範圍第1項所述的晶片封裝結構,進一步包括:一保護材料,覆蓋該晶片的一側壁,並填充該線路結構與該晶片之間的空隙。
- 一種晶片封裝結構,包括:一線路結構,包含一基板及一第一線路層,其中該基板具有相對的兩表面,該第一線路層設置於其中一表面上;一線路重佈結構,設置於該線路結構上,並包括與該第一線路層電性連接的一第二線路層,其中該線路重佈結構具有一開口;一導熱元件,設置於該線路結構上,並具有:一水平部分,具有一第一部分嵌置於該線路重佈結構中,以及一第二部分被該開口所暴露;以及一垂直部分,由該水平部分的該第一部分向上延伸至超過該線路重佈結構的一頂表面;一晶片,設置於該開口中,其中該晶片具有複數個電極墊,且該些電極墊設置於該晶片的一底部,並電性連接該第二線路層,其中該晶片的該底部接觸該導熱元件的該水平部分的該第二部分;以及一散熱片,設置於該線路重佈結構及該晶片之上,並接觸該晶片的一頂部及該導熱元件的該垂直部分的一頂部,其中該導熱元件的該垂直部分與該晶片的一側壁具有50微米的一水平距離。
- 一種晶片封裝結構,包括:一線路結構,包含一基板及一第一線路層,其中該基板具有相對的兩表面,該第一線路層設置於其中一表面上;一線路重佈結構,設置於該線路結構上,並包括與該第一線路層電性連接的一第二線路層,其中該線路重佈結構具有一開口;一導熱元件,設置於該線路結構上,並具有:一水平部分,具有一第一部分嵌置於該線路重佈結構中,以及一第二部分被該開口所暴露;以及一垂直部分,由該水平部分的該第一部分向上延伸至超過該線路重佈結構的一頂表面;一晶片,設置於該開口中,其中該晶片具有複數個電極墊,且該些電極墊設置於該晶片的一底部,並電性連接該第二線路層,其中該晶片的該底部接觸該導熱元件的該水平部分的該第二部分;一散熱片,設置於該線路重佈結構及該晶片之上,並接觸該晶片的一頂部及該導熱元件的該垂直部分的一頂部;以及一連接墊,設置於該線路重佈結構與該散熱片之間,並接觸該散熱片,其中該連接墊與該第二線路層電性連接。
- 一種晶片封裝結構的製造方法,包括下列操作:(i)提供一前驅結構,其中該前驅結構包括:一線路結構,包括一第一線路層;一線路重佈前驅結構,設置於該線路結構上,並包括與該第一線路層電性連接的一第二線路層;一導熱元件,設置於該線路結構上,並具有:一水平部分,嵌置於該線路重佈前驅結構中;以及一垂直部分,由該水平部分向上延伸至超過該線路重佈前驅結構的一頂表面;以及一圖案化離型膜,設置於該線路結構上,並被該線路重佈前驅結構所覆蓋,其中該圖案化離型膜覆蓋該該導熱元件的該水平部分的一部分及與該第一線路層電性連接的一連接墊;(ii)移除該圖案化離型膜及位於該圖案化離型膜上方的該線路重佈前驅結構的一部分,以形成一開口,其中該開口暴露出該導熱元件的該水平部分的該部分及該連接墊;(iii)設置一晶片於該開口中,其中該晶片電性連接該連接墊,且該晶片的一底部接觸該導熱元件的該水平部分的該部分;以及(iv)黏接一散熱片於該晶片及該導熱元件的該垂直部分上。
- 如申請專利範圍第6項所述的晶片封裝結構的製造方法,其中操作(iv)係經由一超音波熔接製程來執行。
- 如申請專利範圍第6項所述的晶片封裝結構的製造方法,其中操作(ii)包括下列步驟:(a)使用一雷射鑽孔製程移除位於該圖案化離型膜的一周邊的一垂直投影方向上的該線路重佈前驅結構的一部分;以及(b)撕除該圖案化離型膜及位於該圖案化離型膜上方的該線路重佈前驅結構的該部分。
- 如申請專利範圍第6項所述的晶片封裝結構的製造方法,其中操作(i)包括下列步驟:(v)形成該導熱元件的該水平部分於該線路結構上;(vi)形成該線路重佈前驅結構覆蓋該導熱元件的該水平部分;(vii)圖案化該線路重佈前驅結構以形成一穿孔暴露出該導熱元件的該水平部分的一部分;以及(viii)形成該導熱元件的該垂直部分於該穿孔中。
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US11282791B2 (en) * | 2019-06-27 | 2022-03-22 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device having a heat dissipation structure connected chip package |
TWI720921B (zh) * | 2020-07-14 | 2021-03-01 | 欣興電子股份有限公司 | 內埋式元件結構及其製造方法 |
KR20220042705A (ko) | 2020-09-28 | 2022-04-05 | 삼성전자주식회사 | 반도체 패키지 및 반도체 패키지의 제조 방법 |
WO2022222015A1 (en) * | 2021-04-20 | 2022-10-27 | Huawei Technologies Co., Ltd. | Semiconductor package |
TWI777741B (zh) | 2021-08-23 | 2022-09-11 | 欣興電子股份有限公司 | 內埋元件基板及其製作方法 |
TWI791342B (zh) | 2021-11-30 | 2023-02-01 | 財團法人工業技術研究院 | 異質整合半導體封裝結構 |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TW201110250A (en) * | 2009-09-04 | 2011-03-16 | Unimicron Technology Corp | Package substrate structure and method of forming same |
TW201509338A (zh) * | 2013-04-03 | 2015-03-16 | Babyak Holdings LLC | 可移除式珠寶底座 |
TW201824471A (zh) * | 2016-09-29 | 2018-07-01 | 南韓商三星電子股份有限公司 | 扇出型半導體封裝 |
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TWI231017B (en) | 2003-08-18 | 2005-04-11 | Advanced Semiconductor Eng | Heat dissipation apparatus for package device |
US20080023805A1 (en) * | 2006-07-26 | 2008-01-31 | Texas Instruments Incorporated | Array-Processed Stacked Semiconductor Packages |
US8927339B2 (en) * | 2010-11-22 | 2015-01-06 | Bridge Semiconductor Corporation | Method of making thermally enhanced semiconductor assembly with bump/base/flange heat spreader and build-up circuitry |
US8632221B2 (en) | 2011-11-01 | 2014-01-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | LED module and method of bonding thereof |
KR102425753B1 (ko) * | 2015-06-01 | 2022-07-28 | 삼성전기주식회사 | 인쇄회로기판, 인쇄회로기판의 제조 방법 및 이를 포함하는 반도체 패키지 |
KR20170112363A (ko) * | 2016-03-31 | 2017-10-12 | 삼성전기주식회사 | 전자부품 패키지 및 그 제조방법 |
TWI622149B (zh) | 2017-01-03 | 2018-04-21 | 力成科技股份有限公司 | 封裝結構的製造方法 |
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TW201110250A (en) * | 2009-09-04 | 2011-03-16 | Unimicron Technology Corp | Package substrate structure and method of forming same |
TW201509338A (zh) * | 2013-04-03 | 2015-03-16 | Babyak Holdings LLC | 可移除式珠寶底座 |
TW201824471A (zh) * | 2016-09-29 | 2018-07-01 | 南韓商三星電子股份有限公司 | 扇出型半導體封裝 |
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US20210159142A1 (en) | 2021-05-27 |
TW202017126A (zh) | 2020-05-01 |
US20200126883A1 (en) | 2020-04-23 |
US10943846B2 (en) | 2021-03-09 |
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