TWI666747B - 具有薄化基底的封裝件及其形成方法 - Google Patents

具有薄化基底的封裝件及其形成方法 Download PDF

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Publication number
TWI666747B
TWI666747B TW106126399A TW106126399A TWI666747B TW I666747 B TWI666747 B TW I666747B TW 106126399 A TW106126399 A TW 106126399A TW 106126399 A TW106126399 A TW 106126399A TW I666747 B TWI666747 B TW I666747B
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Taiwan
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metal
substrate
under
bump
polymer layer
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TW106126399A
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TW201826479A (zh
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余振華
蔡仲豪
王垂堂
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台灣積體電路製造股份有限公司
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Abstract

一種封裝件，其包括：基底、穿透所述基底的凸塊下金 屬(UBM)、位於所述凸塊下金屬之上並接觸所述凸塊下金屬的焊料區、以及位於所述基底之下的內連線結構。所述內連線結構經由所述凸塊下金屬而電性耦接至所述焊料區。元件晶粒位於所述內連線結構之下並接合至所述內連線結構。所述元件晶粒經由所述凸塊下金屬及所述內連線結構而電性耦接至所述焊料區。所述元件晶粒包封於包封材料中。

Description

具有薄化基底的封裝件及其形成方法
本發明實施例是有關於一種具有薄化基底的封裝件及其形成方法。
在封裝積體電路時，可在其中包括多個插入器(interposer)的插入器晶圓上接合多個元件晶粒。所述插入器包括矽穿孔(Through-Silicon Via，TSV)。在接合所述元件晶粒之後，將底部填充物(underfill)分配至所述元件晶粒與所述插入器晶圓之間的空隙中。接著，可進行固化(curing)製程來固化所述底部填充物。可施加模製化合物(molding compound)以將元件晶粒包封於所述模製化合物中。接著，將所得的插入器晶圓及位於其上的頂部晶粒鋸割成多個封裝件，所述多個封裝件包括例如焊料球等裸露出的電性連接件。接著，將所述封裝件接合至封裝件基底或印刷電路板。
根據本發明的一些實施例，一種封裝件包括基底、穿透 所述基底的凸塊下金屬(Under-Bump Metallurgy，UBM)、位於所述凸塊下金屬之上並接觸所述凸塊下金屬的焊料區、以及位於所述基底之下的內連線結構。所述內連線結構經由所述凸塊下金屬而電性耦接至所述焊料區。元件晶粒位於所述內連線結構之下並接合至所述內連線結構。所述元件晶粒經由所述凸塊下金屬及所述內連線結構而電性耦接至所述焊料區。所述元件晶粒包封於包封材料中。
根據本發明的一些實施例，一種封裝件包括半導體基底、位於所述半導體基底之下並接觸所述半導體基底的介電層、以及位於所述介電層之下的內連線結構。所述內連線結構包括與所述介電層的底表面接觸的金屬墊。開口穿透所述半導體基底及所述介電層。聚合物層包括與所述半導體基底重疊的第一部分及延伸至所述開口內以接觸所述金屬墊的第二部分。金屬特徵自所述聚合物層的所述第一部分的頂表面延伸至所述金屬墊。所述金屬特徵被所述聚合物層環繞。
根據本發明的一些實施例，一種形成封裝件的方法包括將元件晶粒接合至晶圓。所述晶圓包括基底及內連線結構。所述方法更包括：對所述基底進行薄化；對所述基底進行蝕刻以在所述基底中形成開口，其中所述內連線結構中的金屬墊經由所述開口而裸露出；形成聚合物層以覆蓋所述基底，其中所述聚合物層延伸至所述開口內以覆蓋所述金屬墊；對所述聚合物層進行蝕 刻，以裸露出所述金屬墊；以及形成上覆於所述聚合物層上的金屬特徵。所述金屬特徵延伸至所述開口內以接觸所述金屬墊。
20A、20B‧‧‧元件晶粒
22、40‧‧‧焊料區
26‧‧‧包封材料
28‧‧‧開口
32、174、178‧‧‧聚合物層
34‧‧‧光阻
38‧‧‧凸塊下金屬
38’‧‧‧虛線
38A‧‧‧頂部部分
38B‧‧‧側壁部分
38C‧‧‧底部部分
42‧‧‧晶圓級封裝件
44、50‧‧‧封裝件
46‧‧‧封裝件組件
48‧‧‧底部填充物
52‧‧‧台階
100‧‧‧晶圓
120‧‧‧基底
120A‧‧‧頂表面
122‧‧‧主動元件
124、162‧‧‧介電層
126、138、148‧‧‧蝕刻終止層
128‧‧‧接觸插塞
130、146‧‧‧介電層
132‧‧‧導電線
132A、132B‧‧‧導電特徵
134‧‧‧擴散阻障層
136‧‧‧含銅材料
140、150‧‧‧金屬間介電層
142‧‧‧通孔
143‧‧‧擴散阻障
144‧‧‧導電線
145‧‧‧導電材料
152‧‧‧通孔
154‧‧‧導電特徵
164‧‧‧通孔
166‧‧‧金屬凸塊
168、171‧‧‧鈍化層
169‧‧‧凸塊下金屬
170‧‧‧內連線結構
172‧‧‧金屬墊
176‧‧‧後鈍化內連線
202、204、206、208、210、212、214、216、218、220、222‧‧‧步驟
T1、T2、T3、T4‧‧‧厚度
W1‧‧‧底部寬度
W2‧‧‧頂部寬度
結合附圖閱讀以下詳細說明，會最佳地理解本發明的各個態樣。應注意，根據本產業中的標準實務，各種特徵並非按比例繪製。事實上，為論述清晰起見，可任意增大或減小各種特徵的尺寸。
圖1至圖9A為根據一些實施例所繪示的形成一種包括穿透基底的凸塊下金屬(UBM)的封裝件的中間階段的剖面圖。
圖9B及圖9C為根據一些實施例所繪示的一種包括穿透相應基底的凸塊下金屬的封裝件的剖面圖。
圖10A及圖10B為根據一些實施例所繪示的一種包括基底的部分晶圓的更詳細的圖示。
圖11為根據一些實施例所繪示的一種用於形成封裝件的製程流程。
以下揭露內容提供用於實現本發明的不同特徵的諸多不同的實施例或實例。以下闡述組件及排列的具體實例以簡化本揭露內容。當然，這些僅為實例且不旨在進行限制。舉例而言，以下說明中將第一特徵形成於第二特徵「之上」或第二特徵「上」 可包括其中第一特徵及第二特徵被形成為直接接觸的實施例，且亦可包括其中第一特徵與第二特徵之間可形成有附加特徵、進而使得所述第一特徵與所述第二特徵可能不直接接觸的實施例。另外，本揭露內容可能在各種實例中重複參考編號及/或字母。此種重複是出於簡潔及清晰的目的，而不是自身表示所論述的各種實施例及/或配置之間的關係。
此外，為易於說明，本文中可能使用例如「之下(underlying)」、「下面(below)」、「下部的(lower)」、「上覆(overlying)」、「上部的(upper)」等空間相對性用語來闡述圖中所示的一個構件或特徵與另一(其他)構件或特徵的關係。所述空間相對性用語旨在除圖中所繪示的定向外亦囊括元件在使用或操作中的不同定向。設備可具有其他定向(旋轉90度或處於其他定向)且本文中所用的空間相對性描述語可同樣相應地進行解釋。
根據各種示例性實施例提供一種包括穿透基底的凸塊下金屬(UBM)的封裝件及其形成方法。討論了一些實施例的一些變型。在各個圖及說明性實施例通篇中，相同的參考編號用於表示相同的構件。
圖1至圖9A根據一些實施例所繪示的一種形成封裝件的中間階段的剖面圖。圖1至圖9A中所示出的步驟亦在圖11中所示出的製程流程中示意性地說明。
圖1說明晶圓100的剖面圖，晶圓100可具有圓形俯視 圖形狀。根據一些實施例，晶圓100中無(free from)例如電晶體及二極體等主動元件，且可無或可包括例如電容器、電感器、電阻器等被動元件。根據本發明的替代實施例，晶圓100為可包括或可不包括主動元件及/或被動元件的元件晶圓。
圖10A說明晶圓100的一部分的更詳細的圖示。晶圓100包括基底120。根據本發明的一些實施例，基底120為例如由晶體矽形成的矽基底等半導體基底。根據替代實施例，基底120是由介電基底形成，所述介電基底例如為可由SiO2、矽石玻璃(Silica glass)、硼矽酸鹽玻璃(Borosilicate glass，BSG)、石英、或無鹼玻璃(Alkaline-free glass)形成的玻璃基底等。
以下簡要論述晶圓100的形成。首先，在基底120上形成主動元件122(若有的話)及介電層124。根據其中形成有主動元件122的一些實施例，介電層124是層間介電(Inter-Layer Dielectric，ILD)。用於形成介電層124的示例性材料包括(但不限於)磷矽酸鹽玻璃(phosphosilicate glass，PSG)、硼矽酸鹽玻璃(BSG)、摻雜硼的磷矽酸鹽玻璃(boron-doped phosphosilicate glass，BPSG)、摻雜氟的矽酸鹽玻璃(fluorine-doped silicate glass，FSG)、正矽酸四乙酯(tetraethyl orthosilicate，TEOS)等。介電層124亦可由氧化矽、氮化矽、氮氧化矽、碳化矽等形成。可使用旋塗(spin-on coating)、流動式化學氣相沉積(Flowable Chemical Vapor Deposition，FCVD)等來形成介電層124。根據本發明的替 代實施例，使用例如電漿增強型化學氣相沉積(Plasma Enhanced Chemical Vapor Deposition，PECVD)、低壓化學氣相沉積(Low Pressure Chemical Vapor Deposition，LPCVD)等沉積方法來形成介電層124。
根據其中形成有主動元件122的一些實施例，在介電層124中形成接觸插塞(contact plugs)128，並使用接觸插塞128將主動元件122電性連接至上覆的金屬線及通孔(vias)。根據本發明的一些實施例，接觸插塞128是由選自鎢、鋁、銅、鈦、鉭、氮化鈦、氮化鉭、其合金、及/或其多層的導電材料形成。根據替代實施例，不形成主動元件，且不在介電層124中形成接觸插塞。
接下來，在基底120及介電層124之上形成內連線結構(interconnect structure)170。相應步驟被示為圖11中所示出的製程流程中的步驟202。可在介電層124之上形成蝕刻終止層126。蝕刻終止層126可由碳化矽、氮化矽、氮氧化矽、氮碳化矽等形成。蝕刻終止層126亦由相對於上覆的介電層130具有高蝕刻選擇性的材料形成，且因此蝕刻終止層126可用於終止對介電層130進行的蝕刻。
圖10A中進一步說明介電層130，介電層130在下文中被另外稱為金屬間介電(Inter-Metal Dielectric，IMD)層130。根據本發明的一些實施例，金屬間介電層130是由介電常數(k值)低於約3.0、約2.5、或甚至更低的低k介電材料形成。金屬間介 電層130可由黑金剛石(Black Diamond)(應用材料公司的註冊商標)、含碳低k介電材料、氫矽倍半氧烷(Hydrogen SilsesQuioxane，HSQ)、甲基矽倍半氧烷(MethylSilsesQuioxane，MSQ)等形成。根據替代實施例，金屬間介電層130是由例如氧化矽、氮化矽、碳化矽、氮氧化矽等非低k介電材料形成。
在金屬間介電層130中形成導電線(或墊)132(包括導電特徵132A及132B，統稱為132)。根據一些實施例，導電線132包括擴散阻障層134及位於擴散阻障層134之上的含銅材料136。擴散阻障層134可包含鈦、氮化鈦、鉭、氮化鉭等，且具有防止含銅材料136中的銅擴散至金屬間介電層130中的功能。導電線132在下文中亦被稱為金屬線或金屬墊。導電線132的形成可包括單鑲嵌(single damascene)製程。
在金屬間介電層130及導電線132之上形成蝕刻終止層138及金屬間介電層140。根據本申請案的一些實施例，蝕刻終止層138是由選自碳化矽、氮化矽、氮氧化矽、氮碳化矽等的介電材料形成。金屬間介電層140可由低k介電材料或非低k介電材料形成，且金屬間介電層140的材料可選自與用於形成金屬間介電層130的候選材料相同的群組。
形成導電通孔142及導電線144以電性耦接至導電線132。根據本發明的一些實施例，通孔142及導電線144的形成包括在金屬間介電層140及蝕刻終止層138中形成通孔開口及溝 渠、進行毯覆沉積(blanket deposition)以形成擴散阻障143、沉積銅或銅合金的薄晶種層(圖中未示出)、以及藉由例如電鍍(electro-plating)、無電鍍敷(electro-less plating)、沉積等以導電材料145填充通孔開口及溝渠的剩餘部分。擴散阻障143可由鈦、氮化鈦、鉭、氮化鉭、或其他替代材料形成。導電材料145可包括銅、銅合金、銀、金、鎢、鋁等。進行例如化學機械研磨(chemical mechanical polishing，CMP)等平坦化步驟以使擴散阻障143及導電材料145的表面平化(level)，並自金屬間介電層140的頂表面移除多餘的材料。
圖10A亦示意性地說明更多的介電(金屬間介電)層146及介電層146中的相應導電線及通孔(圖中未示出)的形成。基於晶圓100的佈線要求而確定金屬間介電層146的數目，且根據一些示例性實施例，金屬間介電層146的數目可介於0至7或以上。金屬間介電層146的數目等於0意味著後續形成的蝕刻終止層148及金屬間介電層150直接形成於金屬間介電層140之上且蝕刻終止層148及金屬間介電層150與金屬間介電層140之間不存在附加的介電層及導電線。金屬間介電層146中的導電線及通孔(圖中未示出)電性耦接至主動元件122。
在介電層146之上形成蝕刻終止層148及金屬間介電層150。根據本申請案的一些實施例，蝕刻終止層148是由選自與用於形成蝕刻終止層126的候選材料相同的群組的介電材料形成， 其中所述候選材料可包括碳化矽、氮化矽、氮氧化矽、氮碳化矽等。金屬間介電層150亦可由低k介電材料或非低k介電材料形成，且金屬間介電層150的材料可選自與用於形成金屬間介電層130及140的候選材料相同的群組。
在金屬間介電層150中形成通孔152及導電特徵154。通孔152及導電特徵154的材料可選自與用於形成通孔142及導電線144者相同的候選材料。所述形成製程亦相似於通孔142及導電線144的形成，且因此本文中不再對其予以贅述。導電特徵154包括導電墊且可能包括導電線。如圖10A中所示，通孔142及152可具有底部寬度小於相應的頂部寬度的錐形輪廓(tapered profile)。儘管圖中未示出，然而通孔142及152亦可具有上部寬度大於相應的下部寬度的錐形輪廓。
在金屬間介電層150之上形成介電層162。根據本發明的一些實施例，介電層162是由例如未經摻雜的矽酸鹽玻璃(Undoped Silicate Glass，USG)、氧化矽、氮化矽、氮氧化矽等非低k介電材料形成。
形成金屬通孔164及金屬凸塊166。根據本發明的一些實施例，通孔164及金屬凸塊166是由銅、鎳、或另一種金屬或金屬合金形成，且可或可不包括擴散阻障層。金屬通孔164及金屬凸塊166亦可包括凸塊下金屬169。金屬通孔164延伸至介電層162中以電性連接至導電特徵154。因此，金屬凸塊166經由多個 導電特徵而電性耦接至導電特徵132A。在本說明通篇中，介電層126及162以及位於介電層126與介電層162之間的介電層、以及該些介電層中的導電特徵被統一稱為內連線結構170。圖中未示出連接至主動元件122(若存在)的導電特徵，但當形成有主動元件122時可形成所述導電特徵。
圖10B根據替代實施例說明晶圓100的剖面圖。在該些實施例中，在金屬間介電層150之上形成鈍化層168，鈍化層168為介電層。在鈍化層168之上形成金屬墊172，且將金屬墊172經由金屬線及通孔而電性耦接至導電特徵132A。金屬墊172可為鋁墊或鋁銅墊，且可使用其他金屬材料。
形成鈍化層171以覆蓋金屬墊172的邊緣部分，且金屬墊172的中心部分經由鈍化層171中的開口而裸露出。鈍化層168及171中的每一者可為單層或複合層，且可由非低k介電材料形成。根據本發明的一些實施例，鈍化層168及171中的一者或鈍化層168及171二者為複合層，所述複合層包括氧化矽層(圖中未示出)及位於所述氧化矽層之上的氮化矽層(圖中未示出)。
在鈍化層171之上形成聚合物層174。聚合物層174可由例如聚醯亞胺(polyimide)、聚苯並噁唑(PolyBenzOxazole，PBO)、苯並環丁烯(BenzoCycloButene，BCB)等聚合物形成。將聚合物層174圖案化而形成後鈍化內連線(Post-Passivation Interconnect，PPI)176，後鈍化內連線176包括上覆於聚合物層 174上的第一部分及延伸至聚合物層174中以電性耦接至金屬墊172的第二部分。在聚合物層174之上形成聚合物層178。聚合物層178可由聚醯亞胺或其他聚合物系材料(例如聚苯並噁唑或苯並環丁烯)形成。金屬通孔164延伸至聚合物層178中以接觸後鈍化內連線176，金屬通孔164可包括凸塊下金屬169的下部部分及形成金屬凸塊166的金屬的下部部分。
重新參照圖1，使用覆晶接合(flip-chip bonding)將多個元件晶粒20A及20B(統稱為元件晶粒20)經由焊料區22接合至晶圓100。相應步驟被示為圖11中所示製程流程中的步驟204。元件晶粒20可包括邏輯晶粒及/或記憶體晶粒。所述邏輯晶粒可包括中央處理單元(Central Processing Unit，CPU)晶粒、微控制單元(Micro Control Unit，MCU)晶粒、輸入-輸出(Input-output，IO)晶粒、基帶(BaseBand，BB)晶粒、或應用處理器(Application processor，AP)晶粒。所述記憶體晶粒可包括快閃(flash)晶粒、靜態隨機存取記憶體(Static Random Access Memory，SRAM)晶粒、動態隨機存取記憶體(Dynamic Random Access Memory，DRAM)晶粒、低功率雙倍資料速率(Double-Data-Rate，DDR)晶粒、高帶寬記憶體(High Bandwidth Memory，HBM)等。
參照圖2，將元件晶粒20包封於包封材料26中。相應步驟被示為圖11中所示製程流程中的步驟206。分配包封材料26並接著例如在熱固化(thermal curing)製程中將包封材料26固化。 包封材料26填充元件晶粒20之間的空隙。包封材料26可包括模製化合物、模製底部填充物、環氧樹脂、或樹脂。包封材料26亦可包括由例如Al2O3形成的填料顆粒(filler particle)。在所述包封之後，包封材料26的頂表面可高於元件晶粒20或與元件晶粒20實質上共面。
圖3說明晶圓100的薄化，其中自基底120的背側(所示的頂側)研磨基底120。相應步驟被示為圖11中所示製程流程中的步驟208。因此，基底120的厚度自厚度T1減小至厚度T2。虛線代表基底120的在研磨期間被移除的部分。根據本發明的一些實施例，薄化基底120的厚度T2介於約2微米(μm)至約20微米之間的範圍內。
參照圖4，自背側蝕刻晶圓100以形成開口28，以便裸露出導電特徵132A。相應步驟被示為圖11中所示製程流程中的步驟210。導電特徵132A的所裸露出的部分可為金屬墊。可使用導電特徵132A作為蝕刻終止層來進行所述蝕刻。根據本發明的一些實施例，開口28的邊緣略微傾斜，其中由於蝕刻是自頂側進行，因此底部寬度W1小於頂部寬度W2。
接下來，參照圖5，形成聚合物層32來作為毯覆層(blanket layer)，以覆蓋基底120及所裸露出的導電特徵132A。相應步驟被示為圖11中所示製程流程中的步驟212。聚合物層32的厚度可介於例如約2微米至約4微米之間的範圍內。聚合物層 32穿透基底120並環繞後續形成的凸塊下金屬或凸塊，且因此有助於減小所得封裝件中的應力。根據一些實施例，聚合物層32是由聚醯亞胺、聚苯並噁唑、苯並環丁烯等形成。聚合物層32可為實質上共形的層，其中水平部分的厚度T3與垂直部分的厚度T4之間的差小於例如約厚度T3及厚度T4二者的30%。
圖6A根據本發明一些實施例說明聚合物層32的圖案化。相應步驟被示為圖11中所示製程流程中的步驟214。例如，當聚合物層32是由例如聚醯亞胺等光敏性材料形成時，可藉由對聚合物層32曝光及顯影來進行微影(photo lithography)製程。根據其中聚合物層32是由非光敏性的材料形成的替代實施例，將聚合物層32圖案化包括施加光阻34並藉由曝光及顯影將光阻34圖案化、以及使用經圖案化的光阻34作為蝕刻罩幕來蝕刻聚合物層32。接著移除光阻34。
根據一些實施例，如圖6A中所示，移除開口28中聚合物層32的實質上所有水平部分，以使導電特徵132與後續形成的凸塊下金屬之間的接觸面積最大化。剩餘的聚合物層32覆蓋基底120的側壁及介電層124的側壁。根據替代實施例，如圖6B中所示，為了提供充足的製程裕度(process margin)給未對準(misalignment)情況，聚合物層32中的開口小於相應的開口28。因此，聚合物層32的剩餘部分包括位於開口28的底部處的水平部分，其中剩餘的水平部分在實體上接觸導電特徵132A的頂表 面。
參照圖7，形成凸塊下金屬38以使凸塊下金屬38延伸至開口28內。相應步驟被示為圖11中所示製程流程中的步驟216。凸塊下金屬38被聚合物層32的相應接觸部分環繞。凸塊下金屬38是由例如金屬或金屬合金等導電材料形成。凸塊下金屬38可由銅層或包括鈦層及位於所述鈦層之上的銅層的複合層形成。根據本發明的一些實施例，凸塊下金屬38填充開口28的底部部分，且不填充開口28的頂部部分。舉例而言，凸塊下金屬38包括位於聚合物層32的頂表面之上的頂部部分38A、位於開口28的側壁上的側壁部分38B以及位於開口28的底部處的底部部分38C。底部部分38C亦可具有實質上平坦的頂表面。底部部分38C的頂表面亦可高於基底120的頂表面120A、實質上與基底120的頂表面120A共面、或低於基底120的頂表面120A，其中虛線38’示意性地代表凸塊下金屬38的頂表面的若干可能位置。如圖7中所示，視開口28的長寬比及形成凸塊下金屬38的製程而定，凸塊下金屬38可具有凹槽(recesses)，或可實質上無凹槽。此外，凸塊下金屬38可完全填充開口28，且因此形成金屬凸塊。
根據一些實施例，形成凸塊下金屬38的步驟包括：毯覆沉積毯覆凸塊下金屬層，並使用經圖案化的光阻(圖中未示出)作為蝕刻罩幕蝕刻所述毯覆凸塊下金屬層的非期望部分，進而留下凸塊下金屬38，如圖7中所示。根據替代實施例，形成凸塊下 金屬38的步驟包括：沉積晶種層，所述晶種層可為銅層或可包括鈦層及位於所述鈦層之上的銅層；在晶種層之上形成圖案化罩幕(圖中未示出)；在晶種層的經由圖案化罩幕中的開口而裸露出的部分上鍍敷金屬材料；移除圖案化罩幕；以及蝕刻晶種層的被所移除的圖案化罩幕覆蓋的部分。
圖8說明焊料區40的形成。相應步驟被示為圖11中所示製程流程中的步驟218。形成方法可包括在凸塊下金屬38上落下焊料球、以及對所述焊料球進行回焊以形成焊料區40。作為另外一種選擇，藉由印刷焊料膏(solder paste)、隨後進行回焊來形成焊料區40。根據一些實施例，焊料區40具有低於基底120的頂表面120A的底部部分。換言之，焊料區40可具有位於基底120中的底部部分(但被聚合物層32及凸塊下金屬38的位於基底120中的部分環繞)。在本說明通篇中，圖8中所示結構被稱為晶圓級封裝件(wafer-level package)42。
接下來，在晶粒鋸割(die-saw)製程中將晶圓級封裝件42單體化(singulate)，且將晶圓級封裝件42分割成多個封裝件44。相應步驟被示為圖11中所示製程流程中的步驟220。如圖9A中所示，接著將封裝件44接合至封裝件組件46以形成封裝件50。相應步驟被示為圖11中所示製程流程中的步驟222。根據一些實施例，封裝件組件46為封裝件基底。根據替代實施例，封裝件組件46為印刷電路板(Printed Circuit Board，PCB)。根據一些示例 性實施例，底部填充物48安置於封裝件44與封裝件組件46之間。
圖9B根據本發明一些實施例說明封裝件50。根據該些實施例，形成凸塊下金屬38以完全填充開口28(圖4)，且凸塊下金屬38的頂表面可高於或低於聚合物層32的頂表面。
圖9C根據本發明一些實施例說明封裝件50，其中將聚合物層32形成為具有如圖6B中所示的形狀，且凸塊下金屬38包括位於開口28的底部處的水平部分。因此，如圖9C中所示，凸塊下金屬38可形成台階(step)52來作為底部部分。
本發明的實施例具有一些有益特徵。根據本發明的實施例，所述基底餘留於最終的封裝件中以提供機械支撐。所述基底自背側被研磨成非常薄，且因此可形成凸塊下金屬來作為貫穿基底連接(through-substrate connection)。由於凸塊下金屬的長度減小，因此電性路徑得以減小。此外，由於基底的厚度減小，因此封裝件的熱效能得以提高。另外，穿透基底的聚合物層有助於減小所得封裝件中的應力。
根據本發明的一些實施例，一種封裝件包括基底、穿透所述基底的凸塊下金屬(UBM)、位於所述凸塊下金屬之上並接觸所述凸塊下金屬的焊料區、以及位於所述基底之下的內連線結構。所述內連線結構經由所述凸塊下金屬而電性耦接至所述焊料區。元件晶粒位於所述內連線結構之下並接合至所述內連線結構。所述元件晶粒經由所述凸塊下金屬及所述內連線結構而電性 耦接至所述焊料區。所述元件晶粒包封於包封材料中。
在上述封裝件中，更包括位於所述基底之下並接觸所述基底的介電層，且所述內連線結構包括位於所述介電層之下的導電特徵，其中所述凸塊下金屬穿透所述介電層而接觸所述導電特徵。
在上述封裝件中，更包括環繞所述凸塊下金屬的聚合物層，其中所述聚合物層穿透所述基底。
在上述封裝件中，所述聚合物層包括直接在所述凸塊下金屬之下延伸的水平部分。
在上述封裝件中，所述焊料區包括與所述基底的一部分處於同一水平高度(at the same level)的部分。
在上述封裝件中，所述基底是半導體基底。
在上述封裝件中，所述基底是玻璃基底。
在上述封裝件中，所述凸塊下金屬包括底部部分，所述底部部分具有與所述焊料區的底表面接觸的頂表面，其中所述凸塊下金屬的所述底部部分的所述頂表面低於所述基底的頂表面。
根據本發明的一些實施例，一種封裝件包括半導體基底、位於所述半導體基底之下並接觸所述半導體基底的介電層、以及位於所述介電層之下的內連線結構。所述內連線結構包括與所述介電層的底表面接觸的金屬墊。開口穿透所述半導體基底及所述介電層。聚合物層包括與所述半導體基底重疊的第一部分及 延伸至所述開口內以接觸所述金屬墊的第二部分。金屬特徵自所述聚合物層的所述第一部分的頂表面延伸至所述金屬墊。所述金屬特徵被所述聚合物層環繞。
在上述封裝件中，所述金屬特徵具有錐形輪廓，所述金屬特徵的上部寬度大於所述金屬特徵的相應的下部寬度。
在上述封裝件中，更包括位於所述金屬特徵之上並接觸所述金屬特徵的焊料區。
在上述封裝件中，所述焊料區的一部分低於所述半導體基底的頂表面。
在上述封裝件中，所述聚合物層包括具有實質上水平的頂表面的部分，所述具有實質上水平的頂表面的部分與所述金屬特徵的一部分的底表面接觸。
在上述封裝件中，所述內連線結構包括：通孔，位於所述金屬墊之下，其中所述通孔具有頂部寬度以及較所述頂部寬度大的底部寬度。
根據本發明的一些實施例，一種方法包括將元件晶粒接合至晶圓。所述晶圓包括基底及內連線結構。所述方法更包括：對所述基底進行薄化；對所述基底進行蝕刻以在所述基底中形成開口，其中所述內連線結構中的金屬墊經由所述開口而裸露出；形成聚合物層以覆蓋所述基底，其中所述聚合物層延伸至所述開口內以覆蓋所述金屬墊；對所述聚合物層進行蝕刻，以裸露出所 述金屬墊；以及形成上覆於所述聚合物層上的金屬特徵。所述金屬特徵延伸至所述開口內以接觸所述金屬墊。
在上述方法中，所述形成所述金屬特徵包括形成凸塊下金屬(UBM)，所述凸塊下金屬包括與所述聚合物層的一部分重疊的第一部分以及位於所述開口中的第二部分。
在上述方法中，更包括形成位於所述金屬特徵之上並接觸所述金屬特徵的焊料區，其中所述焊料區具有延伸至所述基底中的所述開口內的部分。
在上述方法中，更包括將封裝件組件接合至所述焊料區。
在上述方法中，所述對所述基底進行蝕刻包括對半導體基底進行蝕刻。
在上述方法中，所述對所述基底進行蝕刻包括對玻璃基底進行蝕刻。
以上概述了若干實施例的特徵，以使熟習此項技術者可更佳地理解本發明的各個態樣。熟習此項技術者應知，他們可容易地使用本發明作為設計或修改其他製程及結構的基礎來施行與本文中所介紹的實施例相同的目的及/或達成與本文中所介紹的實施例相同的優點。熟習此項技術者亦應認識到，該些等效構造並不背離本發明的精神及範圍，而且他們可在不背離本發明的精神及範圍的條件下對其作出各種改變、代替以及變更。

Claims (10)

  1. 一種封裝件，包括：基底；凸塊下金屬，穿透所述基底；焊料區，位於所述凸塊下金屬之上並接觸所述凸塊下金屬；內連線結構，位於所述基底之下，其中所述內連線結構經由所述凸塊下金屬而電性耦接至所述焊料區；聚合物層，環繞所述凸塊下金屬，其中所述聚合物層穿透所述基底，且所述聚合物層和所述基底由不同材料所形成；元件晶粒，位於所述內連線結構之下並接合至所述內連線結構，其中所述元件晶粒經由所述凸塊下金屬及所述內連線結構而電性耦接至所述焊料區；以及包封材料，包封所述元件晶粒。
  2. 如申請專利範圍第1項所述的封裝件，更包括位於所述基底之下並接觸所述基底的介電層，且所述內連線結構包括位於所述介電層之下的導電特徵，其中所述凸塊下金屬穿透所述介電層而接觸所述導電特徵；或其中所述聚合物層包括直接在所述凸塊下金屬之下延伸的水平部分。
  3. 如申請專利範圍第1項所述的封裝件，其中所述焊料區包括與所述基底的一部分處於同一水平高度的部分；或所述凸塊下金屬包括底部部分，所述底部部分具有與所述焊料區的底表面接觸的頂表面，其中所述凸塊下金屬的所述底部部分的所述頂表面低於所述基底的頂表面。
  4. 如申請專利範圍第1項所述的封裝件，其中所述基底是半導體基底或玻璃基底。
  5. 一種封裝件，包括：半導體基底，介電層，位於所述半導體基底之下並接觸所述半導體基底，內連線結構，位於所述介電層之下，其中所述內連線結構包括與所述介電層的底表面接觸的金屬墊；開口，穿透所述半導體基底及所述介電層，聚合物層，包括：第一部分，與所述半導體基底重疊；以及第二部分，延伸至所述開口內以接觸所述金屬墊；以及金屬特徵，自所述聚合物層的所述第一部分的頂表面延伸至所述金屬墊，其中所述金屬特徵被所述聚合物層環繞。
  6. 如申請專利範圍第5項所述的封裝件，其中所述金屬特徵具有錐形輪廓，所述金屬特徵的上部寬度大於所述金屬特徵的相應的下部寬度；或所述聚合物層包括具有實質上水平的頂表面的部分，所述具有實質上水平的頂表面的部分與所述金屬特徵的一部分的底表面接觸；或所述內連線結構包括通孔，所述通孔位於所述金屬墊之下，其中所述通孔具有頂部寬度以及較所述頂部寬度大的底部寬度。
  7. 如申請專利範圍第5項所述的封裝件，更包括位於所述金屬特徵之上並接觸所述金屬特徵的焊料區，其中所述焊料區的一部分低於所述半導體基底的頂表面。
  8. 一種形成封裝件的方法，包括：將元件晶粒接合至晶圓，其中所述晶圓包括半導體基底及內連線結構；對所述半導體基底進行薄化；對所述半導體基底進行蝕刻以在所述半導體基底中形成開口，其中所述內連線結構中的金屬墊藉由所述開口而裸露出；形成聚合物層以覆蓋所述半導體基底，其中所述聚合物層延伸至所述開口內以覆蓋所述金屬墊；對所述聚合物層進行蝕刻，以裸露出所述金屬墊；以及形成上覆於所述聚合物層上的金屬特徵，其中所述金屬特徵延伸至所述開口內以接觸所述金屬墊。
  9. 如申請專利範圍第8項所述的形成封裝件的方法，其中所述形成所述金屬特徵包括形成凸塊下金屬，所述凸塊下金屬包括與所述聚合物層的一部分重疊的第一部分以及位於所述開口中的第二部分。
  10. 如申請專利範圍第8項所述的形成封裝件的方法，更包括形成位於所述金屬特徵之上並接觸所述金屬特徵的焊料區，其中所述焊料區具有延伸至所述半導體基底中的所述開口內的部分，或更包括將封裝件組件接合至所述焊料區。
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