TWI661466B - 使用具有多種材料之一層的基板圖案化方法 - Google Patents

使用具有多種材料之一層的基板圖案化方法 Download PDF

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Publication number
TWI661466B
TWI661466B TW106112326A TW106112326A TWI661466B TW I661466 B TWI661466 B TW I661466B TW 106112326 A TW106112326 A TW 106112326A TW 106112326 A TW106112326 A TW 106112326A TW I661466 B TWI661466 B TW I661466B
Authority
TW
Taiwan
Prior art keywords
layer
substrate
patterning
mandrels
etching
Prior art date
Application number
TW106112326A
Other languages
English (en)
Chinese (zh)
Other versions
TW201742114A (zh
Inventor
Anton J. Devilliers
安東 Ｊ 德維利耶
Original Assignee
Tokyo Electron Limited
日商東京威力科創股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Electron Limited, 日商東京威力科創股份有限公司 filed Critical Tokyo Electron Limited
Publication of TW201742114A publication Critical patent/TW201742114A/zh
Application granted granted Critical
Publication of TWI661466B publication Critical patent/TWI661466B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
TW106112326A 2016-04-14 2017-04-13 使用具有多種材料之一層的基板圖案化方法 TWI661466B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662322603P 2016-04-14 2016-04-14
US62/322,603 2016-04-14

Publications (2)

Publication Number Publication Date
TW201742114A TW201742114A (zh) 2017-12-01
TWI661466B true TWI661466B (zh) 2019-06-01

Family

ID=60039021

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106112326A TWI661466B (zh) 2016-04-14 2017-04-13 使用具有多種材料之一層的基板圖案化方法

Country Status (6)

Country Link
US (2) US10460938B2 (https=)
JP (1) JP7009681B2 (https=)
KR (1) KR102346568B1 (https=)
CN (1) CN109075123B (https=)
TW (1) TWI661466B (https=)
WO (1) WO2017181057A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9824893B1 (en) 2016-06-28 2017-11-21 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US12051589B2 (en) 2016-06-28 2024-07-30 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
TW201830517A (zh) * 2016-11-16 2018-08-16 日商東京威力科創股份有限公司 用於多重圖案化程序之硬遮罩過蝕刻的調節方法
KR102722138B1 (ko) 2017-02-13 2024-10-24 램 리써치 코포레이션 에어 갭들을 생성하는 방법
US10546748B2 (en) 2017-02-17 2020-01-28 Lam Research Corporation Tin oxide films in semiconductor device manufacturing
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10366917B2 (en) * 2018-01-04 2019-07-30 Globalfoundries Inc. Methods of patterning variable width metallization lines
WO2019152362A1 (en) * 2018-01-30 2019-08-08 Lam Research Corporation Tin oxide mandrels in patterning
KR102841279B1 (ko) 2018-03-19 2025-07-31 램 리써치 코포레이션 챔퍼리스 (chamferless) 비아 통합 스킴 (scheme)
US10573520B2 (en) 2018-06-12 2020-02-25 International Business Machines Corporation Multiple patterning scheme integration with planarized cut patterning
US10950442B2 (en) * 2018-07-06 2021-03-16 Tokyo Electron Limited Methods to reshape spacers for multi-patterning processes using thermal decomposition materials
CN113016053B (zh) 2018-11-16 2025-08-19 朗姆研究公司 气泡缺陷减少
EP3660890B1 (en) * 2018-11-27 2021-08-11 IMEC vzw A method for forming an interconnection structure
CN111415860B (zh) * 2019-01-07 2026-01-30 东京毅力科创株式会社 用于对基底进行多重图案化的方法
US11145509B2 (en) * 2019-05-24 2021-10-12 Applied Materials, Inc. Method for forming and patterning a layer and/or substrate
US11551938B2 (en) 2019-06-27 2023-01-10 Lam Research Corporation Alternating etch and passivation process
CN113363203B (zh) * 2020-03-05 2024-07-16 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US11776812B2 (en) * 2020-05-22 2023-10-03 Tokyo Electron Limited Method for pattern reduction using a staircase spacer
WO2022020507A1 (en) * 2020-07-23 2022-01-27 Lam Research Corporation Advanced self aligned multiple patterning using tin oxide
TW202311555A (zh) 2021-04-21 2023-03-16 美商蘭姆研究公司 最小化錫氧化物腔室清潔時間
US20240419074A1 (en) * 2023-06-14 2024-12-19 Tokyo Electron Limited Formation of sub-lithographic mandrel patterns using reversible overcoat

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060240361A1 (en) * 2005-04-21 2006-10-26 Ji-Young Lee Method of forming small pitch pattern using double spacers
US20110076846A1 (en) * 2005-04-19 2011-03-31 Samsung Electronics Co., Ltd. Semiconductor device having fine contacts and method of fabricating the same
TW201545201A (zh) * 2014-02-23 2015-12-01 Tokyo Electron Ltd 用於平坦化之基板圖案化方法

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7829262B2 (en) * 2005-08-31 2010-11-09 Micron Technology, Inc. Method of forming pitch multipled contacts
US8273634B2 (en) * 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
WO2010096363A2 (en) 2009-02-19 2010-08-26 Arkema Inc. Nanofabrication method
US8486611B2 (en) 2010-07-14 2013-07-16 Micron Technology, Inc. Semiconductor constructions and methods of forming patterns
US8575032B2 (en) * 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8629040B2 (en) * 2011-11-16 2014-01-14 Taiwan Semiconductor Manufacturing Company, Ltd. Methods for epitaxially growing active regions between STI regions
US8883621B2 (en) * 2012-12-27 2014-11-11 United Microelectronics Corp. Semiconductor structure and method of fabricating MOS device
WO2015126812A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers
WO2015126829A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for patterning a substrate for planarization
US9601378B2 (en) * 2015-06-15 2017-03-21 International Business Machines Corporation Semiconductor fins for FinFET devices and sidewall image transfer (SIT) processes for manufacturing the same
US10249501B2 (en) * 2016-03-28 2019-04-02 International Business Machines Corporation Single process for liner and metal fill
US10079180B1 (en) * 2017-03-14 2018-09-18 United Microelectronics Corp. Method of forming a semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110076846A1 (en) * 2005-04-19 2011-03-31 Samsung Electronics Co., Ltd. Semiconductor device having fine contacts and method of fabricating the same
US20060240361A1 (en) * 2005-04-21 2006-10-26 Ji-Young Lee Method of forming small pitch pattern using double spacers
TW201545201A (zh) * 2014-02-23 2015-12-01 Tokyo Electron Ltd 用於平坦化之基板圖案化方法

Also Published As

Publication number Publication date
US10460938B2 (en) 2019-10-29
WO2017181057A1 (en) 2017-10-19
JP7009681B2 (ja) 2022-01-26
JP2019514066A (ja) 2019-05-30
TW201742114A (zh) 2017-12-01
CN109075123B (zh) 2023-05-09
US20200066522A1 (en) 2020-02-27
CN109075123A (zh) 2018-12-21
US20170301552A1 (en) 2017-10-19
KR102346568B1 (ko) 2021-12-31
KR20180125614A (ko) 2018-11-23
US11107682B2 (en) 2021-08-31

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