JP7009681B2 - 複数の材料を有する層を用いて基板をパターン化する方法 - Google Patents

複数の材料を有する層を用いて基板をパターン化する方法 Download PDF

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JP7009681B2
JP7009681B2 JP2018553884A JP2018553884A JP7009681B2 JP 7009681 B2 JP7009681 B2 JP 7009681B2 JP 2018553884 A JP2018553884 A JP 2018553884A JP 2018553884 A JP2018553884 A JP 2018553884A JP 7009681 B2 JP7009681 B2 JP 7009681B2
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layer
mandrel
etching
side wall
substrate
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JP2019514066A (ja
JP2019514066A5 (https=
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ジェイ． デヴィリアーズ，アントン
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Tokyo Electron Ltd
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Tokyo Electron Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/089—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts using processes for implementing desired shapes or dispositions of the openings, e.g. double patterning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/20—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials
    • H10P76/204—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising organic materials of organic photoresist masks
    • H10P76/2041—Photolithographic processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/075—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers of multilayered thin functional dielectric layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Drying Of Semiconductors (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
JP2018553884A 2016-04-14 2017-04-14 複数の材料を有する層を用いて基板をパターン化する方法 Active JP7009681B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US201662322603P 2016-04-14 2016-04-14
US62/322,603 2016-04-14
PCT/US2017/027693 WO2017181057A1 (en) 2016-04-14 2017-04-14 Method for patterning a substrate using a layer with multiple materials

Publications (3)

Publication Number Publication Date
JP2019514066A JP2019514066A (ja) 2019-05-30
JP2019514066A5 JP2019514066A5 (https=) 2020-05-28
JP7009681B2 true JP7009681B2 (ja) 2022-01-26

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JP2018553884A Active JP7009681B2 (ja) 2016-04-14 2017-04-14 複数の材料を有する層を用いて基板をパターン化する方法

Country Status (6)

Country Link
US (2) US10460938B2 (https=)
JP (1) JP7009681B2 (https=)
KR (1) KR102346568B1 (https=)
CN (1) CN109075123B (https=)
TW (1) TWI661466B (https=)
WO (1) WO2017181057A1 (https=)

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US9824893B1 (en) 2016-06-28 2017-11-21 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
US12051589B2 (en) 2016-06-28 2024-07-30 Lam Research Corporation Tin oxide thin film spacers in semiconductor device manufacturing
TW201830517A (zh) * 2016-11-16 2018-08-16 日商東京威力科創股份有限公司 用於多重圖案化程序之硬遮罩過蝕刻的調節方法
KR102722138B1 (ko) 2017-02-13 2024-10-24 램 리써치 코포레이션 에어 갭들을 생성하는 방법
US10546748B2 (en) 2017-02-17 2020-01-28 Lam Research Corporation Tin oxide films in semiconductor device manufacturing
US10727045B2 (en) * 2017-09-29 2020-07-28 Taiwan Semiconductor Manufacturing Company, Ltd. Method for manufacturing a semiconductor device
US10366917B2 (en) * 2018-01-04 2019-07-30 Globalfoundries Inc. Methods of patterning variable width metallization lines
WO2019152362A1 (en) * 2018-01-30 2019-08-08 Lam Research Corporation Tin oxide mandrels in patterning
KR102841279B1 (ko) 2018-03-19 2025-07-31 램 리써치 코포레이션 챔퍼리스 (chamferless) 비아 통합 스킴 (scheme)
US10573520B2 (en) 2018-06-12 2020-02-25 International Business Machines Corporation Multiple patterning scheme integration with planarized cut patterning
US10950442B2 (en) * 2018-07-06 2021-03-16 Tokyo Electron Limited Methods to reshape spacers for multi-patterning processes using thermal decomposition materials
CN113016053B (zh) 2018-11-16 2025-08-19 朗姆研究公司 气泡缺陷减少
EP3660890B1 (en) * 2018-11-27 2021-08-11 IMEC vzw A method for forming an interconnection structure
CN111415860B (zh) * 2019-01-07 2026-01-30 东京毅力科创株式会社 用于对基底进行多重图案化的方法
US11145509B2 (en) * 2019-05-24 2021-10-12 Applied Materials, Inc. Method for forming and patterning a layer and/or substrate
US11551938B2 (en) 2019-06-27 2023-01-10 Lam Research Corporation Alternating etch and passivation process
CN113363203B (zh) * 2020-03-05 2024-07-16 中芯国际集成电路制造(上海)有限公司 半导体器件的形成方法
US11776812B2 (en) * 2020-05-22 2023-10-03 Tokyo Electron Limited Method for pattern reduction using a staircase spacer
WO2022020507A1 (en) * 2020-07-23 2022-01-27 Lam Research Corporation Advanced self aligned multiple patterning using tin oxide
TW202311555A (zh) 2021-04-21 2023-03-16 美商蘭姆研究公司 最小化錫氧化物腔室清潔時間
US20240419074A1 (en) * 2023-06-14 2024-12-19 Tokyo Electron Limited Formation of sub-lithographic mandrel patterns using reversible overcoat

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JP2009506576A (ja) 2005-08-31 2009-02-12 マイクロン テクノロジー， インク． ピッチ増倍コンタクトを形成する方法
US20150243518A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers

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KR100674970B1 (ko) * 2005-04-21 2007-01-26 삼성전자주식회사 이중 스페이서들을 이용한 미세 피치의 패턴 형성 방법
US8273634B2 (en) * 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
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JP2009506576A (ja) 2005-08-31 2009-02-12 マイクロン テクノロジー， インク． ピッチ増倍コンタクトを形成する方法
US20150243518A1 (en) 2014-02-23 2015-08-27 Tokyo Electron Limited Method for multiplying pattern density by crossing multiple patterned layers

Also Published As

Publication number Publication date
US10460938B2 (en) 2019-10-29
WO2017181057A1 (en) 2017-10-19
JP2019514066A (ja) 2019-05-30
TW201742114A (zh) 2017-12-01
CN109075123B (zh) 2023-05-09
US20200066522A1 (en) 2020-02-27
CN109075123A (zh) 2018-12-21
TWI661466B (zh) 2019-06-01
US20170301552A1 (en) 2017-10-19
KR102346568B1 (ko) 2021-12-31
KR20180125614A (ko) 2018-11-23
US11107682B2 (en) 2021-08-31

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