TWI651853B - 半導體元件結構及其製造方法及電晶體 - Google Patents

半導體元件結構及其製造方法及電晶體 Download PDF

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TWI651853B
TWI651853B TW103146471A TW103146471A TWI651853B TW I651853 B TWI651853 B TW I651853B TW 103146471 A TW103146471 A TW 103146471A TW 103146471 A TW103146471 A TW 103146471A TW I651853 B TWI651853 B TW I651853B
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卡羅斯Ｈ 戴爾茲
林群雄
張惠政
章勳明
王建勛
黃懋霖
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台灣積體電路製造股份有限公司
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Abstract

本發明提供一種半導體元件結構包括：一內核結構，形成於一支撐物上，以及一外殼材料，形成於內核結構上並圍繞至少部分的內核結構。外殼材料和內核結構被配置以在外殼材料中形成一量子井通道。

Description

半導體元件結構及其製造方法及電晶體
本發明係有關於半導體元件，且特別是有關於一種半導體元件的製造方法。
本揭露所述的技術一般係有關於半導體元件，且特別是有關於一種半導體元件的製造方法。
傳統平面(planar)元件通常具有微縮化和選擇合適的材料的限制。隨著半導體元件的尺寸持續微縮(例如：微縮至次50nm範圍)，各種問題像是短-通道效應和不良的次-閾值(sub-threshold)特色，經常成為傳統平面元件中嚴重的問題。具有改良性能的新穎元件圖形，像是三維尺寸元件結構(例如：鰭狀場效電晶體(FinFETs))和N-MOS和P-MOS不同高遷移性(high-mobility)通道的異質整合，已經被探討以在元件和電路中推向的更高封裝密度。
根據一實施例，本發明提供一種半導體元件結構，包括：一內核結構，形成於一支撐物上，以及一外殼材料，形成於內核結構上並圍繞至少部分的內核結構。外殼材料和內核結構被配置以在外殼材料中形成一量子井通道。
根據另一實施例，本發明提供一種半導體元件結構的製造方法，包括：形成一內核結構於一支撐物上；以及形 成一外殼材料於內核結構上以圍繞至少部分的內核結構，外殼材料包括一量子井通道。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
100、200‧‧‧奈米線電晶體結構
102、202、302、322、806、A‧‧‧內核結構
104、204、304、324、516、614、808、908、B‧‧‧外殼材料
106、508‧‧‧間隔
108‧‧‧源極/汲極(source/drain)材料
110‧‧‧材料
112‧‧‧淺溝槽隔離結構
114、206、504、802、904‧‧‧支撐物結構
C‧‧‧割線
300‧‧‧n-型電晶體
306、326‧‧‧包覆材料
320‧‧‧p-型電晶體
402、602‧‧‧矽層
404、604、610‧‧‧氧化矽層
406、606‧‧‧矽基板
500、600‧‧‧晶圓
502、804‧‧‧第一材料
506‧‧‧第二材料
510‧‧‧源極/汲極區域
514‧‧‧分離結構
608‧‧‧矽化鍺層
612‧‧‧含鍺材料
902‧‧‧第一材料；內核結構
906‧‧‧罩幕層
1002、1004‧‧‧步驟
根據以下的詳細說明並配合所附圖式做完整揭露。應注意的是，根據本產業的一般作業，圖式並未必按照比例繪製。事實上，可能任意的放大或縮小元件的尺寸，以做清楚的說明。
第1A圖~第1C圖係根據一些實施例描述範例圖式以顯示一水平奈米線電晶體結構。
第2A圖~第2B圖係根據一些實施例描述範例圖式以顯示一垂直奈米線電晶體結構。
第3A圖~第3B圖係根據一些實施例描述範例圖式以分別顯示n-型電晶體結構的能帶圖(band diagram)和p-型電晶體結構的能帶圖。
第4A圖~第4D圖係根據一些實施例描述範例圖式以顯示在絕緣體上覆矽(silicon-on-insulator；SOI)晶圓上製造水平內核結構的製程。
第5A圖~第5F圖係根據一些實施例描述範例圖式以顯示製造包括一水平內核-外殼結構的電晶體結構的製程。
第6A圖~第7F圖係根據一些實施例描述範例圖式以顯示在絕緣體上覆矽(SOI)晶圓上製造一水平內核-外殼結構的另一製 程。
第8A圖~第8C圖係根據一些實施例描述範例圖式以顯示製造一垂直內核-外殼結構的製程。
第9A圖~第9C圖係根據一些實施例描述範例圖式以顯示製造一垂直內核-外殼結構的另一製程。
第10圖係根據一些實施例描述製造包括一內核-外殼結構的元件結構的一範例流程圖。
以下的揭露內容提供許多不同的實施例或範例以實施本發明的不同特徵。以下的揭露各個構件及排列方式的特定範例，以簡化本揭露。當然，這些特定的範例僅作為示例而並非用以限定。例如，以下當本揭露敘述一第一特徵形成於一第二特徵之上或上方，可能包含上述第一特徵與上述第二特徵直接接觸的實施例，亦可能包含了有附加特徵形成於上述第一特徵與上述第二特徵之間，而使上述第一特徵與第二特徵可能未直接接觸的實施例。此外，本揭露中各種不同範例可能重複使用參考符號及/或標記。這些重複係為了簡化與清晰的目的，並非用以限定所討論的各種不同實施例及/或結構之間有特定的關係。
此外，空間相關用詞，例如“上方”、“在...下方”及類似的用詞可在此使用以簡化描述，以描述圖示中一個元件或特徵與另一個(些)元件或特徵之間的關係。除了在圖式中繪示的方位外，這些空間相關用詞意欲包含使用中或操作中的元件之不同方位。裝置可能被轉向不同方位(旋轉90度或其他方 位)，則在此使用的空間相關詞也可依此相同解釋。
奈米科技的發展和生產奈米線的新興能力為下一個世代半導體元件的設計展開新的可能性，像是具有內核-外殼結構的水平奈米線元件和垂直奈米線元件。
第1A圖~第1C圖根據一些實施例描述範例圖式以顯示一水平奈米線電晶體結構。如第1A圖所示，水平奈米線電晶體結構100包括一內核結構102(例如：A)和形成於內核結構102上的一外殼材料104(例如：B)。圍繞至少部份的內核結構102的外殼材料104作為奈米線電晶體結構100的通道區域(例如：量子井通道)，而內核結構102作為一阻障區域。舉例來說，外殼材料104被配置以引導(conduct)一電流流經源極區域和汲極區域108之間，並且包括一反轉層(inversion layer)或一堆疊層(accumulation layer)。此外，奈米線電晶體結構100包括間隔106(例如：氮化矽、氧化矽)和源極/汲極(source/drain)材料108(例如：矽化鍺或矽化碳)。內核結構102延伸穿過間隔106且被一材料110(例如：氧化矽、鍺、矽化鍺)支撐。
第1B圖顯示奈米線電晶體結構100的剖面圖，且第1C圖顯示奈米線電晶體結構100沿著如第1B圖所示割線C的另一個剖面圖。如第1C圖所示，奈米線電晶體結構100形成於一支撐物結構114(例如：一矽基板、一氧化物上覆矽(silicon-on-oxide)晶圓)上。
第2A圖~第2B圖根據一些實施例描述範例圖式以顯示垂直奈米線電晶體結構。如第2A圖和第2B圖所示，垂直奈米線電晶體結構200包括一內核結構202(例如：A)和形成於 內核結構202上的一外殼材料204(例如：B)。圍繞部份的內核結構202的外殼材料204作為奈米線電晶體結構200的通道區域(例如：量子井通道)，而內核結構202作為一阻障區域。舉例來說，外殼材料204被配置以引導(conduct)一電流流經源極區域(未顯示)和汲極區域(未顯示)之間，並且包括一反轉層(inversion layer)或一堆疊層(accumulation layer)。第2B圖顯示奈米線電晶體結構200的剖面圖。內核結構202和外殼材料204形成於一支撐物結構206上。
在一些實施例中，外殼材料104(或外殼材料204)與第一晶格常數和第一能隙(bandgap)相關，而內核結構102(或內核結構202)與第二晶格常數和第二能隙相關。第一能隙小於第二能隙，且第一晶格常數大於第二晶格常數。舉例來說，第一晶格常數大於第二晶格常數約1%至約8%。晶格失配應變(lattice mismatch strain)可透過外殼材料104(或外殼材料204)和內核結構102(或內核結構202)被分散而不產生許多差排(dislocation)。
在特定的實施例中，外殼材料104(或外殼材料204)具有一厚度，其範圍為約2nm至約15nm，且內核結構102(或內核結構202)具有一直徑，其範圍為約3nm至約15nm。舉例來說，為了量子通道侷限(例如：避免穿隧(tunneling)及/或散射)，內核結構102(或內核結構202)具有一最低的厚度限制，且具有一最高的厚度限制以降低由內核結構102(或內核結構202)和外殼材料104(或外殼材料204)之間的晶格失配(lattice mismatch)所產生的差排(dislocations)。舉例來說，為了引導 (conducting)電流(例如：包括一反轉層或一堆疊層)，外殼材料104(或外殼材料204)具有一最低的厚度限制，且具有一最高的厚度限制以降低因內核結構102(或內核結構202)和外殼材料104(或外殼材料204)之間的晶格失配(lattice mismatch)所導致的差排(dislocations)。外殼材料104(或外殼材料204)可具有一厚度，其不大於由奈米線電晶體結構100(或奈米線電晶體結構200)所製造的電晶體的一閘極長度(例如：閘極長度小於或等於50nm)的約1/3。舉例來說，內核結構102(或內核結構202)的半徑被控制在一特定範圍中以提供外殼材料104(或外殼材料204)的厚度更多彈性。
在一些實施例中，外殼材料104(或外殼材料204)包括矽、矽化鍺、鍺、III-V族材料(例如：砷化銦鎵)、或其他合適的材料。內核結構102(或內核結構202)包括矽、矽化鍺、鍺、或其他合適的材料。內核結構102(或內核結構202)和外殼材料104(或外殼材料204)可具有不同的導電類型(例如：不同類型的摻雜物)。舉例來說，內核結構102(或內核結構202)未被摻雜或被p-型摻雜物摻雜至1×1020/cm3，且外殼材料104(或外殼材料204)未被摻雜或被n-型摻雜物摻雜至1×1020/cm3。在另一個實施例中，內核結構102(或內核結構202)未被摻雜或被n-型摻雜物摻雜至1×1020/cm3，且外殼材料104(或外殼材料204)未被摻雜或被p-型摻雜物摻雜至1×1020/cm3。
第3A圖~第3B圖根據一些實施例描述範例圖式以分別顯示n-型電晶體結構的能帶圖(band diagram)和p-型電晶體結構的能帶圖。如第3A圖所示，n-型電晶體300包括一內核 結構302(例如：A)和形成於內核結構302上的一外殼材料304(例如：B)。外殼材料304圍繞至少部分的內核結構302，且作為n-型電晶體300的通道區域(例如：量子井通道)。包覆材料306(例如：介電材料)形成於外殼材料304上且圍繞至少部分的外殼材料304。舉例來說，包覆材料306包括具有大能隙(bandgap)的一高介電常數(high-k)材料，並作為電晶體300的一閘極介電質。如第3A圖所示，一阻障形成於內核結構302(例如：A)和外殼材料304(例如：B)之間的界面上。舉例來說，阻障高度(例如：△E)的範圍為約0.3eV至約0.5eV。
如第3B圖所示，p-型電晶體320包括一內核結構322(例如：A)和形成於內核結構322上的一外殼材料324(例如：B)。外殼材料324圍繞至少部分的內核結構322，並作為p-型電晶體320的通道區域(例如：量子井通道)。包覆材料326(例如：介電材料)形成於外殼材料324上且圍繞至少部分的外殼材料324。如第3B圖所示，一阻障形成於內核結構322(例如：A)和外殼材料324(例如：B)之間的界面上。舉例來說，阻障高度(例如：△E)的範圍為約0.3eV至約0.5eV。作為一個範例，包覆材料326具有大能隙的一高介電常數(high-k)材料，並作為電晶體320的一閘極介電質。在一些實施例中，包覆材料306和包覆材料326包括HfO2、ZrO2、La2O3、Al2O3、TiO2、SrTiO3、LaAlO3、Y2O3、HfOxNy、ZrOxNy、La2OxNy、Al2OxNy、TiOxNy、或其他合適的材料。
第4A圖~第4D圖根據一些實施例描述範例圖式以顯示在絕緣體上覆矽(silicon-on-insulator；SOI)晶圓上製造水 平內核結構的製程。絕緣體上覆矽(SOI)晶圓包括一矽層402位於一埋藏氧化矽層404上，此埋藏氧化矽層404形成於一矽基板406上。矽層402被圖案化(例如：透過微影和蝕刻)。舉例來說，反應離子蝕刻被實施以移除部分的矽層402。第4B圖顯示包括圖案化矽層402的絕緣體上覆矽(SOI)晶圓的剖面圖。蝕刻製程(例如：選擇性蝕刻或均向蝕刻(isotropic etching))被實施在絕緣體上覆矽(SOI)晶圓上。於矽層402下方的部份氧化矽層404被移除，其導致一個或多個奈米線結構懸掛在部分的凹陷氧化矽層404之上，如第4C圖所示。第4D圖顯示水平奈米線結構之一的剖面圖。舉例來說，蝕刻製程係在室溫下利用稀釋的氫氟酸實施。奈米線結構可進一步被退火(例如：在一溫度範圍約600℃至約1000℃)以形成一個或多個水平內核結構(例如：內核結構102)。此外，奈米線結構可被氧化並蝕刻以達到水平內核結構(例如：內核結構102)所欲求的直徑。舉例來說，所形成的內核結構大致上平行於矽基板406，且為橢圓形或圓柱狀。
第5A圖~第5F圖根據一些實施例描述範例圖式以顯示製造包括水平內核-外殼結構的電晶體結構的製程。如第5A圖所示，晶圓500包括形成於支撐物結構504(例如：矽基板)上的第一材料502(例如：A)和形成於(例如：透過磊晶生長)第一材料502上的第二材料506(例如：B)。舉例來說，第一材料502和第二材料506包括具有不同鍺濃度的矽化鍺。在另一實施例中，第二材料506包括矽。間隔508(例如：氮化矽)，及源極/汲極區域510形成於第二材料506上。在一些實施例中，介電材料(例如：氧化矽)可形成於源極/汲極區域510上。
第5B圖顯示晶圓500的剖面圖。一個或多個分離結構514(例如：淺溝槽隔離結構)形成於(例如：鄰近第一材料502)支撐物結構504上。蝕刻製程(例如：選擇性蝕刻或均向蝕刻)被實施於晶圓500上。於第二材料506下方的部分第一材料502被移除，其導致一個或多個奈米線結構懸掛在部分的凹陷第二材料506之上，如第5C圖所示。第5D圖顯示水平奈米線結構之一的剖面圖。奈米線結構可進一步被退火(例如：在一溫度範圍約600℃至約1000℃)以形成一個或多個水平內核結構(例如：內核結構102)。奈米線結構可被氧化並蝕刻以達到水平內核結構(例如：內核結構102)所欲求的直徑。此外，外殼材料516(例如：外殼材料104)形成於(例如：透過磊晶生長)由第二材料506所產生的水平內核結構上，如第5E圖所示。第5F圖顯示包括如第5E圖所示的內核-外殼結構的電晶體結構的剖面圖。
第6A圖~第7F圖根據一些實施例描述範例圖式以顯示在絕緣體上覆矽(SOI)晶圓上製造水平內核-外殼結構的另一製程。如第6A圖所示，絕緣體上覆矽(SOI)晶圓600包括一矽層602位於一埋藏氧化矽層604上，此埋藏氧化矽層604形成於一矽基板606上。矽化鍺層608形成於矽層602上。
縮合製程(condensation process)被實施於絕緣體上覆矽(SOI)晶圓600上，例如：在含氧環境中(例如：在加熱爐(oven)中)介於850℃和1100℃之間的溫度。在縮合製程期間，矽化鍺層608中的鍺原子向內遷移(migrate inwardly)以形成一含鍺材料612。舉例來說，含鍺材料612包括一高比例的鍺(例如：接近100%)。由於縮合製程，氧化矽層610形成於含鍺材料 612上，如第6B圖所示。接著，氧化矽層610被移除(例如：透過蝕刻)，如第6C圖所示。
含鍺材料612被圖案化(例如：透過微影和蝕刻)，如第7A圖所示。第7B圖顯示包括含鍺材料612的絕緣體上覆矽(SOI)晶圓600的剖面圖。蝕刻製程(例如：選擇性蝕刻或均向蝕刻)被實施於絕緣體上覆矽(SOI)晶圓600上。於含鍺材料612下方的部分氧化矽層604被移除，其導致一個或多個奈米線結構懸掛在部分的凹陷氧化矽層604之上，如第7C圖所示。第7D圖顯示水平奈米線結構之一的剖面圖。奈米線結構可進一步被退火(例如：在一溫度範圍約600℃至約1000℃)以形成一個或多個水平內核結構(例如：內核結構102)。奈米線結構可被氧化並蝕刻以達到水平內核結構(例如：內核結構102)所欲求的直徑。此外，外殼材料614(例如：外殼材料104)形成於(例如：透過磊晶生長)由含鍺材料612所產生的水平內核結構上，如第7E圖所示。第7F圖顯示包括如第7E圖所示的內核-外殼結構的剖面圖。
第8A圖~第8C圖根據一些實施例描述範例圖式以顯示製造垂直內核-外殼結構的製程。垂直內核-外殼結構可生長在一支撐物結構802上(例如：矽基板)。如第8A圖所示，第一材料804(例如：氧化矽)被圖案化在支撐物結構802上。一個或多個垂直奈米線結構選擇性地或定向地(directionally)被形成(例如：透過磊晶生長)於圖案化的第一材料804上。奈米線結構可進一步被退火(例如：在一溫度範圍約600℃至約1000℃)以形成一個或多個垂直內核結構806(例如：內核結構202)，如 第8B圖所示。奈米線結構可被氧化並蝕刻以達到垂直內核結構806所欲求的直徑。此外，外殼材料808(例如：外殼材料204)形成於(例如：透過磊晶生長)垂直內核結構806上，如第8C圖所示。作為一個範例，支撐物結構802具有一結晶方向(111)。舉例來說，垂直內核結構806大致上垂直於支撐物結構802。
第9A圖~第9C圖根據一些實施例描述範例圖式以顯示製造垂直內核-外殼結構的另一製程。如第9A圖所示，第一材料902(例如：矽化鍺)形成於支撐物結構904上。罩幕層906形成於第一材料902上，並接著透過像是微影和蝕刻而被圖案化。舉例來說，光阻層被形成在罩幕層906上並被曝露於一欲求圖案的輻射。接著，利用光阻顯影劑使光阻層被顯影。光阻層中的圖案透過罩幕層906被轉移至下方的(underlying)第一材料902中。可利用單一蝕刻(例如：乾蝕刻或濕蝕刻)或多重蝕刻，透過罩幕層906將圖案轉移至下方的(underlying)第一材料902中，且接著罩幕層906被移除以形成一個或多個垂直奈米線結構。奈米線結構可進一步被退火(例如：在一溫度範圍約600℃至約1000℃)以形成一個或多個垂直內核結構902(例如：內核結構202)，如第9B圖所示。奈米線結構可被氧化並蝕刻以達到垂直內核結構902所欲求的直徑。舉例來說，垂直內核結構902大致上垂直於支撐物結構904且為橢圓形或圓柱狀。此外，外殼材料908(例如：外殼材料204)形成於(例如：透過磊晶生長)垂直內核結構902上，如第9C圖所示。
第10圖根據一些實施例描述製造包括內核-外殼結構的元件結構的範例流程圖。於步驟1002，內核結構形成於支 撐物(例如：基板)上。於步驟1004，外殼材料形成於內核結構上以圍繞至少部分的內核結構。外殼材料包括一量子井通道。舉例來說，內核結構和外殼材料透過化學氣相沉積(chemical vapor deposition；CVD)、電漿增強式化學氣相沉積(plasma enhanced chemical vapor deposition；PECVD)、物理氣相沉積(physical vapor deposition；PVD)、濺鍍、原子層沉積(sputtering,atomic layer deposition；ALD)、或其他合適的製程被形成。
根據一實施例，一種元件結構包括：一內核結構，形成於一支撐物上，以及一外殼材料，形成於內核結構上並圍繞至少部分的內核結構。外殼材料和內核結構被配置以在外殼材料中形成一量子井通道。
根據另一實施例，提供一種用來形成一內核-外殼裝置結構的方法。一內核結構形成於一支撐物上。一外殼材料形成於內核結構上以圍繞至少部分的內核結構，外殼材料包括一量子井通道。
根據又另一實施例，一種電晶體包括：一源極區域、一汲極區域、以及一奈米線結構，其包括一內核結構，以及圍繞至少部分的內核結構的一外殼材料。外殼材料和內核結構被配置以於外殼材料中形成一量子井通道以在源極區域和汲極區域引導(conduct)一電流。
前述內文概述了許多實施例的特徵，使本技術領域中具有通常知識者可以從各個方面更佳地了解本揭露。本技術領域中具有通常知識者應可理解，且可輕易地以本揭露為基礎來設計或修飾其他製程及結構，並以此達到相同的目的及/ 或達到與在此介紹的實施例等相同之優點。本技術領域中具有通常知識者也應了解這些相等的結構並未背離本揭露的發明精神與範圍。在不背離本揭露的發明精神與範圍之前提下，可對本揭露進行各種改變、置換或修改。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。

Claims (9)

  1. 一種半導體元件結構，包括：一支撐物，包含一第一頂表面和一第二頂表面，該第一頂表面和該第二頂表面定義在其間具有一頂部開口的一凹部，其中該第一頂表面和該第二頂表面水平地延伸遠離該頂部開口的水平的兩側；一半導體內核結構，物理接觸該第一頂表面和該第二頂表面並水平地延伸通過該頂部開口；一半導體外殼材料，在該頂部開口上圍繞該半導體內核結構，其中該半導體外殼材料和該半導體內核結構在該半導體外殼材料中形成一量子井通道；以及一第一間隔物和一第二間隔物，位於該半導體外殼材料的兩側並圍繞該半導體內核結構。
  2. 如申請專利範圍第1項所述之半導體元件結構，其中：該半導體內核結構和該半導體外殼材料包括在一奈米線結構中；以及該奈米線結構大致上平行於該支撐物。
  3. 如申請專利範圍第1項所述之半導體元件結構，其中：該半導體外殼材料與一第一能隙(bandgap)相關；該半導體內核結構與一第二能隙相關；以及該第一能隙小於該第二能隙；其中形成於該半導體外殼材料和該半導體內核結構之間的一界面上的一阻障與約0.3eV至約0.5eV的一阻障高度相關。
  4. 如申請專利範圍第1項所述之半導體元件結構，更包括：一包覆材料，形成於該半導體外殼材料上並圍繞至少部份的該半導體外殼材料；其中：該半導體外殼材料與一第一能隙相關；該包覆材料與一第二能隙相關；以及該第一能隙小於該第二能隙。
  5. 如申請專利範圍第1項所述之半導體元件結構，其中：該半導體外殼材料與一第一晶格常數相關；該半導體內核結構與一第二晶格常數相關；以及該第一晶格常數大於該第二晶格常數，其中該第一晶格常數大於該第二晶格常數約1%至約8%。
  6. 如申請專利範圍第1項所述之半導體元件結構，其中該半導體外殼材料的厚度係至少基於與該半導體內核結構的厚度相關的訊息來決定。
  7. 一種半導體元件結構的製造方法，包括：形成一支撐物，該支撐物包含一第一頂表面和一第二頂表面，該第一頂表面和該第二頂表面定義在其間具有一頂部開口的一凹部，其中該第一頂表面和該第二頂表面水平地延伸遠離該頂部開口的水平的兩側；在該第一頂表面和該第二頂表面上方直接形成一半導體內核結構，該半導體內核結構水平地延伸通過該頂部開口；形成一第一間隔物和一第二間隔物圍繞該半導體內核結構；以及在該頂部開口上形成一半導體外殼材料以圍繞該半導體內核結構，該半導體外殼材料包括一量子井通道，其中該第一間隔物和該第二間隔物在該半導體外殼材料的兩側。
  8. 如申請專利範圍第7項所述之半導體元件結構的製造方法，更包括：形成一包覆材料於該半導體外殼材料上以圍繞至少部分的該半導體外殼材料以於該半導體外殼材料中形成該量子井通道。
  9. 一種電晶體，包括：一支撐物，具有一頂部開口；一源極區域和一汲極區域，位於該支撐物上該頂部開口之兩側；一奈米線結構，包括物理接觸該支撐部之一第一頂表面和一第二頂表面的一半導體內核結構，以及在該頂部開口上圍繞該半導體內核結構的一半導體外殼材料，其中該第一頂表面和該第二頂表面分別在該源極區域和該汲極區域下方；其中該半導體外殼材料和該半導體內核結構於該半導體外殼材料中形成一量子井通道以在該源極區域和汲極區域之間引導(conduct)一電流；以及一第一間隔物和一第二間隔物，位於該半導體外殼材料的兩側並圍繞該半導體內核結構。
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