TWI640082B - 使用互補式金氧半導體製造流程以製造電荷捕獲閘極堆疊的方法 - Google Patents

使用互補式金氧半導體製造流程以製造電荷捕獲閘極堆疊的方法 Download PDF

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TWI640082B
TWI640082B TW104100137A TW104100137A TWI640082B TW I640082 B TWI640082 B TW I640082B TW 104100137 A TW104100137 A TW 104100137A TW 104100137 A TW104100137 A TW 104100137A TW I640082 B TWI640082 B TW I640082B
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dielectric
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克里希納斯瓦米 庫馬爾
謝慧美
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美商賽普拉斯半導體公司
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Abstract

描述了一種製造記憶體元件的方法。一般而言，該方法包括：在基板表面形成一介電堆疊，其含有穿隧介電質與覆蓋該穿隧介電質的電荷捕獲層；在介電堆疊上方沈積含有氧化物的一第一覆蓋層；在第一覆蓋層上方形成含有氮化物的一第二覆蓋層；圖樣化該第一和第二覆蓋層以及該介電堆疊以形成一記憶體元件的一閘極堆疊；移除該第二覆蓋層；以及執行一氧化製程以在該電荷捕獲層之上形成一阻擋氧化層，其中該氧化製程消耗該第一覆蓋層。也描述了其他具體實例。

Description

使用互補式金氧半導體製造流程以製造電荷捕獲閘極堆疊的方法 【相關申請案之交互參照】
本申請案主張基於35 U.S.C.119(e)享有在2014年2月6日申請之第61/936,546號美國臨時申請案的優先權，其全部內容係併入本文作為參考。
本揭露一般係關於半導體元件的領域，且更特別是關於將電荷捕獲閘級堆疊整合至互補式金氧半導體流程的方法。
雖然基於金屬氧化物半導體場效電晶體(MOSFETs)之含有邏輯元件和界面電路的積體電路係典型地使用標準的互補式金氧半導體(CMOS)製造流程製造，其涉及導電材料、半導體材料和介電材料的形成與圖樣化。用於這種互補式金氧半導體製造流程的這些材料之組成，還有加工試劑的組成和濃度，以及溫度在每個操作中係被嚴格控制以確保產生的MOSFETs能夠正常運行。對於許多的應用，希望的是在積體電路中包括含有電荷捕獲閘級堆疊之以FETs為基礎的非揮發性記憶體元件。電荷捕獲閘級堆疊的形成涉及在兩介電或氧化層之間夾著氮化物或氮氧化物的電荷捕獲層的形成，其典型地稱為氧化物-氮化物-氧化物(Oxide-Nitride-Oxide， ONO)堆疊。製造ONO堆疊的傳統技術是使用和標準互補式金氧半導體製造流程明顯不同的材料和製程，且其會決定性的影響MOSFETs的製造或會被MOSFETs的製造所影響。特別是，藉由改變頂部氧化層或阻擋氧化層的厚度或組成，MOSFET之閘極氧化層或介電的形成可明顯地降低先前形成之ONO堆疊的效能。
描述了製造一種包括記憶體元件和邏輯元件之電路的方法。在一具體實例中，該方法包括在一基板表面上形成一介電堆疊，其包括一穿隧介電質和覆蓋該穿隧介電質的一電荷捕獲層。含有氧化物的一第一覆蓋層沈積在介電堆疊之上，且含有氮化物的一第二覆蓋層形成在該第一覆蓋層之上。該第一和第二覆蓋層與該介電堆疊係被圖樣化以形成一記憶體元件的一閘極堆疊。移除該第二覆蓋層且進行一氧化製程以在該電荷捕獲層上形成一阻擋氧化層，其中該氧化製程會消耗該第一覆蓋層。
202‧‧‧通道
204‧‧‧第一區
206‧‧‧基板
208‧‧‧通道
210‧‧‧第二區
211‧‧‧襯墊氧化層
212‧‧‧隔離結構
214‧‧‧介電堆疊
215‧‧‧圖樣化遮罩層
216‧‧‧穿隧介電質
218‧‧‧電荷捕獲層
218a‧‧‧第一電荷捕獲層
218b‧‧‧第二電荷捕獲層
220‧‧‧中間氧化層
222‧‧‧覆蓋層
222a‧‧‧第一覆蓋層
222b‧‧‧第二覆蓋層
224‧‧‧犧牲氧化層
226‧‧‧圖樣化遮罩層
228‧‧‧閘極堆疊
230‧‧‧阻擋氧化層
232‧‧‧第一閘極氧化層
234‧‧‧MOS元件
236‧‧‧HV MOS元件
238‧‧‧圖樣化遮罩層
240‧‧‧開口
242‧‧‧第二閘極氧化層
244‧‧‧閘極層
246‧‧‧閘極
248‧‧‧記憶體元件
250‧‧‧閘極
252‧‧‧閘極
254‧‧‧側壁隔離層
256‧‧‧延伸區域
258‧‧‧源極和汲極區域
306‧‧‧基板
316‧‧‧穿隧介電質
318‧‧‧電荷捕獲層
318a‧‧‧第一電荷捕獲層
318b‧‧‧第二電荷捕獲層
322‧‧‧覆蓋層
322a‧‧‧第一覆蓋層
322b‧‧‧第二覆蓋層
324‧‧‧犧牲氧化層
328‧‧‧閘極堆疊
330‧‧‧阻擋氧化層
402‧‧‧通道
406‧‧‧基板
416‧‧‧穿隧介電質
418‧‧‧電荷捕獲層
418a‧‧‧第一電荷捕獲層
418b‧‧‧第二電荷捕獲層
423‧‧‧第一犧牲氧化層
424‧‧‧第二犧牲氧化層
428‧‧‧閘極堆疊
430‧‧‧阻擋氧化層
600‧‧‧積體電路
606‧‧‧基板
602‧‧‧記憶體元件
604‧‧‧第一區
608‧‧‧MOS元件
610‧‧‧第二區
614‧‧‧通道
616‧‧‧表面
618‧‧‧源極
620‧‧‧汲極
622‧‧‧閘極堆疊
624‧‧‧穿隧介電質
626‧‧‧電荷捕獲層
628‧‧‧阻擋氧化層
630‧‧‧閘極層
632‧‧‧絕緣或介電層
634‧‧‧通道
636‧‧‧源極
638‧‧‧汲極
640‧‧‧閘極
642‧‧‧閘極氧化層
644‧‧‧多晶矽閘極層
本發明的具體實例將會從下面的詳細說明和從伴隨的圖式與下面提供之隨附的申請專利範圍被更完整的了解，其中：圖1是闡明製造含有金屬氧化物半導體場效電晶體(MOSFETs)與帶有電荷捕獲閘級堆疊之非揮發性記憶體(NVM)元件的積體電路(IC)的方法流程圖；圖2A-2Q是闡明在根據圖1方法製造IC時的IC部分截面的方塊圖，其中第一覆蓋層含有沈積的氧化物；圖3A-3C是闡明在根據圖1方法製造IC時的IC部分截面的 方塊圖，其中第一覆蓋層含有沈積的氮化物；圖4A-4F是闡明製造含有MOSFET與帶有電荷捕獲閘級堆疊之NVM元件的IC的另一具體實例之方法流程圖，其中第一覆蓋層含有生長出的氧化物；圖5是闡明製造含有MOSFET與帶有電荷捕獲閘級堆疊之NVM元件的IC的另一具體實例之方法流程圖，其係使用具有分離沈積腔室的組合設備工具用以生長出氧化物第一覆蓋層以及沈積氮化物或氮氧化物；以及圖6A和6B是闡明根據本揭露的其中一具體實例所製造之含有MOSFET與非平面、多閘極之NVM元件的IC的方塊圖。
本揭露一般是指向將含有電荷捕獲閘級堆疊之記憶體元件整合至互補式金氧半導體製造流程的方法。
為了提供對本發明的徹底理解，在下面的敘述中，許多具體細節會被說明，像是具體的配置、組成和製程等。在其他例子中，沒有特別詳細地描述熟知的製程和製造技術以避免不必要的模糊本發明。進一步地，要了解到顯示在圖式中的各種具體實例僅是代表性說明且沒有必要按照比例繪製。
用於本文中的術語"在…上方"，"在…之上"，"在…之間"和"在…上面"是表示一層與其他層的相對位置。一層沈積或設置在另一層的上方或下方可以是直接與其他層接觸或可以是具有一或多個介於其中的層。一層沈積或設置在層之間可以是直接與該些層接觸或可以是具有一或多個 介於其中的層。相反的，第一層在第二層上面是指和第二層接觸。
一個整合包含金屬氧化物半導體場效電晶體(MOSFET)和含有電荷捕獲閘級堆疊的非揮發性記憶體元件之電路的方法具體實例將參考圖1和2A到2Q被詳細的說明。圖1是闡明一種製造包含金屬氧化物半導體場效電晶體(MOSFETs)與帶有電荷捕獲閘級堆疊的非揮發性記憶體(NVM)元件之積體電路(IC)的方法具體實例的流程圖。圖2A-2Q是闡明在根據圖1方法製造IC期間的IC截面方塊圖。
參考圖1和2A，製程從在基板206的第一區204形成供記憶體元件的通道202和在基板的第二區210形成供一或多個金屬氧化物半導體(Metal-Oxide-Semiconductor，MOS)元件的通道208開始(步驟102)。基板206可以是由適合用於半導體元件製造之單晶材料所組成的傳統矽晶圓(bulk wafer)，或可包括形成在基板上之適合材料的頂部磊晶層。適合的材料包括但不限於，矽、鎵、矽-鎵或III-V化合物半導體材料。
一般而言，通道202、208是藉由在第一區204和第二區210透過襯墊氧化層211植入適當的離子種類。例如，可用從約5到約100千電子伏特(keV)的能量和從約1e14 cm-2到約1e16 cm-2的劑量植入BF2以形成N-型非揮發性記憶體元件。P-型元件可同樣藉由以適當的劑量和能量植入砷或磷離子來形成。要理解的是可使用植入在基板206的兩區域同時形成通道202、208，或使用標準光刻技術分開形成，該光刻技術包括圖樣化光阻層以遮罩其中一個區域。襯墊氧化層211是具有從約10奈米(nm)到約20nm厚度的二氧化矽(SiO2)，且其可藉由熱氧化製程或臨場蒸氣產生技術(ISSG)生長。
在一些具體實例中，像是所顯示的，可在基板206上形成隔離結構212以將形成在第一區204的記憶體元件與形成在第二區210的MOS元件電性隔離。隔離結構212是在形成襯墊氧化層211和通道202、208之前形成，且可藉由任何傳統的技術形成，例如但不限於，淺溝渠隔離(STI)或矽局部氧化(LOCOS)。
接著，參考圖1和2B，一圖樣化遮罩層215形成在襯墊氧化層211上面或將其覆蓋，且襯墊氧化層被蝕刻或圖樣化以從基板206的第一區204移除氧化層(步驟104)。圖樣化遮罩層215可包括使用標準光刻技術的光阻層圖樣化，且可使用濕式或乾式蝕刻製程蝕刻或移除襯墊氧化層211以停止在基板206的表面上。在一例示具體實例中，襯墊氧化層211係使用含有表面活性劑之10：1的緩衝氧化蝕刻劑(BOE)在濕式清洗製程中移除。或者，濕式清洗製程可使用20：1的BOE濕式蝕刻、50：1的氫氟酸(HF)濕式蝕刻、襯墊蝕刻、或任何其他類似於以氫氟酸為基礎的濕式蝕刻化學品。
參考圖1和2C，形成介電堆疊214，其係從至少在基板206的第一區204的記憶體元件的通道202之上形成一穿隧介電質216開始(步驟106)。穿隧介電質216可為適合允許電荷載體在施以閘極偏壓情況下穿隧至電荷捕獲層的任何材料且具有任何厚度，同時維持當記憶體元件未被偏壓時的適當漏電屏障。在某些具體實例中，穿隧介電質216是二氧化矽、氮氧化矽或其之組合，且可藉由熱氧化製程、臨場蒸氣產生技術(ISSG)或自由基氧化生長。
例如，在一具體實例中，二氧化矽穿隧介電質216可在自由 基氧化製程中生長，其涉及將氫氣(H2)和氧氣(O2)以兩者約1：1的比例流至製程腔室而不需要點火的事件，像是形成電漿，其在其他方面係典型用於將H2和O2裂解形成蒸氣。取而代之的，H2和O2被允許於範圍在約-900-1000°C的溫度和範圍在約0.5-5托耳(Torr)的壓力下反應以在基板表面形成自由基，像是OH自由基、HO2自由基或O雙自由基。自由基氧化製程是在範圍在約1-10分鐘的持續時間下進行以產生具有厚度從約1.5奈米(nm)到約3.0nm的穿隧介電質216，其係藉由氧化和消耗基板的曝露表面達到。要了解的是在此圖和之後的圖中穿隧介電質216的厚度相對於襯墊氧化層211被誇張，其是約7倍厚以達到清楚的目的。在自由基氧化製程中生長的穿隧介電質216比藉由濕式氧化技術形成的穿隧介電質(即便是在減少的厚度下)稠密且由較少的氫原子/cm3組成，在某些具體實例中，自由基氧化製程是在批量處理腔室或能夠處理多個基板的熔爐中進行以提供高品質的穿隧介電質216而不影響製造設備可能的生產量(晶圓/小時)要求。
在另一具體實例中，穿隧介電質216是藉由化學氣相沈積法(CVD)或原子層沈積法沈積，且由一介電層組成，其可包括但不限於二氧化矽、氮氧化矽、氮化矽、氧化鋁、氧化鉿、氧化鋯、矽酸鉿、矽酸鋯、氮氧化鉿、鉿鋯氧化物和氧化鑭。在另一具體實例中，穿隧介電質216為一具有例如但不限於二氧化矽或氮氧化矽之底層材料與可包括但不限於氮化矽、氧化鋁、氧化鉿、氧化鋯、矽酸鉿、矽酸鋯、氮氧化鉿、鉿鋯氧化物和氧化鑭之頂層材料的雙層介電區。
參考圖1和2D，一電荷捕獲層218形成在穿隧介電質216上面或將其覆蓋(步驟108)。一般而言，如具體實例中所示，電荷捕獲層218 是一多層電荷捕獲層，其包括至少較接近穿隧介電質216之一較低或第一電荷捕獲層218a以及相對於第一電荷捕獲層為缺乏氧且含有多層電荷捕獲層中主要電荷捕獲分布之一第二電荷捕獲層218b。
電荷捕獲層218的第一電荷捕獲層218a可包括氮化矽(Si3N4)、富含矽的氮化矽或氮氧化矽(SiOxNy(Hz))。例如，第一電荷捕獲層218a可包括具有厚度介於2.0nm到4.0nm的氮氧化矽層，其係藉由CVD製程使用二氯矽烷(DCS)/氨(NH3)和一氧化二氮(N2O)/NH3氣體混合物以設計用來提供富含矽和富含氧之氮氧化物層的比例與流速獲得。
然後多層電荷捕獲層218的第二電荷捕獲層218b形成於第一電荷捕獲層218a之上。第二電荷捕獲層218b可包括氮化矽及具有氧、氮和/或矽之化學計量組成與第一電荷捕獲層218a不同的氮氧化矽層。第二電荷捕獲層218b可包括具有介於2.0nm和5.0nm的厚度，且可藉由CVD製程使用含有DCS/NH3和N2O/NH3氣體混合物的製程氣體以設計用來提供富含矽和缺乏氧之頂部氮化物層的比例與流速來形成或沈積。
如本文中所使用，術語"富含氧"和"富含矽"係相對於化學計量的氮化矽而言，或"氮化物"在本領域中一般是指具有(Si3N4)組成且具有約2.0的折射率者。因此，"富含氧"的氮氧化矽需要從化學計量的氮化矽往較高wt.%的矽和氧移動(即，減少氮)。因此，富含氧的氮氧化矽膜更像二氧化矽且RI減少到純二氧化矽的1.45 RI。類似地，描述於本文中的"富含矽"膜需要從化學計量的氮化矽往較高wt.%的矽移動且帶有比"富含氧"膜少的氧。因此，富含矽的氮氧化矽膜更像矽且RI增加到純矽的3.5 RI。
在一些具體實例中，多層電荷捕獲層218是一分離的電荷捕 獲層，其進一步含有一薄的中間氧化層220將第一電荷捕獲層218a和第二電荷捕獲層218b分開。中間氧化層220係實質地減少了在設計穿隧到第一電荷捕獲層218a期間之電荷聚集在第二電荷捕獲層218b邊界的機率，導致比傳統記憶體元件低的漏電流。
在一具體實例中，中間氧化層220係藉由氧化至選擇的深度而形成，其係使用熱或自由基氧化。自由基氧化可例如在1000-1100℃的溫度使用單晶圓工具進行，或在800-900℃使用批式反應器工具進行。H2和O2氣體混合物可以大約1：1的比例，以及在批式製程中300-500微托耳(micro Torr，mTorr)或使用單氣相工具10-15mTorr的壓力，使用單晶圓工具以1-2分鐘的時間或使用批式製程以30分鐘到1小時的時間，被導入至製程腔室中。在一些具體實例中，自由基氧化製程不具有點火事件，像是形成電漿，其在其他方面係典型用於將H2和O2裂解形成蒸氣。取而代之的，H2和O2被允許在第一電荷捕獲層218a的表面反應形成自由基，像是OH自由基、HO2自由基或O雙自由基，以形成中間氧化層220。
參考圖1和2E，一覆蓋層222形成在介電堆疊214或電荷捕獲層218上面或將其覆蓋(步驟110)。在一些具體實例中，像是所顯示的，覆蓋層222係一多層覆蓋層，其含有至少一較低或第一覆蓋層222a覆蓋電荷捕獲層218和覆蓋第一覆蓋層222a的第二覆蓋層222b。
在一具體實例中，第一覆蓋層222a可包括高溫氧化物(HTO)，像是氧化矽(SiO2)，其具有界於2.0nm和4.0nm的厚度，並以低壓化學氣相沈積(LPCVD)熱氧化製程沈積。例如，氧化製程可包括將基板206在沈積腔室中曝露至矽源，像是矽烷、氯矽烷或二氯矽烷，以及含氧氣體， 像是O2或N2O，在從約50mTorr到約1000mTorr的壓力，經過從約10分鐘到約120分鐘的期間且同時維持基板在從約900℃到約1000℃的溫度。在一些具體實例中，氧化製程是在與用於形成第二電荷捕獲層218b的相同製程腔室中原地進行，且馬上接在第二電荷捕獲層形成之後。
第二覆蓋層222b可包括氮化矽、富含矽的氮化矽或富含矽的氮氧化矽層，其具有界於2.0nm到4.0nm的厚度且係藉由CVD製程使用N2O/NH3和DCS/NH3氣體混合物形成。
參考圖1和2F，犧牲氧化層224係形成在覆蓋層222上面或將其覆蓋(步驟112)。在一具體實例中，犧牲氧化層224可包括藉由熱氧化製程或自由基氧化生長的高溫氧化物(HTO)層，且其具有介於2.0nm和4.0nm的厚度。在另一具體實例中，犧牲氧化層224可藉由化學氣相沈積製程在低壓化學氣相沈積(LPCVD)腔室中形成或沈積。例如，犧牲氧化層224可藉由CVD製程使用含有矽烷或DCS與含氧氣體之氣體混合物的製程氣體沈積，該含氧氣體例如為O2或N2O，其以設計用來提供二氧化矽(SiO2)犧牲氧化層的比例與流速進行。
接著，參考圖1和2G，圖樣化遮罩層226係形成在犧牲氧化層224上面或將其覆蓋，且參考圖2H，被蝕刻或圖樣化以形成閘極堆疊228之犧牲氧化層、覆蓋層222和介電堆疊214覆蓋記憶體元件的通道202，以及從基板206的第二區210移除犧牲氧化層、覆蓋層和介電堆疊(步驟114)。圖樣化遮罩層226可包括使用標準光刻技術的光阻層圖樣化，且可使用含有一或多個分開步驟的乾式蝕刻製程蝕刻或移除犧牲氧化層224、覆蓋層222和介電堆疊214以使其停止在穿隧介電質216的表面和襯墊氧化層 211。
參考圖1和2I，犧牲氧化層224以及部分或實質上全部的最頂部或在多層中的第二覆蓋層222b、覆蓋層222係從閘極堆疊228以一高度選擇清洗製程中被移除(步驟116)。此清洗製程進一步移除任何氧化物，像是留在閘極堆疊228外之第一區204中和在第二區210中的氧化物穿隧介電質216和襯墊氧化層211以準備基板206在該區中的閘極氧化層生長。在一例示性的實施中，犧牲氧化層224和第二覆蓋層222b係以濕式清洗製程使用10：1之含有界面活性劑的緩衝氧化蝕刻劑(BOE)移除。或者，濕式清洗製程可使用20：1的BOE濕式蝕刻、50：1的氫氟酸(HF)濕式蝕刻、襯墊蝕刻或任何其他類似於以氫氟酸為基礎的濕式蝕刻化學品來進行。
接者，參考圖1和2J，進行氧化製程以將留下的覆蓋層222或多層中的第一覆蓋層222a、覆蓋層和視情況地部分第二電荷捕獲層218b氧化以形成阻擋氧化層230覆蓋在第二電荷捕獲層上。在一具體實例中，氧化製程被調適以氧化第一覆蓋層222a形成阻擋氧化層230，同時氧化至少部分在第二區210的基板206表面以形成第一閘極氧化層232覆蓋在至少一MOS元件的至少通道208上(步驟118)。氧化製程可包括原地蒸氣生成(ISSG)、CVD或自由基氧化，其係在批式或單一基板製程腔室中使用或不使用點火事件像是電漿來進行。例如，在一具體實例中，阻擋氧化層230和閘極氧化層232可在自由基氧化製程中生長，其係涉及將氫氣(H2)和氧氣(O2)以彼此大約1：1的比例不使用點火事件像是形成電漿而流至製程腔室，該點火事件典型是用於將H2和O2裂解形成蒸氣。取而代之的，H2和O2被允許在覆蓋層222的表面或第一覆蓋層222a的表面在大約700-800℃的溫 度在大約0.5-5Torr範圍的壓力下反應形成自由基，像是OH自由基、HO2自由基或O雙自由基。自由基氧化製程是在大約10-15分鐘的持續時間下進行以藉由氧化和消耗第一覆蓋層222a和具有從約3nm到約4.5nm厚度的部分第二電荷捕獲層218b以及具有從約5nm到約7nm厚度的閘極氧化層232而達到阻擋氧化層230生長的目的。
在一些具體實例中，像是圖2k到2Q所顯示，該方法進一步包括雙閘極氧化層製造流程以能夠製造MOS元件234和高壓(High Voltage，HV)MOS元件236。參考圖1和2K，圖樣化遮罩層238係形成在基板206的第一和第二區域204，210之上(步驟120)。圖樣化遮罩層238可為使用標準光刻技術的光阻層圖樣化，且包括至少一開口240在第二區210的通道208之上。厚的第一閘極氧化層232在曝露區域藉由使用BOE蝕刻進行蝕刻，其係在類似於該些敘述於上關於移除犧牲氧化層224的條件下進行，且然後圖樣化遮罩層238被移除。
參考圖1和2L，基板206使用那些不會蝕刻氧化層的濕式蝕刻清洗，以保護HV MOS元件236的第一閘極氧化層232以及閘極堆疊228的阻擋氧化層230和第一閘極氧化層232(步驟122)。然後將基板206進行熱氧化製程以生產具有厚度從約1.5nm到約3nm之薄的第二閘極氧化層242。
在一些具體實例中，可使用薄的高介電常數或高-k介電材料代替二氧化矽。高-k介電材料可包括但不限於，氧化鉿、氧化鋯、矽酸鉿、氮氧化鉿、鉿鋯氧化物和氧化鑭，其係藉由例如下述製程沈積：原子層沈積(ALD)、物理氣相沈積(PVD)、化學氣相沈積(CVD)、低壓CVD(LPCVD) 或電漿增強CVD(PECVD)製程。
參考圖1和2M，任何適用於調節記憶體元件偏壓和MOS元件操作之導電或半導體材料的閘極層244係形成於閘極堆疊228、HV MOS元件236的第一閘極氧化層232以及MOS元件234的第二閘極氧化層242之上(步驟124)。在一具體實例中，閘極層係藉由物理氣相沈積形成且由含金屬材料組成，其可包括但不限於，金屬氮化物、金屬碳化物、金屬矽化物、鉿、鋯、鈦、鉭、鋁、釕、鈀、鉑、鈷和鎳。在另一具體實例中，閘極層係藉由CVD製程形成且由經摻雜的多晶矽組成。
參考圖1和2N，使用遮罩層(未顯示)和標準光刻技術將閘極層244圖樣化以停止在阻擋氧化層230、第一閘極氧化層232和第二閘極氧化層242的表面，從而形成記憶體元件248之閘極堆疊228的閘極246、HV MOS元件236的閘極250以及MOS元件234的閘極252(步驟126)。
參考圖1和2O-2P，側壁隔離層254與所有元件的閘極246、250、252相鄰形成，且留下的阻擋氧化層230、第一閘極氧化層232和第二閘極氧化層242的曝露部分係被異向性地蝕刻以得到如圖2P顯示的結構，其實質帶有完整的記憶體元件248、HV MOS元件236以及MOS元件234(步驟128)。
參考圖1和2Q，記憶體元件248、HV MOS元件236和MOS元件234的閘極堆疊實質完成後，可執行尖端和/或環形植入以形成延伸區域256，執行源極和汲極植入以形成所有元件的源極和汲極區域258(步驟130)。
在其他具體實例中，覆蓋層可包括單層或多層的氮化矽或氮 氧化矽。覆蓋層322可為具有同質組成物的單層氮化矽或氮氧化矽、具有梯度化學劑量組成物的單層氮化矽或氮氧化矽，或如具體實例中所示，可為多層，覆蓋層含有至少一具有氮化物之較低或第一覆蓋層322a覆蓋電荷捕獲層318以及具有氮化物的第二覆蓋層322b覆蓋第一覆蓋層322a。
參考圖3A，一種使用多層，覆蓋層322製造含有MOSFET和非-NVM元件之積體電路(IC)的方法，其從在基板306表面之上形成穿隧介電質316和電荷捕獲層318開始。穿隧介電質316、電荷捕獲層318和基板306具有如上述圖1和2A到2D所描述的組成和/或可如上述圖1和2A到2D所描述般形成。一般而言，如具體實例中所顯示，電荷捕獲層318是一多層電荷捕獲層，其含有至少較靠近穿隧介電質316之一較低或第一電荷捕獲層318a以及相對第一電荷捕獲層缺乏氧且含有在多層電荷捕獲層中主要的電荷捕獲分布之一第二電荷捕獲層318b。視情況地，電荷捕獲層318可為分離的電荷捕獲層，進一步含有一薄的中間氧化層(此圖中未顯示)將第一電荷捕獲層318a和第二電荷捕獲層318b分開，如上面關於圖2D的描述。
第一覆蓋層322a可包括氮化矽、富含矽的氮化矽或富含矽的氮氧化物矽層，其具有介於2.0nm和4.0nm之間的厚度，且係藉由使用N2O/NH3和DCS/NH3氣體混合物的CVD製程形成。類似地，第二覆蓋層322b也可包括氮化矽、富含矽的氮化矽或富含矽的氮氧化矽層，其具有介於1.5nm和4.0nm之間的厚度，且係藉由使用N2O/NH3和DCS/NH3氣體混合物的CVD製程形成。視情況地，第一覆蓋層322a和第二覆蓋層322b可包括不同的化學計量。例如，第一覆蓋層322a可具有矽或富含氧的組成物，例如，第一覆蓋層可包括富含氧-氮化物或具有實質上和第一電荷捕獲層318a相同 化學計量組成的氮氧化物以促進隨後的第一覆蓋層氧化。
類似地，第二覆蓋層322b也可包括氮化矽、富含矽的氮化物或富含矽的氮氧化物層，其具有介於1.5nm和4.0nm之間的厚度，且係藉由使用N2O/NH3和DCS/NH3氣體混合物的CVD製程形成。視情況地，第二覆蓋層322b可具有實質上和第二電荷捕獲層318b相同的化學計量組成，即相對於第一覆蓋層322a為缺乏氧的。
接著，犧牲氧化層324形成在介電覆蓋層322上面或將其覆蓋。犧牲氧化層324可具有實質上和犧牲氧化層224組成完全相同的組成，且可如上面關於該層描述般形成。
接著，犧牲氧化層324、電荷捕獲層318和覆蓋層322被根據圖2G到2H所描述般圖樣化以在基板306的第一或NVM區形成閘極堆疊328，並從第二或MOS區移除該些層(未顯示於此圖中)。
參考圖3B，犧牲氧化層324和部分或實質上全部頂部或第二覆蓋層322b以高度選擇性清洗製程被從閘極堆疊328移除。此清洗製程可為實質上與上面關於圖2I描述的閘極氧化物(Gate Oxide，GOX)預清洗是相同的。
參考圖3C，執行氧化製程以氧化覆蓋層322或多層覆蓋層的第一覆蓋層322a，以及部分第二電荷捕獲層318b的留下部分以形成覆蓋在第二電荷捕獲層上的阻擋氧化層330。氧化製程可為實質上與上面關於圖2J的描述是相同的。在一些具體實例中，該氧化製程係用於同時地形成至少一基板第二區之MOS元件的閘極氧化層或電晶體(未顯示於此圖中)。
此製造流程接著以實質上如上面關於圖2H到2Q的描述般 繼續以完成NVM和MOS元件或電晶體的製造。
在又一具體實例中，關於圖4A-4F的描述，多層中的第一覆蓋層、覆蓋層含有使用濕式熱氧化製程或臨場蒸氣產生技術(ISSG)製程生長而非沈積的氧化矽。
參考圖4A，該方法從在基板406表面上方形成穿隧介電質416和含有第一電荷捕獲層418a與第二電荷捕獲層418b的電荷捕獲層418開始。穿隧介電質416、電荷捕獲層418和基板406具有上面關於圖1與圖2A到2D描述的組成和/或可用上面關於圖1與圖2A到2D描述般形成。接著，第一犧牲氧化層423可形成在第二電荷捕獲層418b上面或將其覆蓋。犧牲氧化層423可具有實質上和犧牲氧化層224與324組成相同之組成，且可如上面關於該些層描述般形成。
接著，參考圖4B，第一犧牲氧化層423以一實質上與描述於上關於圖21和3B的GOX預清洗相同的清洗製程移除。如同這些清洗製程，移除第一犧牲氧化層423的清洗製程也可移除部份下面的第二電荷捕獲層418b。
接著，參考圖4C，第一覆蓋層422a係使用濕式熱氧化製程ISSG製程形成在第二電荷捕獲層418b上面或將其覆蓋。一般而言，ISSG製程係在ISSG腔室中使用在至少約1000℃的水執行或進行。
接著，參考圖4D，基板回到使用的工具上以形成初始介電堆疊的穿隧介電質416和電荷捕獲層418，且第二覆蓋層422b形成在第一覆蓋層422a上面或將其覆蓋。一般而言，第二覆蓋層422b可具有與描述於上之第二覆蓋層222b和322b組成相同的組成，且可包括氮化矽、富含矽的 氮化矽或富含矽的氮氧化矽層，其具有介於2.0nm和4.0nm之間的厚度，是藉由使用N2O/NH3和DCS/NH3氣體混合物的CVD製程形成。第二犧牲氧化層424形成在第二覆蓋層222b上面或將其覆蓋。一般而言，犧牲氧化層424具有介於2.0nm和4.0nm之間的厚度以及與犧牲氧化層224、324和423組成實質相同的組成，可如上面關於該些層描述般形成。犧牲氧化層424、覆蓋層422和穿隧介電質416以及電荷捕獲層418係被蝕刻或圖樣化以形成覆蓋在記憶體元件之通道402的閘極堆疊428和移除犧牲氧化層、覆蓋層與來自基板第二區的介電堆疊(未顯示於此圖中)。
參考圖4E，犧牲氧化層424和部分或實質上全部頂部或第二覆蓋層422b以高度選擇性清洗製程從閘極堆疊428被移除。此清洗製程可為實質上與上面關於圖2I描述的GOX預清洗是相同的。
最後，參考圖4F，執行氧化製程以氧化留下的部分覆蓋層422或多層的第一覆蓋層422a、覆蓋層以及部分的第二電荷捕獲層418b以形成阻擋氧化層430覆蓋於第二電荷捕獲層。氧化製程可為實質上與上面關於圖2J的描述是相同的。在一些具體實例中，該氧化製程係用於同時地形成至少一基板第二區之MOS元件的閘極氧化層或電晶體(未顯示於此圖中)。
此製造流程接著以實質上如上面關於圖2H到2Q的描述般繼續以完成NVM和MOS元件或電晶體的製造。
在另一可替代的具體實例中，含有MOSFET和帶有電荷捕獲閘級堆疊之NVM元件的IC係使用帶有分開沈積腔室的組合設備工具來生長氧化第一覆蓋層和沈積氮化物或氮氧化物而製造。適合的單晶圓組合 設備工具包括，例如，商業上可從位於加州聖塔克拉拉(Santa Clara,Calif.)之應用材料公司(Applied Materials,Inc)獲得的CenturaTM平台。
參考圖5的流程圖，本方法從藉由ISSG在組合設備工具的第一腔室(腔室1)生長穿隧氧化層(TUNOX)開始(步驟502)。接著，基板被轉移至組合設備工具的第二腔室(腔室2)並沈積多層電荷捕獲層的底部(B_SiN)和頂部(T_SiN)氮化矽層(步驟504)。用於沈積底部和頂部層的組成和製程係與該些描述於上關於圖1和圖2A到2D者實質相同。接著，基板回到組合設備工具的第一腔室(腔室1)，且將會作為多層之第一層、覆蓋層之一薄的氧化層係生長在頂部(T_SiN)層(步驟506)。用於生長薄的氧化層之組成和製程係與該些描述於上關於第一覆蓋層422a的濕式熱氧化製程或ISSG製程實質相同。基板回到組合設備工具的第二腔室(腔室2)且將會作為多層之第二層的第二氮化矽層(第二T_SiN)係生長在薄的氧化第一覆蓋層的頂部(步驟508)。在使用組合設備工具執行的最後步驟中，基板被轉移至組合設備工具的第三腔室(腔室3)且犧牲氧化層沈積在第二氮化矽層上方(步驟510)。沈積犧牲氧化層的組成和製程係與該些描述於上關於犧牲氧化層的乾式熱氧化製程實質相同。然後從組合設備工具移除基板，執行清潔以移除犧牲氧化層和全部或實質上全部的第二氮化矽層，且執行氧化製程以氧化該薄的氧化層或第一覆蓋層和部分在下方的頂部電荷捕獲層以形成在電荷捕獲層上的阻擋氧化層(步驟512)。
此製造流程接著以實質上如上面關於圖2H到2Q的描述般繼續以完成NVM和MOS元件或電晶體的製造。
另一方面，本揭露係指向含有電荷捕獲區域的多閘極或多閘 極-表面記憶體元件，該電荷捕獲區域係覆蓋在基板表面上面或之上形成的通道的二或多側，以及指向製造其之方法。一般非平面多閘極元件包括水平或垂直通道形成於基板表面上面或上方且被其三或多側被閘極包圍。
圖6A闡述含有在基板606的第一區604形成之非平面多閘極記憶體元件602且在第二區610與其相鄰整合形成之MOS元件608的積體電路600的一具體實例。
參考圖6A，記憶體元件602，一般是指finFET，包括從覆蓋在基板606之表面616的半導體材料的薄膜或層形成的通道614，其連接記憶體元件的源極618和汲極620。通道614被鳍状物三側圍繞，其形成元件的閘極堆疊622。閘極堆疊622(以從源極到汲極的方向測量)的厚度決定了產生作用的元件通道長度。
根據本發明的揭露，圖6A的非平面多閘極記憶體元件602可包括多層電荷捕獲層和阻擋氧化層，其係藉由氧化和消耗覆蓋層以及部分的電荷捕獲層形成。圖6B是圖6A之含有部分基板606、通道614和閘極堆疊622的非平面記憶體元件的部分截面圖。閘極堆疊622包括覆蓋升起之通道614的穿隧介電質624、電荷捕獲層626、阻擋氧化層628和覆蓋阻擋層的閘極層630以形成記憶體元件602的控制閘極。如上面所描述，閘極層630可包括經摻雜的多晶矽或金屬層。通道614和閘極堆疊622可直接形成在基板606上或形成在一絕緣或介電層632上，例如埋氧層，其係形成於基板的上面或之上。
雖然沒有顯示在這些圖式中，將會了解的是電荷捕獲層626可為含有至少一較低或第一電荷捕獲層的多層電荷捕獲層以及一較高或第 二電荷捕獲層覆蓋該第一電荷捕獲層，該較低或第一電荷捕獲層含有較接近穿隧介電質624的氮化物。一般而言，第二電荷捕獲層含有富含矽、缺乏氧之氮化物層且含有分布在多層電荷捕獲層中主要的電荷捕獲，而第一電荷捕獲層含有富含氧的氮化物或氮氧化矽，且是相對頂部電荷捕獲層而言為富含氧的，以此減少其中的電荷捕獲數量。富含氧是指其中在第一電荷捕獲層中的氧氣濃度從約15到約40%，而在第二電荷捕獲層的氧氣濃度少於約5%。在一些具體實例中，多層電荷捕獲層進一步包括至少一薄的，居間或中間氧化層使第二電荷捕獲層與第一電荷捕獲層分開。
最後，阻擋氧化層628可包括藉由氧化和消耗覆蓋層與部分電荷捕獲層626形成的氧化層，如上面關於圖2A-2Q的描述。
在顯示於圖6A的具體實例中，MOS元件608也是finFET，且包括從覆蓋在基板606之表面616的半導體材料的薄膜或層形成的通道634，其連接MOS元件的源極636和汲極638。通道634也被鳍状物或閘極三側圍繞，其形成MOS元件608的閘極640。參考圖6B，MOS元件608的閘極640包括閘極氧化層642覆蓋升起的通道634和金屬或經摻雜的多晶矽閘極層644覆蓋該閘極氧化層。
因此，已描述了包含MOSFET與含有電荷捕獲閘級堆疊之非揮發性記憶體元件的積體電路的具體實例和形成其之方法。雖然本揭露已經參考具體的例示具體實例描述，但是明顯的是，在不偏離揭露的廣泛精神和範疇下，可對這些具體實例作各種修改和改變。因此，說明書和圖式係作為說明性的而非限制的意思。
提供本揭露的摘要以符合37 C.F.R.§1.72(b)，其要求摘要允 許讀者快速得知技術揭露的一或多個具體實例之本質。其提交應理解並非用於解釋或限制本申請專利範圍的範疇或意圖。此外，前面的詳細敘述可被看作是各種特徵群組在一起於一單一具體實例中，其係為了簡化揭露的目的。此揭露方式並不解釋為反映所聲稱的具體實例需要比清楚列舉在每個申請專利範圍更多的特徵之意圖。而是如同下面的申請專利範圍所反映，發明的標的在於少於單一揭露的具體實例之所有特徵。因此，下面的申請專利範圍從而併入詳細說明中，且每個申請專利範圍以其本身作為一分開的具體實例。
在敘述中提到的一個具體實例或一具體實例係指與具體實例中描述相關之特別的特徵、結構或特點係包括至少一電路或方法的具體實例。一個具體實例之詞句的表意在說明書中的各個地方並不必然指向相同的具體實例。

Claims (19)

  1. 一種製造半導體裝置的方法，其包含：在基板上形成一介電堆疊，該介電堆疊含有一穿隧介電質在該基板之上以及一電荷捕獲層在該穿隧介電質之上；在介電堆疊之上形成含有高溫矽氧化物的一第一覆蓋層；在第一覆蓋層之上形成含有氮化物的一第二覆蓋層；圖樣化該第一和第二覆蓋層與該介電堆疊以在基板的第一區中形成一記憶體元件的閘極堆疊；移除該第二覆蓋層；以及執行氧化製程以在該電荷捕獲層之上形成一阻擋氧化層，其中該氧化製程消耗該第一覆蓋層。
  2. 如申請專利範圍第1項的方法，其中形成所述第一覆蓋層包括使用低壓氧化製程在用於形成介電堆疊的腔室中原地執行高溫氧化物(HTO)的沈積。
  3. 如申請專利範圍第1項的方法，其中該氧化製程消耗部分的電荷捕獲層。
  4. 如申請專利範圍第1項的方法，其中，該氧化製程不實質地消耗任何的電荷捕獲層。
  5. 如申請專利範圍第1項的方法，其進一步包含在第二覆蓋層之上形成一犧牲氧化層，且其中圖樣化以形成閘極堆疊包含圖樣化犧牲氧化層、第一和第二覆蓋層以及介電堆疊以形成在基板第一區中之該記憶體元件的該閘極堆疊，且同時地從基板的第二區移除犧牲氧化層、第一和第二覆蓋 層以及介電堆疊。
  6. 如申請專利範圍第5項的方法，其中移除第二覆蓋層包含從該閘極堆疊移除犧牲氧化層和第二覆蓋層，且同時地從該基板的該第二區移除任何殘留的氧化物。
  7. 如申請專利範圍第6項的方法，其中執行該氧化製程以形成該阻擋氧化層包含同時地在基板第二區中形成邏輯元件的閘極氧化層。
  8. 一種製造半導體裝置的方法，其包含：在一基板上形成一介電堆疊，該介電堆疊含有一穿隧介電質在該基板之上以及一電荷捕獲層在該穿隧介電質之上；在介電堆疊之上形成一富含氧-氮化物的第一覆蓋層；在第一覆蓋層之上形成一含有氮化物的第二覆蓋層；圖樣化該第一和第二覆蓋層以及該介電堆疊以在基板的第一區中形成一記憶體元件的閘極堆疊；移除該第二覆蓋層；以及執行一氧化製程以在該電荷捕獲層之上形成一阻擋氧化層，其中該氧化製程消耗該第一覆蓋層，其中所述電荷捕獲層包含多層電荷捕獲層，所述多層電荷捕獲層包含至少第一氮化物層接近所述穿隧介電質，並且其中所述第一覆蓋層和所述多層電荷捕獲層的所述第一氮化物層含有實質上相同的化學計量組成。
  9. 如申請專利範圍第8項的方法，其中該多層電荷捕獲層進一步包含在該第一氮化物層之上的一第二氮化物層，該第二氮化物層相對於第一氮化物層為缺乏氧且含有多層電荷捕獲層中主要電荷捕獲分布。
  10. 如申請專利範圍第9項的方法，其中該第二覆蓋層和多層電荷捕獲層中的第二氮化物層含有實質上相同的化學計量組成。
  11. 如申請專利範圍第8項的方法，其進一步包含在第二覆蓋層之上形成一犧牲氧化層，且其中圖樣化以形成該閘極堆疊包含有圖樣化該犧牲氧化層、該第一和第二覆蓋層以及該介電堆疊以形成在基板第一區中之記憶體元件的該閘極堆疊，以及從基板的一第二區移除該犧牲氧化層、該第一和第二覆蓋層和該介電堆疊。
  12. 如申請專利範圍第11項的方法，其中移除該第二覆蓋層包括從閘極堆疊移除該犧牲氧化層和該第二覆蓋層，且同時地從基板的該第二區移除氧化層。
  13. 如申請專利範圍第12項的方法，其中執行該氧化製程以形成該阻擋氧化層包含同時地在基板的該第二區中形成邏輯元件的閘極氧化層。
  14. 一種製造半導體裝置的方法，其包含：在一基板上形成一介電堆疊，該介電堆疊含有一穿隧介電質在該基板之上以及一電荷捕獲層在該穿隧介電質之上；在一組合設備工具的第一腔室中於該介電堆疊之上生長含有一薄氧化層的一第一覆蓋層；在該組合設備工具的第二腔室中於該第一覆蓋層之上形成含有氮化物的一第二覆蓋層；在該組合設備工具的第三腔室中於該第二覆蓋層之上使用自由基氧化製程形成含有高溫氧化物(HTO)的一犧牲氧化層；圖樣化該犧牲氧化層、該第一和第二覆蓋層以及該介電堆疊以在基板 的一第一區中形成一記憶體元件的一閘極堆疊；移除該犧牲氧化層和該第二覆蓋層；以及執行一氧化製程以在該電荷捕獲層之上形成一阻擋氧化層，其中該氧化製程消耗該第一覆蓋層。
  15. 如申請專利範圍第14項的方法，其中該電荷捕獲層包括一多層電荷捕獲層，其含有至少一第一氮化物層，該第一氮化物層較接近穿隧介電質；以及在該第一氮化物層之上的一第二氮化物層，該第二氮化物層相對於第一氮化物層為缺乏氧且含有多層電荷捕獲層中主要電荷捕獲分布。
  16. 如申請專利範圍第15項的方法，其中該第二覆蓋層和多層電荷捕獲層中的第二氮化物層含有實質上相同的化學計量組成。
  17. 如申請專利範圍第14項的方法，其中圖樣化以形成閘極堆疊進一步包括從基板的一第二區移除該犧牲氧化層、該第一和第二覆蓋層以及該介電堆疊。
  18. 如申請專利範圍第17項的方法，其中移除犧牲氧化層和第二覆蓋層包含同時地從基板的該第二區移除一氧化層。
  19. 如申請專利範圍第18項的方法，其中執行該氧化製程以形成該阻擋氧化層包含同時地在基板的該第二區中形成一邏輯元件的一閘極氧化層。
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