US20050215074A1 - ONO formation method - Google Patents

ONO formation method Download PDF

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US20050215074A1
US20050215074A1 US10/809,891 US80989104A US2005215074A1 US 20050215074 A1 US20050215074 A1 US 20050215074A1 US 80989104 A US80989104 A US 80989104A US 2005215074 A1 US2005215074 A1 US 2005215074A1
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oxide layer
nitride
oxide
forming
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Fuja Shone
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Skymedi Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/02126—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H01L21/0214—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being a silicon oxynitride, e.g. SiON or SiON:H
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
    • H01L21/0217—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02321—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer
    • H01L21/02323—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen
    • H01L21/02326—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment introduction of substances into an already existing insulating layer introduction of oxygen into a nitride layer, e.g. changing SiN to SiON
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02337—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/954—Making oxide-nitride-oxide device

Definitions

  • the present invention is related to a method for forming a dielectric layer in a non-volatile memory device, more specifically, to a formation method of an oxide-nitride-oxide (ONO) layer.
  • ONO oxide-nitride-oxide
  • Non-volatile memory devices are currently in wide use in electronic components that require the retention of information when electrical power is terminated.
  • Non-volatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices.
  • EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased.
  • Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
  • an EEPROM device typically includes a floating-gate electrode upon which electrical charge is stored.
  • a flash EEPROM device electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the transistor. The electron transfer is initiated by either hot electron injection or Fowler-Nordheim tunneling.
  • One important dielectric material for the fabrication of the floating-gate electrode is an ONO structure. During programming, electrical charges are transferred from the substrate to the silicon nitride layer in the ONO structure and trapped therein.
  • the ONO structure is in wide use in non-volatile memory devices.
  • FIG. 1 The ONO formation described in U.S. Pat. No. 5,168,334 is shown in FIG. 1 , which is most commonly used.
  • a bottom oxide layer 102 is thermally grown over the surface of a silicon substrate 101 , and then an overlying layer 103 of silicon nitride is deposited to a thickness of around 200 angstroms.
  • a top oxide layer 104 is deposited on the silicon nitride layer 103 , thereby an ONO layer 10 is formed.
  • U.S. Pat. Nos. 5,966,603 and 6,297,096 reveal another way of ONO formation.
  • a bottom oxide layer 202 is thermally grown on a silicon substrate 201 , followed by depositing a silicon nitride layer 203 .
  • an oxidation process is conducted to consume a part of the silicon nitride layer 203 into a top oxide layer 204 , thereby an ONO layer 20 including the bottom oxide layer 202 , the nitride layer 203 and the top oxide layer 204 is formed. It is noted that typically half of the thickness of the top oxide layer 204 comes from the consumed nitride layer 203 .
  • the silicon nitride layer 203 should be at least 50 angstroms thicker than the final desired nitride thickness, with the extra nitride being for consumption of the top oxide layer 204 .
  • the top oxide layer 104 formed by deposition may incur oxide quality issue that is harmful to isolation, and the method that the top oxide layer 204 formed by oxidation may be not be able to easily control the thickness of the nitride layer 203 . Therefore, it is necessary to develop other ONO formation methods for resolving the above-mentioned problems.
  • the objective of the present invention is to provide a method of forming an ONO layer in a non-volatile memory device, with a view to increasing process flexibility and obtaining a thicker top oxide layer of the ONO layer for specific process requirements.
  • an ONO formation method has been developed. First, a bottom oxide layer is formed on a silicon substrate, and then a silicon-rich nitride layer is deposited on the bottom oxide layer. Then, an oxidation process is performed to react with silicon atoms in the silicon-rich nitride layer, so as to form a top oxide layer.
  • the silicon-rich layer can be replaced with a combination of a nitride layer and a polysilicon layer.
  • the oxidation process can consume the polysilicon layer into the top oxide layer, and proper oxygen is introduced into the nitride layer.
  • a first oxide layer may be formed before oxidation to be a part of the top oxide layer, thereby a thicker top oxide layer of the ONO layer can be obtained.
  • the first oxide layer may be formed by low-pressure chemical vapor deposition (LPCVD) or use high-temperature oxide (HTO).
  • FIG. 1 illustrates a known ONO formation method
  • FIGS. 2 ( a ) and 2 ( b ) illustrate another known ONO formation method
  • FIGS. 3 ( a ) and 3 ( b ) illustrate the first embodiment of the ONO formation method in accordance with the present invention
  • FIGS. 4 ( a ) and 4 ( b ) illustrate the second embodiment of the ONO formation method in accordance with the present invention
  • FIGS. 5 ( a ) and 5 ( b ) illustrate the third embodiment of the ONO formation method in accordance with the present invention
  • FIGS. 6 ( a ) and 6 ( b ) illustrate the fourth embodiment of the ONO formation method in accordance with the present invention
  • FIGS. 7 ( a ) and 7 ( b ) illustrate the fifth embodiment of the ONO formation method in accordance with the present invention.
  • FIGS. 8 ( a ) and 8 ( b ) illustrate the sixth embodiment of the ONO formation method in accordance with the present invention.
  • FIGS. 3 ( a ) and 3 ( b ) illustrate the first embodiment of the ONO formation method in accordance with the present invention.
  • a bottom oxide layer 302 typically of 10-100 angstroms is formed on a silicon substrate 301 in which the bottom oxide layer 302 may be fabricated by oxidation in a furnace.
  • a silicon-rich nitride layer 303 typically of 10-200 angstroms is deposited on the bottom oxide layer 302 .
  • the silicon-rich nitride layer 303 is then conducted to introduce proper oxygen into the silicon-rich nitride layer 303 , thereby a top oxide layer 304 ranging from 20 to 200 angstroms is formed by consuming extra silicon atoms in the silicon-rich nitride layer 303 . Accordingly, the silicon-rich nitride layer 303 may be transformed into a thinner nitride layer 303 ′ of less silicon concentration. Nevertheless, the thickness of the nitride layer 303 ′ is not far less than that of the silicon-rich nitride layer 303 due to the high concentration of silicon atoms in the silicon-rich nitride layer 303 . As a result, an ONO layer 30 including the bottom oxide layer 302 , the nitride layer 303 ′ and the top oxide layer 304 is formed.
  • FIGS. 4 ( a ) and 4 ( b ) The second embodiment of the ONO formation method in accordance with the present invention is shown in FIGS. 4 ( a ) and 4 ( b ).
  • a bottom oxide layer 402 ranging from 10 to 100 angstroms is formed on a silicon substrate 401 , and then a nitride layer 403 ranging from 10 to 200 angstroms and a polysilicon layer 404 ranging from 10 to 100 angstroms are deposited in sequence.
  • FIG. 4 ( b ) an oxidation process at a temperature of 700-1100° C.
  • an ONO layer 40 including the bottom oxide layer 402 , the nitride layer 403 and the top oxide layer 405 is formed.
  • FIGS. 5 ( a ) and 5 ( b ) The third embodiment of the ONO formation method in accordance with the present invention is shown in FIGS. 5 ( a ) and 5 ( b ).
  • a bottom oxide layer 502 ranging from 10 to 100 angstroms is formed on a silicon substrate 501 , and then a silicon-rich nitride layer 503 ranging from 10 to 200 angstroms and a first oxide layer 504 are deposited in sequence.
  • an oxidation process at a temperature of 700-1100° C. is then conducted to consume extra silicon atoms in the silicon-rich nitride layer 503 , so as to form a second oxide layer 503 ′.
  • the second oxide layer 503 ′ together with the first oxide layer 504 form a top oxide layer 505 ranging from 20 to 200 angstroms, and thus the top oxide layer 505 is thicker than the first oxide layer 504 .
  • the first oxide layer may be formed by LPVCD or made of HTO, i.e., thermally formed in a temperature between 500-800° C. Accordingly, an ONO layer 50 including the bottom oxide layer 502 , the nitride layer 503 and the top oxide layer 505 is formed.
  • the first oxide layer 504 added before oxidation is to attain a thicker top oxide layer, so as to meet specific requirements and enhance process flexibility.
  • FIGS. 6 ( a ) and 6 ( b ) illustrate the fourth embodiment of the ONO formation method put forth in the present invention.
  • a bottom oxide layer 602 ranging from 10 to 100 angstroms is formed over the surface of a silicon substrate 601 , and a nitride layer 603 ranging from 10 to 100 angstroms, a polysilicon layer 604 ranging from 10 to 200 angstroms and a first oxide layer 605 ranging from 10 to 100 angstroms are sequentially deposited or grown thereafter.
  • an oxidation process at a temperature of 700-1100° C. is then conducted to consume polysilicon layer 604 into a second oxide layer 604 ′.
  • the second oxide layer 604 ′ together with the first oxide layer 605 forms a top oxide layer 606 ranging from 20 to 200 angstroms.
  • an ONO layer 60 including the bottom oxide layer 602 , the nitride layer 603 and the top oxide layer 606 is formed.
  • FIGS. 7 ( a ) and 7 ( b ) illustrate the fifth embodiment of the ONO formation method put forth in the present invention.
  • a bottom oxide layer 702 ranging from 10 to 100 angstroms is formed on a silicon substrate 701 , and a polysilicon layer 703 ranging from 10 to 100 angstroms and a nitride layer 704 ranging from 10 to 100 angstroms are sequentially deposited afterwards.
  • the nitride layer 704 cannot be too thick to hinder the penetration of the silicon atoms, and a thickness of 20-50 angstroms or even less is preferred. As a result, an ONO layer 70 including the bottom oxide layer 702 , the nitride layer 704 and the top oxide layer 705 is formed.
  • FIGS. 8 ( a ) and 8 ( b ) illustrate the sixth embodiment of the ONO formation method put forth in the present invention.
  • a bottom oxide layer 802 ranging from 10 to 100 angstroms is formed on a silicon substrate 801 , and then a polysilicon layer 803 ranging from 10 to 100 angstroms, a nitride layer 804 ranging from 10 to 100 angstroms and a first oxide layer 805 ranging from 20 to 200 angstroms are sequentially deposited.
  • an oxidation process is then conducted at a temperature ranging from 700-1000° C.
  • an ONO layer 80 including the bottom oxide layer 802 , the nitride layer 804 and the top oxide layer 806 is formed.
  • the objective of adding the first oxide layers 605 and 805 is to provide the thicker top oxide layers 606 and 806 , and HTO or LPCVD oxide can be selected as material thereof.

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Abstract

An ONO formation method comprises the following procedures. First, a bottom oxide layer is formed on a silicon substrate, and then a silicon-rich nitride layer is deposited on the bottom oxide layer. Then, an oxidation process is performed to react with silicon atoms in the silicon-rich nitride layer, so as to form a top oxide layer. Alternatively, the silicon-rich layer can be replaced with a combination of a nitride layer and a polysilicon layer. The oxidation process can consume the polysilicon layer into the top oxide layer, and proper oxygen is introduced into the nitride layer.

Description

    BACKGROUND OF THE INVENTION
  • (A) Field of the Invention
  • The present invention is related to a method for forming a dielectric layer in a non-volatile memory device, more specifically, to a formation method of an oxide-nitride-oxide (ONO) layer.
  • (B) Description of the Related Art
  • Non-volatile memory devices are currently in wide use in electronic components that require the retention of information when electrical power is terminated. Non-volatile memory devices include read only memory (ROM), programmable read only memory (PROM), erasable programmable read only memory (EPROM) and electrically erasable programmable read only memory (EEPROM) devices. EEPROM devices differ from other non-volatile memory devices in that they can be electrically programmed and erased. Flash EEPROM devices are similar to EEPROM devices in that memory cells can be programmed and erased electrically. However, Flash EEPROM devices enable the erasing of all memory cells in the device using a single electrical current pulse.
  • Typically, an EEPROM device includes a floating-gate electrode upon which electrical charge is stored. In a flash EEPROM device, electrons are transferred to a floating-gate electrode through a dielectric layer overlying the channel region of the transistor. The electron transfer is initiated by either hot electron injection or Fowler-Nordheim tunneling. One important dielectric material for the fabrication of the floating-gate electrode is an ONO structure. During programming, electrical charges are transferred from the substrate to the silicon nitride layer in the ONO structure and trapped therein. Nowadays, the ONO structure is in wide use in non-volatile memory devices.
  • The ONO formation described in U.S. Pat. No. 5,168,334 is shown in FIG. 1, which is most commonly used. A bottom oxide layer 102 is thermally grown over the surface of a silicon substrate 101, and then an overlying layer 103 of silicon nitride is deposited to a thickness of around 200 angstroms. Next, a top oxide layer 104 is deposited on the silicon nitride layer 103, thereby an ONO layer 10 is formed.
  • U.S. Pat. Nos. 5,966,603 and 6,297,096 reveal another way of ONO formation. As shown in FIG. 2(a), a bottom oxide layer 202 is thermally grown on a silicon substrate 201, followed by depositing a silicon nitride layer 203. As shown in FIG. 2(b), an oxidation process is conducted to consume a part of the silicon nitride layer 203 into a top oxide layer 204, thereby an ONO layer 20 including the bottom oxide layer 202, the nitride layer 203 and the top oxide layer 204 is formed. It is noted that typically half of the thickness of the top oxide layer 204 comes from the consumed nitride layer 203. Thus, for instance, if it is desired to have a top oxide layer 204 of a thickness with around 100 angstroms, the silicon nitride layer 203 should be at least 50 angstroms thicker than the final desired nitride thickness, with the extra nitride being for consumption of the top oxide layer 204.
  • However, the top oxide layer 104 formed by deposition may incur oxide quality issue that is harmful to isolation, and the method that the top oxide layer 204 formed by oxidation may be not be able to easily control the thickness of the nitride layer 203. Therefore, it is necessary to develop other ONO formation methods for resolving the above-mentioned problems.
    • SUMMARY OF THE INVENTIION
  • The objective of the present invention is to provide a method of forming an ONO layer in a non-volatile memory device, with a view to increasing process flexibility and obtaining a thicker top oxide layer of the ONO layer for specific process requirements.
  • To achieve the above objective, an ONO formation method has been developed. First, a bottom oxide layer is formed on a silicon substrate, and then a silicon-rich nitride layer is deposited on the bottom oxide layer. Then, an oxidation process is performed to react with silicon atoms in the silicon-rich nitride layer, so as to form a top oxide layer.
  • Alternatively, the silicon-rich layer can be replaced with a combination of a nitride layer and a polysilicon layer. The oxidation process can consume the polysilicon layer into the top oxide layer, and proper oxygen is introduced into the nitride layer.
  • In addition, a first oxide layer may be formed before oxidation to be a part of the top oxide layer, thereby a thicker top oxide layer of the ONO layer can be obtained. The first oxide layer may be formed by low-pressure chemical vapor deposition (LPCVD) or use high-temperature oxide (HTO).
    • BRIEF DESCRIPTION OF THE DRAWINGS
  • FIG. 1 illustrates a known ONO formation method;
  • FIGS. 2(a) and 2(b) illustrate another known ONO formation method;
  • FIGS. 3(a) and 3(b) illustrate the first embodiment of the ONO formation method in accordance with the present invention;
  • FIGS. 4(a) and 4(b) illustrate the second embodiment of the ONO formation method in accordance with the present invention;
  • FIGS. 5(a) and 5(b) illustrate the third embodiment of the ONO formation method in accordance with the present invention;
  • FIGS. 6(a) and 6(b) illustrate the fourth embodiment of the ONO formation method in accordance with the present invention;
  • FIGS. 7(a) and 7(b) illustrate the fifth embodiment of the ONO formation method in accordance with the present invention; and
  • FIGS. 8(a) and 8(b) illustrate the sixth embodiment of the ONO formation method in accordance with the present invention.
    • DETAILED DESCRIPTION OF THE INVENTION
  • Embodiments of the present invention are now being described with reference to the accompanying drawings.
  • FIGS. 3(a) and 3(b) illustrate the first embodiment of the ONO formation method in accordance with the present invention. In FIG. 3(a), a bottom oxide layer 302 typically of 10-100 angstroms is formed on a silicon substrate 301 in which the bottom oxide layer 302 may be fabricated by oxidation in a furnace. Then, a silicon-rich nitride layer 303 typically of 10-200 angstroms is deposited on the bottom oxide layer 302. As shown in FIG. 3(b), an oxidation process at a temperature of 700-1100° C. is then conducted to introduce proper oxygen into the silicon-rich nitride layer 303, thereby a top oxide layer 304 ranging from 20 to 200 angstroms is formed by consuming extra silicon atoms in the silicon-rich nitride layer 303. Accordingly, the silicon-rich nitride layer 303 may be transformed into a thinner nitride layer 303′ of less silicon concentration. Nevertheless, the thickness of the nitride layer 303′ is not far less than that of the silicon-rich nitride layer 303 due to the high concentration of silicon atoms in the silicon-rich nitride layer 303. As a result, an ONO layer 30 including the bottom oxide layer 302, the nitride layer 303′ and the top oxide layer 304 is formed.
  • The second embodiment of the ONO formation method in accordance with the present invention is shown in FIGS. 4(a) and 4(b). In FIG. 4(a), a bottom oxide layer 402 ranging from 10 to 100 angstroms is formed on a silicon substrate 401, and then a nitride layer 403 ranging from 10 to 200 angstroms and a polysilicon layer 404 ranging from 10 to 100 angstroms are deposited in sequence. As shown in FIG. 4(b), an oxidation process at a temperature of 700-1100° C. is then conducted to consume the polysilicon layer 404 into a top oxide layer 405 ranging from 20 to 200 angstroms, and proper oxygen is introduced into the nitride layer 403 during the oxidation process. Accordingly, an ONO layer 40 including the bottom oxide layer 402, the nitride layer 403 and the top oxide layer 405 is formed.
  • The third embodiment of the ONO formation method in accordance with the present invention is shown in FIGS. 5(a) and 5(b). In FIG. 5(a), a bottom oxide layer 502 ranging from 10 to 100 angstroms is formed on a silicon substrate 501, and then a silicon-rich nitride layer 503 ranging from 10 to 200 angstroms and a first oxide layer 504 are deposited in sequence. As shown in FIG. 5(b), an oxidation process at a temperature of 700-1100° C. is then conducted to consume extra silicon atoms in the silicon-rich nitride layer 503, so as to form a second oxide layer 503′. The second oxide layer 503′ together with the first oxide layer 504 form a top oxide layer 505 ranging from 20 to 200 angstroms, and thus the top oxide layer 505 is thicker than the first oxide layer 504. The first oxide layer may be formed by LPVCD or made of HTO, i.e., thermally formed in a temperature between 500-800° C. Accordingly, an ONO layer 50 including the bottom oxide layer 502, the nitride layer 503 and the top oxide layer 505 is formed. In comparison with the above-mentioned first embodiment, the first oxide layer 504 added before oxidation is to attain a thicker top oxide layer, so as to meet specific requirements and enhance process flexibility.
  • FIGS. 6(a) and 6(b) illustrate the fourth embodiment of the ONO formation method put forth in the present invention. A bottom oxide layer 602 ranging from 10 to 100 angstroms is formed over the surface of a silicon substrate 601, and a nitride layer 603 ranging from 10 to 100 angstroms, a polysilicon layer 604 ranging from 10 to 200 angstroms and a first oxide layer 605 ranging from 10 to 100 angstroms are sequentially deposited or grown thereafter. As shown in FIG. 6(b), an oxidation process at a temperature of 700-1100° C. is then conducted to consume polysilicon layer 604 into a second oxide layer 604′. The second oxide layer 604′ together with the first oxide layer 605 forms a top oxide layer 606 ranging from 20 to 200 angstroms. As a result, an ONO layer 60 including the bottom oxide layer 602, the nitride layer 603 and the top oxide layer 606 is formed.
  • FIGS. 7(a) and 7(b) illustrate the fifth embodiment of the ONO formation method put forth in the present invention. In FIG. 7(a), a bottom oxide layer 702 ranging from 10 to 100 angstroms is formed on a silicon substrate 701, and a polysilicon layer 703 ranging from 10 to 100 angstroms and a nitride layer 704 ranging from 10 to 100 angstroms are sequentially deposited afterwards. As shown in FIG. 7(b), an oxidation process at a temperature of 700-1100° C. is implemented to consume the polysilicon layer 703 into a top oxide layer 705 that is formed on the surface of the nitride layer 704, in which the silicon atoms in the polysilicon layer 703 diffuse through the nitride layer 704 to react with the oxygen in the oxidation process, so as to form the top oxide layer 705. Therefore, the nitride layer 704 cannot be too thick to hinder the penetration of the silicon atoms, and a thickness of 20-50 angstroms or even less is preferred. As a result, an ONO layer 70 including the bottom oxide layer 702, the nitride layer 704 and the top oxide layer 705 is formed.
  • FIGS. 8(a) and 8(b) illustrate the sixth embodiment of the ONO formation method put forth in the present invention. In FIG. 8(a), a bottom oxide layer 802 ranging from 10 to 100 angstroms is formed on a silicon substrate 801, and then a polysilicon layer 803 ranging from 10 to 100 angstroms, a nitride layer 804 ranging from 10 to 100 angstroms and a first oxide layer 805 ranging from 20 to 200 angstroms are sequentially deposited. As shown in FIG. 8(b), an oxidation process is then conducted at a temperature ranging from 700-1000° C. to consume the polysilicon layer 803 into a second oxide layer 803′, in which the silicon atoms in the polysilicon layer 803 diffuse through the nitride layer 804 to react with oxygen, so as to form the second oxide layer 803′. The first and second oxide layers 805 and 803′ form a top oxide layer 806. As a result, an ONO layer 80 including the bottom oxide layer 802, the nitride layer 804 and the top oxide layer 806 is formed.
  • Similarly, the objective of adding the first oxide layers 605 and 805 is to provide the thicker top oxide layers 606 and 806, and HTO or LPCVD oxide can be selected as material thereof.
  • The above-described embodiments of the present invention are intended to be illustrative only. Numerous alternative embodiments may be devised by those skilled in the art without departing from the scope of the following claims.

Claims (20)

1. A method of forming an oxide-nitride-oxide layer in a non-volatile memory device, comprising the steps of:
providing a silicon substrate;
forming a bottom oxide layer on the silicon substrate;
depositing a silicon-rich nitride layer on the bottom oxide layer; and
performing an oxidation process to react with silicon atoms in the silicon-rich nitride layer, so as to form a top oxide layer.
2. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 1, wherein the bottom oxide layer is of a thickness between 10 and 100 angstroms.
3. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 1, wherein the silicon-rich nitride layer is of a thickness between 10 and 200 angstroms.
4. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 1, wherein the oxidation process is conducted at a temperature between 700 and 1100° C.
5. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 1, wherein the top oxide layer is of a thickness between 20 and 200 angstroms.
6. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 1, further comprising the step of depositing a first oxide layer on the silicon-rich nitride layer before the oxidation process is performed.
7. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 6, wherein the first oxide layer is a part of the top oxide layer.
8. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 6, wherein the first oxide layer is made of high-temperature oxide.
9. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 6, wherein the first oxide layer is deposited by chemical vapor deposition.
10. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 6, wherein the first oxide layer is of a thickness between 10 and 100 angstroms.
11. A method for forming an oxide-nitride-oxide layer in a non-volatile memory device, comprising the steps of:
providing a silicon substrate;
forming a bottom oxide layer on the silicon substrate;
depositing a nitride layer on the bottom oxide layer;
depositing a polysilicon layer on the nitride layer; and
performing an oxidation process to react with the polysilicon layer, so as to form a top oxide layer.
12. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 11, wherein the nitride layer is of a thickness between 10 and 200 angstroms.
13. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 11, wherein the polysilicon layer is of a thickness between 10 and 100 angstroms.
14. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 11, further comprising the step of depositing a first oxide layer on the polysilicon layer before the oxidation process is performed.
15. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 14, wherein the first oxide layer is a part of the top oxide layer.
16. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 14, wherein the first oxide layer is made of high-temperature oxide.
17. A method for forming an oxide-nitride-oxide layer in a non-volatile memory device, comprising the steps of:
providing a silicon substrate;
forming a bottom oxide layer on the silicon substrate;
depositing a polysilicon layer on the bottom oxide layer;
depositing a nitride layer on the polysilicon layer; and
performing an oxidation process, so as to form a top oxide layer.
18. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 17, further comprising the step of depositing a first oxide layer on the nitride layer before the oxidation process is performed.
19. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 18, wherein the first oxide layer is a part of the top oxide layer.
20. The method for forming an oxide-nitride-oxide layer in a non-volatile memory device of claim 17, wherein the nitride layer is of a thickness between 20 and 50 angstroms.
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