TWI627226B - 用於密封之雙側強化助焊劑 - Google Patents

用於密封之雙側強化助焊劑 Download PDF

Info

Publication number
TWI627226B
TWI627226B TW103126266A TW103126266A TWI627226B TW I627226 B TWI627226 B TW I627226B TW 103126266 A TW103126266 A TW 103126266A TW 103126266 A TW103126266 A TW 103126266A TW I627226 B TWI627226 B TW I627226B
Authority
TW
Taiwan
Prior art keywords
dsr
substrate
solder paste
material comprises
materials
Prior art date
Application number
TW103126266A
Other languages
English (en)
Other versions
TW201512294A (zh
Inventor
拉馬克席納 豪瑟 文卡達吉利艾巴
蘇塔巴 穆赫吉
哈利許 汗奇納 斯達帕
摩甘納 迪 艾維拉 里貝
修利 沙卡
巴瓦 辛基
拉霍 洛特
Original Assignee
美商阿爾發金屬化工公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美商阿爾發金屬化工公司 filed Critical 美商阿爾發金屬化工公司
Publication of TW201512294A publication Critical patent/TW201512294A/zh
Application granted granted Critical
Publication of TWI627226B publication Critical patent/TWI627226B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/29198—Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199—Material of the matrix
    • H01L2224/2929—Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73201—Location after the connecting process on the same surface
    • H01L2224/73203—Bump and layer connectors
    • H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/8101—Cleaning the bump connector, e.g. oxide removal step, desmearing
    • H01L2224/81011—Chemical cleaning, e.g. etching, flux
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81024—Applying flux to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81009—Pre-treatment of the bump connector or the bonding area
    • H01L2224/81026—Applying a precursor material to the bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818—Bonding techniques
    • H01L2224/81801—Soldering or alloying
    • H01L2224/81815—Reflow soldering
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81908—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving monitoring, e.g. feedback loop
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
    • H01L2224/83855—Hardening the adhesive by curing, i.e. thermosetting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H01L2224/921—Connecting a surface with connectors of different types
    • H01L2224/9212—Sequential connecting processes
    • H01L2224/92122—Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125—Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0133—Ternary Alloys
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954—Other details of electrical connections
    • H05K2201/10977—Encapsulated connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H05K3/284—Applying non-metallic protective coatings for encapsulating mounted components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3489—Composition of fluxes; Methods of application thereof; Other methods of activating the contact surfaces

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
  • Wire Bonding (AREA)

Abstract

本發明係關於用於半導體製造之雙側強化(DSR)材料及方法。該等DSR材料展現出習知底部填充材料之特性與在室溫下增強之穩定性。

Description

用於密封之雙側強化助焊劑
一或多個態樣大體上係關於電子工業，且更具體言之關於用於半導體封裝之材料及方法。
對於可在半導體封裝中在板及組件兩個層面用作習知底部填充材料之替代品的新穎產品之需求日益增加。總成製造商尋求替代性高度穩定之底部填充材料以在各種條件下促進電子工業中封裝材料之簡易處理。
根據一或多個態樣，提供雙側強化材料及方法。
本發明之一個態樣係有關一種在裝配製程期間將雙側強化(dual-side reinforcement，DSR)材料施加於器件上之方法。在一個實施例中，該方法包含將焊料膏材料印刷在印刷電路板基板上，用拾取和放置裝置拾取球狀柵格陣列器件，將器件浸漬於印刷助焊劑疊層封裝(package on package，PoP)機器中，以及將器件放置於基板上之焊料膏焊墊上。
該方法之態樣可進一步包括對基板施加熱以回焊器件以使器件連接至基板。該方法進一步可包含在對基板施加熱以回焊器件之後，用可固化DSR材料完全地填充器件與基板之間的間隙。該方法進一步可包含利用掃描電子顯微鏡分析器件下方之可固化DSR材料。
本發明之另一態樣係有關一種雙側強化材料，其展現出底部填充材料之特性與在室溫下增強之穩定性。在一個實施例中，該材料包含在室溫下穩定之樹脂混合物、硬化劑、催化劑及至少一種其他添加劑。
雙側強化材料之態樣進一步包括達成傳統底部填充材料之機械特性的材料，及/或達成傳統底部填充材料之跌落衝擊特性的材料。
以下更詳細地論述此等例示性態樣及實施例之其他態樣、實施例及優勢。此外，應理解前述資訊及以下【實施方式】均僅為各種態樣及實施例之說明性實例，且意欲提供用於理解所主張之態樣及實施例之性質及特徵的概述或框架。將隨附圖式包括在內以提供對各種態樣及實施例之說明及進一步理解，且其併入本說明書中且構成本說明書之一部分。該等圖式以及本說明書其餘部分用於闡明所描述及主張之態樣及實施例之原理及操作。
在圖式中，相同參考字符通常指貫穿不同視圖始終之相同零件。此外，圖式未必按比例繪製，取而代之，通常將重點放在說明所揭示之實施例之原理，且不欲作為限制該等實施例之定義。為清楚起見，並非每一組件均可標記於每張圖中。在以下描述中，參考隨附圖式描述各種實施例，其中：圖1為施加根據一或多個實施例之雙側強化(DSR)材料之方法的流程圖。
圖2為用掃描電子顯微鏡(SEM)拍攝之根據一或多個實施例之經DSR材料填充之封裝的相片。
圖3呈現一伴隨實例中論述之跌落衝擊資料。
圖4為展示根據一或多個實施例之DSR材料之黏度穩定性的圖式。
圖5及圖6呈現來自一伴隨實例中論述之熱循環測試之資料。
圖7呈現一伴隨實例中論述之跌落衝擊資料。
本文所述之各種實施例在其應用方面不限於如以下描述中所闡述或圖式中所說明之構造細節及組件配置。一或多個實施例能夠超越本文例示性呈現之該等實施例以各種方式實施或執行。
目前，習知的基於熱固性聚合物之底部填充材料廣泛用作封裝材料以增強或提高材料之機械特性。廣泛用於電子工業中密封製程之底部填充材料對溫度敏感，且若暴露於室溫則可引起如預固化之問題。此情況及暴露於空氣中又可引起底部填充材料中之黏度累積，該黏度累積會引起處理問題。因此，習知底部填充材料之使用具有某些固有缺陷，因為其需要與標準回焊製程分開之獨立固化製程且該等底部填充材料必須儲存於-4℃以下。
根據一或多個實施例，材料及方法可解決習知底部填充材料之此等缺陷。在一些實施例中，可施加本文所揭示之材料且該材料將充當傳統底部填充材料，且可用於標準回焊製程以固化材料。固化後，該材料將傾向於具有底部填充材料之特性，展現室溫穩定性，且可在無任何額外措施之情況下儲存及使用。所揭示之DSR材料為具有極佳室溫穩定性之材料。在一些非限制性實施例中，DSR材料在室溫下穩定持續至少20天。所揭示之材料在黏度方面亦為穩定的。有益的是，無需與標準回焊製程分開之獨立固化製程。
如本文所使用，回焊通常可指其中在印刷電路板表面上印刷或分配焊料膏或放置預製焊料或兩種操作均實施，在經沈積之焊料內部或附近放置組件，且將總成加熱至足以回焊焊料之溫度的製程。
根據一或多個實施例，雙側強化(DSR)材料可展現習知底部填充材料之特性，但在室溫下具有增強之穩定性。在至少一些實施例中， DSR材料包括在室溫下通常均穩定的樹脂混合物、硬化劑、催化劑及至少一種其他添加劑。
根據一或多個實施例，揭示施加DSR材料之方法。為了施加DSR材料，一種方法包括將焊料膏材料印刷在印刷電路板基板上，用拾取和放置裝置拾取球狀柵格陣列器件，將器件浸漬於印刷助焊劑疊層封裝(PoP)機器中，以及將器件放置於基板上之焊料膏焊墊上。
如本文所使用的術語「雙側強化材料」或「DSR材料」可指一類含助焊劑之可固化組合物。該組合物可包括樹脂、硬化劑及催化劑及任何其他所需添加劑中之一或多者。其中可存在或可不存在助焊劑。在至少一些實施例中，不存在助焊劑。當DSR材料受熱(諸如經由回焊製程)時，該材料可經歷三維交聯反應以在焊接點以及BGA焊球與基板之間的任何間隙的周圍形成堅硬固體塊，藉此充當底部填充材料。
根據一或多個非限制性實施例，DSR材料可包括在所指明之重量百分比下的以下成分中之一或多者：
a)具有高沸點之有機溶劑 30重量%-40重量%
b)不同官能度之環氧樹脂 5重量%-10重量%
c)具有高分子量及雙官能之固體環氧樹脂 15重量%-30重量%
d)作為活化劑之二羧酸 3重量%-10重量%
e)作為催化劑之經取代芳胺 2重量%-8重量%
f)作為催化劑之膦基鹽 1重量%-5重量%
g)液體酸酐型硬化劑/催化劑 1重量%-5重量%
h)液體型應力調節劑 0.1重量%-4重量%
i)助黏劑 0.1重量%-3重量%
j)強化填料 20重量%-50重量%
根據一或多個實施例，材料之穩定性及所要黏度可歸因於該類 環氧樹脂與硬化劑之間的比率。所用催化劑在室溫下通常應呈低反應性且應僅在高溫(處理溫度)下發生交聯反應。交聯較佳應在焊料熔融後開始。若環氧樹脂在焊料熔融前即經歷交聯，則經交聯之環氧樹脂可變硬且硬化之環氧樹脂可能不允許熔融之焊料在電子電路板上形成適合接點。根據一或多個實施例，環氧樹脂與硬化劑之組合可在焊料熔融之後在高溫下引發交聯反應。經硬化/交聯之環氧樹脂可在焊接點周圍形成套環且可減少焊接點上外加應力之轉移。
在至少一些實施例中，可以所要比率混合該等組分且使其經歷研磨，諸如三輥研磨。確認例如FOG<10微米後，可停止研磨製程。經研磨之樣品接著可與所要量之強化填料混合以獲得最終DSR產品。
根據一或多個非限制性實施例，DSR材料之黏度可在約100Pa.S至500Pa.S範圍內。可利用DSC量測DSR材料之量熱特性以確定峰值固化溫度，該溫度通常應高於焊料熔點。可利用熱機械分析儀(Thermo Mechanical Analyzer，TMA)量測DSR材料之玻璃轉移溫度(Tg)及熱膨脹係數(CTE)，且可藉由動態機械分析(Dynamic mechanical Analysis，DMA)量測該材料之儲存模數。
根據一些實施例，提供可利用PoP機器簡易應用的施加DSR材料之方法。DSR材料可具有意欲充當底部填充材料之非助焊特性。利用PoP施加DSR材料(有時稱為「助焊劑」)後，DSR材料可在標準SMT回焊中經歷交聯。
圖1說明施加DSR材料之方法之一例示性實施例。如所示，該方法可涉及將焊料膏材料印刷在印刷電路板基板上，用拾取和放置裝置拾取球狀柵格陣列器件，將器件浸漬於印刷助焊劑疊層封裝(PoP)機器中，以及將器件放置於基板上之焊料膏焊墊上。在回焊製程之後，可用可固化DSR材料完全地填充組件與板之間的間隙。
根據一或多個實施例，可控制該方法之各種製程參數。此等參 數可包括例如所浸漬組件之浸漬時間、浸漬高度及上升速度。浸漬時間可為至關重要的，因為其決定BGA中各焊球上之助焊劑轉移量。各焊球上之助焊劑轉移量可影響經裝配之封裝的最終機械可靠性特性。較長浸漬時間可使得該封裝之機械特性較高。較小封裝與較大封裝之浸漬時間通常可有所不同。在一些非限制性實施例中，推薦浸漬時間為約0.1秒至約5秒。浸漬高度亦可有助於達成最終封裝之較高機械強度。在一些非限制性實施例中，浸漬高度可視封裝及對指定封裝之最終機械可靠性要求而定自約50%至約90%變化。在一些特定實施例中，推薦BGA封裝之焊球高度的約90%作為浸漬高度。通常認為上升速度為設備將組件自DSR材料之助焊劑焊盤提起之速度。應在處理之前針對不同類型之封裝將上升速度最佳化。
根據一或多個實施例，DSR材料具有習知底部填充材料之特性，但在室溫下具有極佳穩定性。傳統底部填充材料在室溫下不穩定且其黏度受影響，此在處理時對其流動能力及固化能力有不利影響。本發明揭示之DSR材料在室溫下為穩定的且將傾向於提供底部填充材料之所有有益的機械特性。
本文所述之方法及組合物可用於包括(但不限於)印刷電路板製造、LED裝配、光伏打電池製造、半導體製造及晶粒黏著之應用。
自以下實例將更充分地理解本文所揭示之材料及方法之此等及其他實施例之功能及優勢。以下實例意欲說明所揭示之材料及方法之益處，但未例示其全部範圍。
實例1
如圖2所示，利用掃描電子顯微鏡(SEM)分析位於組件下方之可固化DSR材料。自SEM影像明顯看出板與BGA組件之間的間隙完全經可固化DSR材料填充且沒有空隙。此無空隙、完全填充之DSR材料有助於增強板上組件之機械可靠性。
實例2
如圖3所示，比較DSR材料與標準底部填充材料stay Chip 3082之跌落衝擊特性。
圖3之魏普圖(weibull plot)顯示標準SMT焊料膏、帶有底部填充材料Staychip 3082之標準SMT焊料膏及帶有DSR材料(NHHV4+40% Si)之標準SMT焊料膏的跌落衝擊資料。經比較，顯然帶有底部填充材料之焊料膏的跌落衝擊特性遠高於標準焊料膏。
另外，亦確認DSR材料等效於經底部填充且經回焊之板。自此跌落衝擊資料充分確認DSR材料之表現類似於底部填充材料。
實例3
藉由使用Malcolm黏度計來測定DSR材料之穩定性且在規定時間間隔下量測DSR材料之黏度。圖4顯示來自Malcolm黏度計之黏度資料。DSR材料顯示極佳之穩定性。
實例4
熱循環測試根據IPC 9701-A標準進行(0℃(10分鐘)至+125℃(10分鐘)持續1000次循環)。為了失效分析，在1000次循環之後，進行BGA之橫截面及顯微觀察。將失效定義為在最多5次連續讀取掃描內標稱電阻增加20%。資料呈現於附圖5中。如所說明，任何焊料膏之電阻未增加超過20%。圖6呈現熱循環之後的橫截面。
SH2及NHHV4-S均通過自0℃至+125℃之1000次熱循環(停留時間為10分鐘)。對於SH2及NHHV4-S而言，直至1000次熱循環，未在焊球及助焊劑材料上觀察到裂痕。對於Sn3Ag0.5Cu CVP390焊料膏而言，在未添加SH2或NHHV4-S之情況下，750次循環之後即出現裂痕。因此，SH2及NHHV4-S為焊接點提供對抗熱循環測試期間之週期性脹縮(由CTE失配引起)的額外抵抗力。
實例5
使用操作條件B(1500Gs，0.5毫秒脈衝，半正弦曲線)根據JEDEC標準JESD22-B111「Board Level Drop Test Method of Components for Handheld Electronic Products」比較所揭示之DSR材料與習知焊料膏之跌落衝擊特性。將失效偵測定義為在5次連續跌落期間第一次間歇不連續事件之後有3次附加此類事件。
資料呈現於圖7中。NHHV4-S及SH2跌落衝擊特徵生命值分別比僅用習知焊料膏高約2倍及3倍。SH5-F跌落衝擊特徵生命值比僅用習知焊料膏幾乎高6倍。
應理解本文所論述之組合物及方法之實施例在應用方面不限於本文所闡述之構造細節及配置。該等組合物及方法能夠實施於其他實施例且能夠以各種方式實踐或執行。本文所提供之特定實施例之實例僅用於說明性目的且不欲為限制性的。詳言之，與任何一或多個實施例結合論述之作用、要素及特徵不欲自任何其他實施例之類似作用中排除。
此外，本文所使用之成語及術語係用於描述之目的且不應視為限制性的。本文所使用之「包括」、「包含」、「具有」、「含有」、「涉及」及其變化形式意在涵蓋列在其後之項目及其等效物以及其他項目。
上文已描述至少一個實施例之若干態樣，應理解各種改變、修改及改良對熟習此項技術者而言為易於想到的。該等改變、修改及改良意欲成為本發明之一部分且意欲處在本發明之範疇內。因此，先前之描述及圖式僅以實例方式出現。

Claims (9)

  1. 一種在裝配製程期間將雙側強化(DSR)材料施加於裝置上之方法，該方法包含：將焊料膏材料印刷在印刷電路板基板上；用拾取和放置裝置拾取球狀柵格陣列器件；將該器件浸漬於印刷助焊劑疊層封裝(PoP)機器中；將該器件放置於該基板上之焊料膏焊墊上；對該基板施加熱以回焊該器件以使該器件連接至該基板；以及用可固化DSR材料填充該器件與該基板之間的間隙；其中該DSR材料包括環氧樹脂及硬化劑；且其中該環氧樹脂及硬化劑之組合僅在該焊料膏材料熔融之後在高溫下引發交聯反應。
  2. 如請求項1之方法，其進一步包含利用掃描電子顯微鏡分析該器件下方之該可固化DSR材料。
  3. 如請求項1之方法，其中浸漬時間為0.1秒至5秒。
  4. 如請求項1之方法，其中浸漬高度為50%至90%。
  5. 如請求項1之方法，其中該DSR材料包括二羧酸。
  6. 如請求項1之方法，其中該DSR材料包括經取代芳胺。
  7. 如請求項1之方法，其中該DSR材料包括膦基鹽。
  8. 如請求項1之方法，其中該DSR材料包括液體酸酐型硬化劑。
  9. 如請求項1之方法，其中該DSR材料具有100至500Pa.S範圍內之黏度。
TW103126266A 2013-08-02 2014-07-31 用於密封之雙側強化助焊劑 TWI627226B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IN3497/CHE/2013 2013-08-02
IN3497CH2013 2013-08-02

Publications (2)

Publication Number Publication Date
TW201512294A TW201512294A (zh) 2015-04-01
TWI627226B true TWI627226B (zh) 2018-06-21

Family

ID=52432416

Family Applications (1)

Application Number Title Priority Date Filing Date
TW103126266A TWI627226B (zh) 2013-08-02 2014-07-31 用於密封之雙側強化助焊劑

Country Status (7)

Country Link
US (1) US9786629B2 (zh)
JP (1) JP6573882B2 (zh)
KR (2) KR102338917B1 (zh)
CN (1) CN105453240B (zh)
DE (1) DE112014003568T5 (zh)
TW (1) TWI627226B (zh)
WO (1) WO2015017615A1 (zh)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110763699B (zh) * 2019-10-12 2022-12-20 广州兴森快捷电路科技有限公司 线路板的内层互连缺陷的分析方法及线路板

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1795550A (zh) * 2003-05-23 2006-06-28 国家淀粉及化学投资控股公司 预先施用的底层填料密封剂的应用方法
TW200949964A (en) * 2008-03-19 2009-12-01 Henkel Corp Method of fabricating a semiconductor package or circuit assembly using a fluxing underfill composition applied to solder contact points in a dip process

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6780682B2 (en) * 2001-02-27 2004-08-24 Chippac, Inc. Process for precise encapsulation of flip chip interconnects
US7331502B2 (en) * 2001-03-19 2008-02-19 Sumitomo Bakelite Company, Ltd. Method of manufacturing electronic part and electronic part obtained by the method
JP3608536B2 (ja) * 2001-08-08 2005-01-12 松下電器産業株式会社 電子部品実装方法
US6833629B2 (en) * 2001-12-14 2004-12-21 National Starch And Chemical Investment Holding Corporation Dual cure B-stageable underfill for wafer level
US7037399B2 (en) * 2002-03-01 2006-05-02 National Starch And Chemical Investment Holding Corporation Underfill encapsulant for wafer packaging and method for its application
US7279223B2 (en) * 2003-12-16 2007-10-09 General Electric Company Underfill composition and packaged solid state device
US20090075429A1 (en) * 2005-04-27 2009-03-19 Lintec Corporation Sheet-Like Underfill Material and Semiconductor Device Manufacturing Method
US7169641B2 (en) * 2005-05-03 2007-01-30 Stats Chippac Ltd. Semiconductor package with selective underfill and fabrication method therfor
JP4757070B2 (ja) * 2006-03-27 2011-08-24 富士通株式会社 半田付け用フラックス及び半導体素子の接合方法
KR20100132480A (ko) * 2007-07-23 2010-12-17 헨켈 리미티드 땜납 플럭스
US8008419B2 (en) * 2008-08-13 2011-08-30 Designer Molecules, Inc. Siloxane monomers and methods for use thereof
KR20110092553A (ko) * 2010-02-09 2011-08-18 삼성전자주식회사 자기조립된 절연 박막을 포함하는 반도체 패키지 모듈 및 그 제조 방법
JP5278385B2 (ja) * 2010-06-22 2013-09-04 信越化学工業株式会社 実装用封止材及びそれを用いて封止した半導体装置
KR20130124070A (ko) * 2012-05-04 2013-11-13 삼성전자주식회사 플립칩 패키지 제조 장치 및 이를 이용한 플립칩 패키지 제조 방법

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1795550A (zh) * 2003-05-23 2006-06-28 国家淀粉及化学投资控股公司 预先施用的底层填料密封剂的应用方法
TW200949964A (en) * 2008-03-19 2009-12-01 Henkel Corp Method of fabricating a semiconductor package or circuit assembly using a fluxing underfill composition applied to solder contact points in a dip process

Also Published As

Publication number Publication date
KR20220009982A (ko) 2022-01-25
KR102338917B1 (ko) 2021-12-13
KR20160039617A (ko) 2016-04-11
JP2016535451A (ja) 2016-11-10
DE112014003568T5 (de) 2016-04-14
JP6573882B2 (ja) 2019-09-11
US20160163672A1 (en) 2016-06-09
US9786629B2 (en) 2017-10-10
CN105453240B (zh) 2018-05-01
TW201512294A (zh) 2015-04-01
CN105453240A (zh) 2016-03-30
WO2015017615A1 (en) 2015-02-05

Similar Documents

Publication Publication Date Title
JP4299140B2 (ja) ウエハレベル用の二重硬化ｂ−ステージ化可能なアンダーフィル
US6367150B1 (en) Solder flux compatible with flip-chip underfill material
TWI552237B (zh) A semiconductor wafer bonding method, a semiconductor wafer bonding method, a semiconductor device manufacturing method, and a semiconductor device
JP4887850B2 (ja) アンダーフィル用液状樹脂組成物、並びにそれを用いた半導体装置の製造方法及び半導体装置
JP6800140B2 (ja) フリップチップ実装体の製造方法、フリップチップ実装体、および先供給型アンダーフィル用樹脂組成物
WO2004059721A1 (ja) 電子部品装置
US8075721B2 (en) Low exothermic thermosetting resin compositions useful as underfill sealants and having reworkability
DE60217095T2 (de) Einkomponentige heisshärtende epoxidharzzusammensetzung und halbleitermontage-unterfüllungsmaterial
TWI627226B (zh) 用於密封之雙側強化助焊劑
CA2364933A1 (en) Novel high temperature underfilling material with low exotherm during use
JP4366971B2 (ja) 液状封止樹脂組成物の設計方法、および半導体装置の製造方法
JP2005206664A (ja) 半導体封止用樹脂組成物
JP4119356B2 (ja) 半導体装置の製造方法及び半導体装置
JP2006143795A (ja) 液状樹脂組成物、それを用いた半導体装置の製造方法及び半導体装置
JP2003105054A (ja) 液状封止樹脂組成物及び半導体装置
Zhang et al. Development of environmentally friendly nonanhydride no-flow underfills
JP7436240B2 (ja) アンダーフィル材、及びこれを用いた半導体装置の製造方法
JP2004090021A (ja) 硬化性フラックス
JP2001055432A (ja) 半導体装置封止用樹脂組成物及びこれを用いた半導体装置、並びに半導体装置製造方法及び製造装置
JP2005251880A (ja) 半導体装置の製造方法及び半導体装置
JP2002261202A (ja) 液状封止樹脂組成物及び半導体装置
JP4569116B2 (ja) 液状封止樹脂組成物及びそれを用いた半導体装置の製造方法
Capote et al. Reflow-curable polymer fluxes for flip chip encapsulation
JP2008251836A (ja) 半導体装置
JP2008305898A (ja) 電子部品の封止構造

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees