TWI624732B - 半導體裝置用基板之製造方法 - Google Patents

半導體裝置用基板之製造方法 Download PDF

Info

Publication number
TWI624732B
TWI624732B TW106112708A TW106112708A TWI624732B TW I624732 B TWI624732 B TW I624732B TW 106112708 A TW106112708 A TW 106112708A TW 106112708 A TW106112708 A TW 106112708A TW I624732 B TWI624732 B TW I624732B
Authority
TW
Taiwan
Prior art keywords
film
substrate
pattern
organic
photoresist
Prior art date
Application number
TW106112708A
Other languages
English (en)
Other versions
TW201738662A (zh
Inventor
荻原勤
菊地里枝
Original Assignee
信越化學工業股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 信越化學工業股份有限公司 filed Critical 信越化學工業股份有限公司
Publication of TW201738662A publication Critical patent/TW201738662A/zh
Application granted granted Critical
Publication of TWI624732B publication Critical patent/TWI624732B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/075—Silicon-containing compounds
    • G03F7/0752—Silicon-containing compounds in non photosensitive layers or as additives, e.g. for dry lithography
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/091—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers characterised by antireflection means or light filtering or absorbing means, e.g. anti-halation, contrast enhancement
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/094—Multilayer resist systems, e.g. planarising layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/004—Photosensitive materials
    • G03F7/09—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers
    • G03F7/11—Photosensitive materials characterised by structural details, e.g. supports, auxiliary layers having cover layers or intermediate layers, e.g. subbing layers
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/162—Coating on a rotating support, e.g. using a whirler or a spinner
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/16—Coating processes; Apparatus therefor
    • G03F7/168—Finishing the coated layer, e.g. drying, baking, soaking
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/20—Exposure; Apparatus therefor
    • G03F7/2037—Exposure with X-ray radiation or corpuscular radiation, through a mask with a pattern opaque to that radiation
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/32—Liquid compositions therefor, e.g. developers
    • G03F7/325—Non-aqueous compositions
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/30—Imagewise removal using liquid means
    • G03F7/32—Liquid compositions therefor, e.g. developers
    • G03F7/325—Non-aqueous compositions
    • G03F7/327—Non-aqueous alkaline compositions, e.g. anhydrous quaternary ammonium salts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H01L21/02288—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating printing, e.g. ink-jet printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02296—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer
    • H01L21/02318—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment
    • H01L21/02345—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light
    • H01L21/02348—Forming insulating materials on a substrate characterised by the treatment performed before or after the formation of the layer post-treatment treatment by exposure to radiation, e.g. visible light treatment by exposure to UV light
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H01L21/0276—Photolithographic processes using an anti-reflective coating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0332—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065—Plasma etching; Reactive-ion etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/31058—After-treatment of organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Architecture (AREA)
  • Structural Engineering (AREA)
  • Inorganic Chemistry (AREA)
  • General Chemical & Material Sciences (AREA)
  • Plasma & Fusion (AREA)
  • Materials For Photolithography (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

本發明之目的係提供可在半導體裝置等之製造步驟中，將基板上之凹凸圖案予以填埋，並以低成本將基板予以高度地平坦化之有機膜之形成方法。該有機膜之形成方法係藉由在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理而形成有機膜之方法，其特徵為：形成該塗佈膜後，在該不溶化處理之前或與該不溶化處理同時，實施對該基板施加振動之處理。

Description

半導體裝置用基板之製造方法
本發明關於可在半導體裝置等之微細加工步驟使用之極為平坦的有機膜之形成方法及使用了該有機膜之形成方法之半導體裝置用基板之製造方法。
微影技術中的光源之短波長化所致之圖案尺寸的微型化引領著半導體裝置之處理性能的高性能化。但是，ArF光源之後的短波長化之速度減緩，替代微型化之高性能化則變得有其必要。於是，正在進行藉由將半導體裝置之結構三維化且更高密度地配置電晶體可將半導體裝置高性能化之技術的開發。具有如此的三維化結構之半導體裝置之基板比起迄今為止的基板，就電路圖案而言，由於形成更深且更細的結構，故迄今為止對平面性之結構形成已最適化的微影技術無法保有具實用性之製程允差。於是，必須藉由使用可將形成有三維結構之基板平坦化之材料來形成平坦面後，在該平坦面上以微影技術進行圖案化來確保製程允差。
作為可形成如此的平坦面之技術已知有許多利用旋轉塗佈型之有機膜所為之平坦化膜之形成技術(專利文獻1-5)，但以如此的材料形成的有機膜並不代表可對應全部的半導體裝置製造用基板之圖案。此外也有人提出聚醚多元醇、聚縮醛等之液狀添加劑之添加等(專利文獻6-7)，通常如此的添加物其乾蝕刻耐性不佳，故該添加物殘留在塗佈膜中的話，可能會有基板加工時之乾蝕刻耐性不足，且作為基板加工用之有機膜時之乾蝕刻耐性不足的情形。又，作為平坦化的一種方法，將基板上的凹凸填埋後，以化學機械研磨(CMP)製程進行平坦化之方法(專利文獻8)也已實用，惟CMP係高成本製程。在如此的狀況下，尋求使用有機膜並以低成本將半導體裝置製造用基板高度地平坦化之方法。 [先前技術文獻] [專利文獻]
[專利文獻1]日本特開2005-292528號公報 [專利文獻2]日本特開2008-65081號公報 [專利文獻3]日本特開2008-242492號公報 [專利文獻4]日本特開2014-24831號公報 [專利文獻5]日本特開2014-219559號公報 [專利文獻6]國際公開第WO2008/026468號小冊 [專利文獻7]日本特開2013-253227號公報 [專利文獻8]日本特開2004-335873號公報
[發明所欲解決之課題] 本發明乃鑑於上述情事而成，其目的為提供可在半導體裝置等之製造步驟中，將基板上之凹凸圖案予以填埋，並以低成本將基板予以高度地平坦化之有機膜之形成方法。 [解決課題之手段]
為了達成上述目的，本發明係提供一種有機膜之形成方法，其係藉由在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理而形成有機膜之方法，其特徵為：形成前述塗佈膜後，在前述不溶化處理之前或與前述不溶化處理同時，實施對前述基板施加振動之處理。
若為如此的方法，在半導體裝置等之製造步驟中，可形成將基板上的凹凸之圖案予以填埋，並以低成本將基板予以高度地平坦化之有機膜。
又，前述施加振動之處理中宜施加頻率為0.01Hz至10GHz之振動。
藉由實施施加如此的頻率之振動之處理，能有效率地使塗佈膜流動，並可形成表面積最少的狀態，亦即可形成極為平坦的有機膜。
又，前述不溶化處理宜為50℃以上500℃以下之熱處理、波長為400nm以下之紫外線照射處理、及電子束照射處理中之任一者、或它們的組合。
藉由以如此的方法實施不溶化處理，可形成保持在平坦狀態之有機膜。
又，宜使用包含含有芳香環之樹脂者作為前述有機膜形成用組成物。
在本發明之有機膜之形成方法，例如可適當地使用包含含有芳香環之樹脂之有機膜形成用組成物。
又，本發明係提供一種半導體裝置用基板之製造方法，其係以上述方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上使用含有矽之光阻下層膜形成用組成物來形成含矽之光阻下層膜，在該含矽之光阻下層膜上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到前述含矽之光阻下層膜，將轉印有該圖案之含矽之光阻下層膜作為遮罩並以乾蝕刻將圖案轉印到前述有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
又，本發明係提供一種半導體裝置用基板之製造方法，其係以上述方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上使用含有矽之光阻下層膜形成用組成物來形成含矽之光阻下層膜，在該含矽之光阻下層膜上形成有機抗反射膜，在該有機抗反射膜上使用光阻組成物來形成光阻上層膜而製成4層光阻膜，在前述光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到前述有機抗反射膜與前述含矽之光阻下層膜，將轉印有該圖案之有機抗反射膜與含矽之光阻下層膜作為遮罩並以乾蝕刻將圖案轉印到前述有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
又，本發明係提供一種半導體裝置用基板之製造方法，其係以上述方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上形成選自於氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、及氮化鈦膜之無機硬遮罩，在該無機硬遮罩上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到前述無機硬遮罩，將轉印有該圖案之無機硬遮罩作為遮罩並以乾蝕刻將圖案轉印到有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
又，本發明係提供一種半導體裝置用基板之製造方法，其係以上述方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上形成選自於氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、及氮化鈦膜之無機硬遮罩，在該無機硬遮罩上形成由有機膜與含矽之光阻下層膜構成的多層光阻膜或有機抗反射膜，在該多層光阻膜或有機抗反射膜上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻經由朝前述多層光阻膜或前述有機抗反射膜之圖案轉印而將前述圖案轉印到前述無機硬遮罩，將轉印有該圖案之無機硬遮罩作為遮罩並以乾蝕刻將圖案轉印到已形成於前述基板上之有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
如上所述，以本發明之方法所形成的有機膜具有優良的平坦化特性，故藉由將此有機膜和例如在2層光阻製程、在使用有含矽之光阻下層膜之3層光阻製程、或在使用有含矽之光阻下層膜及有機抗反射膜之4層光阻製程等多層光阻製程中的各種膜材料組合使用，可將上層光阻(光阻上層膜)之圖案高精度地轉印至基板，並在基板上形成圖案。亦即，若為本發明之半導體裝置用基板之製造方法即可製造高精度的半導體裝置用基板。
此時，宜利用化學氣相沉積(CVD)法或原子層堆積(ALD)法來實施前述無機硬遮罩之形成。
在本發明之半導體裝置用基板之製造方法中，例如可用如此的方法來形成無機硬遮罩。
又，宜在前述電路圖案之形成中，利用波長為10nm以上300nm以下之高能射線所為之微影、電子束所為之直接描繪、及奈米壓印中之任一者、或它們的組合來形成電路圖案。
又，宜在前述電路圖案之形成中，以鹼顯影或有機溶劑所為之顯影來顯影電路圖案。
在本發明之半導體裝置用基板之製造方法中，可適當地使用如此的電路圖案之形成方法及顯影方法。
又，前述基板宜含有金屬膜、金屬碳化物膜、金屬氧化物膜、金屬氮化物膜、或金屬氧氮化物膜。
又，構成前述基板之金屬宜為矽、鈦、鎢、鉿、鋯、鉻、鍺、銅、鋁、銦、鎵、砷、鈀、鐵、鉭、銥、鉬、或它們的合金。
若為本發明之半導體裝置用基板之製造方法，則可將如上所述之基板經由加工而製造半導體裝置用基板。 [發明之效果]
如以上說明，若為本發明則可填埋基板上的凹凸圖案，並形成能將基板高度地平坦化之有機膜。又，由於即使不使用高成本製程之CMP仍可將基板高度地平坦化，故可用低成本實施基板之平坦化。又，由於以本發明之方法所形成的有機膜具有優良的平坦化特性，故在半導體裝置製造上極為有效。藉由將此有機膜和例如在2層光阻製程、在使用有含矽之光阻下層膜之3層光阻製程或在使用有含矽之光阻下層膜及有機抗反射膜之4層光阻製程等多層光阻製程中的各種膜材料組合使用，可將上層光阻(光阻上層膜)之圖案高精度地轉印至基板，並在基板上形成圖案。亦即，若為本發明之半導體裝置用基板之製造方法，可製造高精度的半導體裝置用基板。
如上所述，一直以來尋求在半導體裝置等之製造步驟中，可填埋基板上之凹凸圖案並以低成本將基板高度地平坦化之有機膜之形成方法之開發。
以往，例如作為將一部分或全部形成有半導體電路之基板等之具有凹凸圖案之基板平坦化的方法，係將有機膜形成用組成物旋轉塗佈於基板上，然後藉由煅燒以有機膜來填埋基板表面之凹凸圖案而形成平坦的表面。但是，此方法雖能填補表面的微小凹凸，惟難以在基板表面整體中需要進行填補之圖案密度高處與圖案密度低處之間均勻地形成平坦的表面。一般而言，經塗佈之組成物會以隨附於基板上所形成的凹凸圖案之形狀來形成具有凹凸之塗佈膜。通常，在形成半導體電路之製程中，會將如此的塗佈膜進行不溶化處理再往形成下一層膜之步驟前進。本發明人們針對基板之平坦化反覆深入探討後之結果發現：藉由塗佈有機膜形成用組成物後，在不溶化處理之前或與不溶化處理同時，對塗佈膜施加振動能量來使塗佈膜流動，可形成表面積最少的狀態，亦即極為平坦之有機膜，乃至完成本發明。
亦即，本發明係藉由在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理而形成有機膜之方法，其係在形成前述塗佈膜後，並在前述不溶化處理之前或與前述不溶化處理同時，實施對前述基板施加振動之處理之有機膜之形成方法。
以下，針對本發明詳細地說明，但本發明並不限於此。
＜有機膜之形成方法＞ 以下邊參照圖式邊說明本發明。 圖1係以本發明之有機膜之形成方法在具有間距圖案(space pattern)之基板上形成有機膜之一例之流程圖。在圖1之方法，首先將有機膜形成用組成物旋轉塗佈(旋塗)於基板1上，並形成塗佈膜2。此時，受到基板1上之凹凸圖案的影響而會以隨附於基板形狀的形狀來形成具有凹凸之塗佈膜2(圖1(A))。此塗佈膜2係由旋轉塗佈時無法揮發而殘留的溶劑與樹脂等構成。對於此已形成塗佈膜之基板實施施加振動之處理。藉由使基板1振動而對此塗佈膜2施加振動的話，會發生塗佈膜2之液狀化，塗佈膜2(主要為塗佈膜2中之樹脂)會流動(圖1(B))。就結果而言，凹凸被消除並形成平坦的塗佈膜2(圖1(C))。最後可利用熱、光、或兩者之處理將此平坦的塗佈膜2予以不溶化並形成平坦的有機膜3(圖1(D))。而且，可在此經不溶化而得的有機膜3上旋轉塗佈例如後述之含矽之光阻下層膜形成用組成物等之塗佈膜形成用組成物來形成塗佈膜。另外，在圖1的方法中，係於形成塗佈膜2後，並於塗佈膜2之不溶化處理前，實施對基板1施加振動之處理，但對基板1施加振動之處理亦可在塗佈膜2之形成後，而與不溶化處理同時實施。
圖2係以本發明之有機膜之形成方法在具有線圖案(line pattern)之基板上之廣範圍地具有微細圖案的部分形成有機膜之一例之流程圖。首先，圖2的方法係先在基板1上旋轉塗佈有機膜形成用組成物並形成塗佈膜2。此時，若圖案之節距(pitch)大的情況，會如圖1所示，受到基板上之凹凸圖案的影響而以隨附於基板形狀之形狀來形成具有凹凸之塗佈膜2，但在微細圖案，例如半節距(half pitch)比200nm更微細之圖案中，並不會隨附於個別之圖案，而是平均地形成圖案之中心部為凹形狀之(整體具有圖案之部分為平緩的凹形狀)塗佈膜2(圖2(A))。對於此已形成塗佈膜之基板實施施加振動之處理。與上述同樣地藉由使基板1振動而對塗佈膜2施加振動的話，凹凸會被消除並形成平坦的塗佈膜2(圖2(B)、圖2(C))。最後可利用熱、光、或兩者之處理將此平坦的塗佈膜2予以不溶化而形成平坦的有機膜3(圖2(D))。而且，可在此經不溶化而得的有機膜3上旋轉塗佈例如後述之含矽之光阻下層膜形成用組成物等之塗佈膜形成用組成物來形成塗佈膜。另外，在圖2的方法中，係於形成塗佈膜2後，於塗佈膜2之不溶化處理前，實施對基板1施加振動之處理，但對基板1施加振動之處理亦可在塗佈膜2之形成後，而與不溶化處理同時實施。
以下，針對本發明之有機膜之形成方法之各步驟進行更詳細的說明。
[塗佈膜之形成] 在本發明之有機膜之形成方法中，首先會在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜。就具有凹凸圖案之基板而言並無特別限制，例如可使用具有間距圖案(space pattern)、線圖案(line pattern)之基板等。又，本發明所使用的有機膜形成用組成物並無特別限制，宜使用包含含有芳香環之樹脂之有機膜形成用組成物。另外，旋轉塗佈並無特別限制，使用旋塗機等並以公知的方法實施即可。
[對基板施加振動之處理] 在本發明之有機膜之形成方法中，會在形成塗佈膜後，在前述不溶化處理之前或與前述不溶化處理同時，實施對前述基板施加振動之處理。圖3係顯示施加振動之處理之一例之說明圖。作為對基板施加振動之方法，例如可例示在基板上形成塗佈膜後，使振動發生裝置5之振動面6與塗佈膜形成後之基板4密合，並以空壓、電力驅動而令塗佈膜形成後之基板4振動之方法。例如可藉由利用超音波振盪器所產生之超音波經由振子(vibrator)傳播到基板之方法。
又，在施加振動之處理中，宜施加頻率為0.01Hz至10GHz之振動。藉由實施施加如此的頻率之振動之處理，能有效率地使塗佈膜流動，可形成表面積最少的狀態，亦即極為平坦的有機膜。
[不溶化處理] 在本發明之有機膜之形成方法中，係於形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理。不溶化處理宜為50℃以上500℃以下之熱處理、波長為400nm以下(10~400nm)之紫外線照射處理、及電子束照射處理中之任一者、或它們的組合。藉由以如此的方法實施不溶化處理，可形成保持在平坦狀態之有機膜。
經過如上所述之步驟，可在具有凹凸圖案之基板上形成經不溶化而得的有機膜。在此，該有機膜之厚度係因應圖案之深度而適當地選擇，宜設定為10~20,000nm，設定為20~15,000nm特佳。
將以此方式形成之有機膜使用於多層光阻製程時，可在其上形成含有矽之光阻下層膜、不含矽之光阻上層膜(單層光阻膜)、氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜或氮化鈦膜等之無機硬遮罩。又，由於即使不使用高成本製程之CMP仍可將基板高度地平坦化，故可用低成本實施基板之平坦化。
＜半導體裝置用基板之製造方法＞ 本發明提供一種半導體裝置用基板之製造方法，其係以上述之本發明之有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上使用含有矽之光阻下層膜形成用組成物來形成含矽之光阻下層膜，在該含矽之光阻下層膜上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到前述含矽之光阻下層膜，將轉印有該圖案之含矽之光阻下層膜作為遮罩並以乾蝕刻將圖案轉印到前述有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
本發明之半導體裝置用基板之製造方法所使用的基板宜含有金屬膜、金屬碳化物膜、金屬氧化物膜、金屬氮化物膜、或金屬氧氮化物膜。
又，構成基板之金屬宜為矽、鈦、鎢、鉿、鋯、鉻、鍺、銅、鋁、銦、鎵、砷、鈀、鐵、鉭、銥、鉬、或它們的合金。
在上述半導體裝置用基板之製造方法中，上述有機膜亦可作為犧牲膜(sacrificial film)來使用。
作為有機膜形成用組成物，宜使用如上所述之包含含有芳香環之樹脂之組成物。用在193nm曝光時，使用含有大量芳香族基且基板蝕刻耐性高的材料的話，會有k值變高且基板反射變高的情況，但藉由以含矽之光阻下層膜來抑制反射能使基板反射成為0.5%以下。又，在極紫外線(EUV)曝光時，使用含有大量芳香族基且基板蝕刻耐性高的有機膜材料的話，能形成微細圖案。
作為含矽之光阻下層膜宜使用聚矽氧烷基底之塗佈膜。藉由使含矽之光阻下層膜具有作為抗反射膜之效果，可抑制反射。具體而言，可列舉得自於日本特開2004-310019號公報、日本特開2007-302873號公報、日本特開2009-126940號公報等所揭示之組成物之含矽之光阻下層膜。
又，用來形成光阻上層膜之光阻組成物可為正型、負型之任一者，可使用與通常所使用的光阻組成物相同者。利用上述光阻組成物來形成光阻上層膜時，與上述形成有機膜時同樣地宜使用旋塗法。將光阻組成物予以旋塗後，會實施預烘，上述預烘宜在60~180℃、10~300秒之範圍內實施。其後遵循常規方法實施曝光，並實施曝光後烘烤(Post Exposure Bake，PEB)、顯影，可獲得光阻圖案(電路圖案)。另外，光阻上層膜之厚度並無特別限制，宜為30~500nm，為50~400nm特佳。
又，在電路圖案的形成中，宜利用波長為10nm以上300nm以下之高能射線所為之微影、電子束所為之直接描繪、及奈米壓印中之任一者、或它們的組合來形成電路圖案。
作為曝光光可列舉波長300nm以下之高能射線，具體而言可列舉248nm、193nm、157nm之準分子雷射、3~20nm之軟X射線，即所謂EUV光、電子束、X射線等。
又，在電路圖案的形成中，宜以鹼顯影或有機溶劑所為之顯影來顯影電路圖案。
然後，將得到的光阻圖案作為遮罩來實施蝕刻。含矽之光阻下層膜之乾蝕刻加工，例如可使用氟碳化物系氣體，並將上述之光阻圖案作為遮罩來實施。然後可將含矽之光阻下層膜圖案(已轉印有圖案之含矽之光阻下層膜)作為遮罩，並使用例如氧氣或氫氣來實施有機膜之乾蝕刻加工。
接下來的基板之蝕刻亦可利用常規方法來實施，例如：基板若為SiO2 、SiN、矽氧(silica)系低介電常數絕緣膜，則可藉由實施以氟碳化物系氣體為主體之蝕刻來將圖案轉印於基板；基板若為p-Si、Al、W，則可藉由實施以氯系、溴系氣體為主體之蝕刻來將圖案轉印於基板。
上述含矽之光阻下層膜上亦可形成有機抗反射膜(BARC)，再於其上形成光阻上層膜。亦即，本發明提供一種半導體裝置用基板之製造方法，係以上述之本發明之有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上使用含有矽之光阻下層膜形成用組成物來形成含矽之光阻下層膜，在該含矽之光阻下層膜上形成有機抗反射膜，在該有機抗反射膜上使用光阻組成物來形成光阻上層膜而製成4層光阻膜，在前述光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到前述有機抗反射膜與前述含矽之光阻下層膜，將轉印有該圖案之有機抗反射膜與含矽之光阻下層膜作為遮罩並以乾蝕刻將圖案轉印到前述有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
另外，此方法係於含矽之光阻下層膜之上形成有機抗反射膜，除此之外可與上述之使用了含矽之光阻下層膜之半導體裝置用基板之製造方法同樣地實施。就有機抗反射膜而言並無特別限制，可使用公知者，並可使用旋塗等公知的方法來形成。
又，亦可在上述有機膜上形成氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、或氮化鈦膜等之無機硬遮罩。亦即，本發明提供一種半導體裝置用基板之製造方法，係以上述之本發明之有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上形成選自於氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、及氮化鈦膜之無機硬遮罩，在該無機硬遮罩上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到前述無機硬遮罩，將轉印有該圖案之無機硬遮罩作為遮罩並以乾蝕刻將圖案轉印到有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
又，無機硬遮罩之形成宜利用CVD法或ALD法來實施。
無機硬遮罩的蝕刻可使用例如氟碳化物系氣體，並將光阻圖案作為遮罩來實施。然後，可將無機硬遮罩圖案作為遮罩，並使用氧氣或氫氣來實施有機膜之乾蝕刻加工。在有機膜之上形成無機硬遮罩來替換含矽之光阻下層膜，除此之外可與上述之使用了含矽之光阻下層膜之半導體裝置用基板之製造方法同樣地實施。
又，亦可在無機硬遮罩上形成由有機膜與含矽之光阻下層膜構成的多層光阻膜或有機抗反射膜。亦即，本發明提供一種半導體裝置用基板之製造方法，係以上述之本發明之有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上形成選自於氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、及氮化鈦膜之無機硬遮罩，在該無機硬遮罩上形成由有機膜與含矽之光阻下層膜構成的多層光阻膜或有機抗反射膜，在該多層光阻膜或有機抗反射膜上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻經由朝前述多層光阻膜或前述有機抗反射膜之圖案轉印而將前述圖案轉印到前述無機硬遮罩，將轉印有該圖案之無機硬遮罩作為遮罩並以乾蝕刻將圖案轉印到已形成於前述基板上之有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到前述基板。
使用了氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、或氮化鈦膜等之無機硬遮罩時，利用無機硬遮罩與BARC之組合，即使在NA超過1.0之高NA之浸潤式曝光，仍可抑制反射。形成BARC的另一個益處為：可獲得在無機硬遮罩正上方之製程允差變寬裕之效果。
另外，此方法係在無機硬遮罩上形成由有機膜與含矽之光阻下層膜構成的多層光阻膜或有機抗反射膜，除此之外可與上述使用了無機硬遮罩之半導體裝置用基板之製造方法同樣地實施。
如上所述，由於以本發明之方法形成的有機膜具有優良的平坦化特性，故藉由將此有機膜和例如在2層光阻製程、在使用有含矽之光阻下層膜之3層光阻製程、或在使用有含矽之光阻下層膜及有機抗反射膜之4層光阻製程等多層光阻製程中的各種膜材料組合使用，可將上層光阻(光阻上層膜)之圖案高精度地轉印至基板，並於基板上形成圖案。亦即，若為本發明之半導體裝置用基板之製造方法，則能製造高精度的半導體裝置用基板。 [實施例]
以下揭示合成例、製備例、實施例、及比較例具體地說明本發明，但本發明並不受限於該等記載。另外，就分子量而言，求得利用凝膠滲透層析法(GPC)所為之以聚苯乙烯換算之重量平均分子量(Mw)及數目平均分子量(Mn)，並由它們導出分散度(Mw/Mn)。
[合成例1] 將雙酚茀200g、37%甲醛水溶液75g、草酸5g放入300ml之燒瓶，邊攪拌邊使其在100℃反應24小時。反應後，使其溶解於甲基異丁酮500ml，並利用充分的水洗將觸媒與金屬雜質去除。然後，減壓去除溶劑，並於150℃減壓到2mmHg，將水分、未反應單體去除，獲得135g如下所示之聚合物1。利用GPC求得分子量(Mw)、分散度(Mw/Mn)。 分子量(Mw)=6,500 分散度(Mw/Mn)=5.20
[化1]聚合物1
[製備例1] 藉由使10質量份之上述聚合物1溶解於含有FC-430(住友3M公司製)0.1質量%之丙二醇單甲醚乙酸酯(以下PGMEA)100質量份中，並以0.1μm之氟樹脂製過濾器過濾，製得有機膜形成用組成物溶液(SOL-1)。
[實施例1] 備妥以二氧化矽形成有高度為0.1μm、寬度為1mm之凹凸圖案之矽基板A。在此基板A上旋轉塗佈SOL-1形成塗佈膜後，對基板施加振盪頻率為38kHz之振動5分鐘(振動處理)後，於300℃烘烤60秒鐘形成有機膜。將有圖案的部分與沒有圖案的部分以接觸式高低差計α-Step(KLA公司製)測定平坦度。結果如表1所示。
[實施例2] 備妥以二氧化矽在1mm之範圍內重複形成有高度為0.1μm、由半節距(half pitch)為50nm之圖案與50nm之間距(space)構成的重複圖案之基板B。使用基板B，除此之外與實施例1同樣地形成有機膜，並測定平坦度。結果如表1所示。
[比較例1] 使用基板A並與實施例1同樣地形成塗佈膜後，不實施上述振動處理，而於300℃烘烤60秒鐘形成有機膜。與實施例1同樣地測定平坦度。結果如表1所示。
[比較例2] 使用基板B替換基板A，除此之外與比較例1同樣地形成有機膜並測定平坦度。結果如表1所示。
[表1]
如表1所示，在形成塗佈膜後，並於烘烤(不溶化處理)前實施了對基板施加振動之處理之實施例1及實施例2，成功的利用有機膜將基板上之凹凸圖案填埋並將基板高度地平坦化。另一方面，未實施對基板施加振動之處理之比較例1及比較例2，無法將基板高度地平坦化。
由上可知：若為本發明之有機膜之形成方法，可形成能將基板高度地平坦化之有機膜。又，由於即使不使用高成本製程之CMP仍可將基板高度地平坦化，故啟示可用低成本實施基板之平坦化。
另外，本發明並不限於上述實施形態。上述實施形態係為例示，所有具有實質上與本發明之申請專利範圍所記載之技術思想相同的構成、發揮同樣的作用效果者，均包含於本發明之技術範圍內。
1‧‧‧基板
2‧‧‧塗佈膜
3‧‧‧有機膜
4‧‧‧塗佈膜形成後之基板
5‧‧‧振動發生裝置
6‧‧‧振動面
[圖1] (A)~(D)係以本發明之有機膜之形成方法在具有間距圖案(space pattern)之基板上形成有機膜之一例之流程圖。 [圖2] (A)~(D)係以本發明之有機膜之形成方法在具有線圖案(line pattern)之基板上形成有機膜之一例之流程圖。 [圖3] 係顯示本發明之有機膜之形成方法中的施加振動之處理之一例之說明圖。

Claims (12)

  1. 一種半導體裝置用基板之製造方法，其特徵為：以有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上使用含有矽之光阻下層膜形成用組成物來形成含矽之光阻下層膜，在該含矽之光阻下層膜上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到該含矽之光阻下層膜，將轉印有該圖案之含矽之光阻下層膜作為遮罩並以乾蝕刻將圖案轉印到該有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到該基板；該有機膜之形成方法係藉由在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理而形成有機膜之方法，形成該塗佈膜後，在該不溶化處理之前或與該不溶化處理同時，實施對該基板施加振動之處理。
  2. 一種半導體裝置用基板之製造方法，其特徵為：以有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上使用含有矽之光阻下層膜形成用組成物來形成含矽之光阻下層膜，在該含矽之光阻下層膜上形成有機抗反射膜，在該有機抗反射膜上使用光阻組成物來形成光阻上層膜而製成4層光阻膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到該有機抗反射膜與該含矽之光阻下層膜，將轉印有該圖案之有機抗反射膜與含矽之光阻下層膜作為遮罩並以乾蝕刻將圖案轉印到該有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到該基板；該有機膜之形成方法係藉由在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理而形成有機膜之方法，形成該塗佈膜後，在該不溶化處理之前或與該不溶化處理同時，實施對該基板施加振動之處理。
  3. 一種半導體裝置用基板之製造方法，其特徵為：以有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上形成選自於氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、及氮化鈦膜之無機硬遮罩，在該無機硬遮罩上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻將圖案轉印到該無機硬遮罩，將轉印有該圖案之無機硬遮罩作為遮罩並以乾蝕刻將圖案轉印到有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到該基板；該有機膜之形成方法係藉由在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理而形成有機膜之方法，形成該塗佈膜後，在該不溶化處理之前或與該不溶化處理同時，實施對該基板施加振動之處理。
  4. 一種半導體裝置用基板之製造方法，其特徵為：以有機膜之形成方法在具有凹凸圖案之基板上形成有機膜，在該有機膜上形成選自於氧化矽膜、氮化矽膜、氧氮化矽膜、非晶態矽膜、及氮化鈦膜之無機硬遮罩，在該無機硬遮罩上形成由有機膜與含矽之光阻下層膜構成的多層光阻膜或有機抗反射膜，在該多層光阻膜或有機抗反射膜上使用光阻組成物來形成光阻上層膜，在該光阻上層膜形成電路圖案，將形成有該圖案之光阻上層膜作為遮罩並以乾蝕刻經由朝該多層光阻膜或該有機抗反射膜之圖案轉印而將該圖案轉印到該無機硬遮罩，將轉印有該圖案之無機硬遮罩作為遮罩並以乾蝕刻將圖案轉印到已形成於該基板上之有機膜，再將轉印有該圖案之有機膜作為遮罩並以乾蝕刻將圖案轉印到該基板；該有機膜之形成方法係藉由在具有凹凸圖案之基板上旋轉塗佈有機膜形成用組成物來形成塗佈膜後，進行該塗佈膜對有機溶劑之不溶化處理而形成有機膜之方法，形成該塗佈膜後，在該不溶化處理之前或與該不溶化處理同時，實施對該基板施加振動之處理。
  5. 如申請專利範圍第1至4項中任一項之半導體裝置用基板之製造方法，其中，其係在該施加振動之處理中施加頻率為0.01Hz至10GHz之振動。
  6. 如申請專利範圍第1至4項中任一項之半導體裝置用基板之製造方法，其中，該不溶化處理係50℃以上500℃以下之熱處理、波長為400nm以下(10~400nm)之紫外線照射處理、及電子束照射處理中之任一者、或它們的組合。
  7. 如申請專利範圍第1至4項中任一項之半導體裝置用基板之製造方法，其係使用包含含有芳香環之樹脂者作為該有機膜形成用組成物。
  8. 如申請專利範圍第3或4項之半導體裝置用基板之製造方法，其係利用CVD法或ALD法來實施該無機硬遮罩之形成。
  9. 如申請專利範圍第1至4項中任一項之半導體裝置用基板之製造方法，其係在該電路圖案之形成中，利用波長為10nm以上300nm以下之高能射線所為之微影、電子束所為之直接描繪、及奈米壓印中之任一者、或它們的組合來形成電路圖案。
  10. 如申請專利範圍第1至4項中任一項之半導體裝置用基板之製造方法，其係在該電路圖案之形成中，以鹼顯影或有機溶劑所為之顯影來顯影電路圖案。
  11. 如申請專利範圍第1至4項中任一項之半導體裝置用基板之製造方法，其中，該基板含有金屬膜、金屬碳化物膜、金屬氧化物膜、金屬氮化物膜、或金屬氧氮化物膜。
  12. 如申請專利範圍第11項之半導體裝置用基板之製造方法，其中，構成該基板之金屬為矽、鈦、鎢、鉿、鋯、鉻、鍺、銅、鋁、銦、鎵、砷、鈀、鐵、鉭、銥、鉬、或它們的合金。
TW106112708A 2016-04-21 2017-04-17 半導體裝置用基板之製造方法 TWI624732B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2016-085123 2016-04-21
JP2016085123A JP6534959B2 (ja) 2016-04-21 2016-04-21 有機膜の形成方法及び半導体装置用基板の製造方法

Publications (2)

Publication Number Publication Date
TW201738662A TW201738662A (zh) 2017-11-01
TWI624732B true TWI624732B (zh) 2018-05-21

Family

ID=60088501

Family Applications (1)

Application Number Title Priority Date Filing Date
TW106112708A TWI624732B (zh) 2016-04-21 2017-04-17 半導體裝置用基板之製造方法

Country Status (4)

Country Link
US (1) US9984891B2 (zh)
JP (1) JP6534959B2 (zh)
KR (1) KR20170120516A (zh)
TW (1) TWI624732B (zh)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10490458B2 (en) 2017-09-29 2019-11-26 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of cutting metal gates and structures formed thereof
JP6894364B2 (ja) * 2017-12-26 2021-06-30 信越化学工業株式会社 有機膜形成用組成物、半導体装置製造用基板、有機膜の形成方法、及びパターン形成方法
CN112368645A (zh) 2018-06-13 2021-02-12 布鲁尔科技公司 用于euv光刻的粘附层
US11955336B2 (en) * 2021-04-23 2024-04-09 Taiwan Semiconductor Manufacturing Company, Ltd. Method of manufacturing a semiconductor device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005213105A (ja) * 2004-01-30 2005-08-11 Matsushita Electric Ind Co Ltd 多結晶金属酸化物薄膜とその製造方法及び不揮発性メモリ
US20080090170A1 (en) * 2006-10-04 2008-04-17 Ikuo Yoneda Pattern forming template and pattern forming method
US20100072889A1 (en) * 2007-05-29 2010-03-25 Asahi Glass Company, Limited Photosensitive composition, partition walls and black matrix

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3760030D1 (en) * 1986-02-07 1989-02-02 Nippon Telegraph & Telephone Photosensitive and high energy beam sensitive resin composition containing substituted polysiloxane
GB9018698D0 (en) * 1990-08-24 1990-10-10 Lynxvale Ltd Semiconductive copolymers for use in electroluminescent devices
JP2866996B2 (ja) * 1991-02-01 1999-03-08 日東電工株式会社 有機重合体溶液
JPH0539562A (ja) * 1991-08-06 1993-02-19 Fuji Electric Corp Res & Dev Ltd ＣｕＩｎＳｅ２ 薄膜の形成方法
JPH05160018A (ja) * 1991-12-04 1993-06-25 Fujitsu Ltd 回転塗布方法
JPH1197437A (ja) * 1997-09-18 1999-04-09 Asahi Kasei Micro Syst Co Ltd 半導体装置の製造方法および製造装置
US6503570B2 (en) * 2000-03-13 2003-01-07 Jrs Corporation Cyclosilane compound, and solution composition and process for forming a silicon film
US7813780B2 (en) * 2005-12-13 2010-10-12 Medtronic Minimed, Inc. Biosensors and methods for making and using them
US20070227907A1 (en) * 2006-04-04 2007-10-04 Rajiv Shah Methods and materials for controlling the electrochemistry of analyte sensors
US6993840B2 (en) * 2002-07-18 2006-02-07 Canon Kabushiki Kaisha Manufacturing method of liquid jet head
JP4369203B2 (ja) 2003-03-24 2009-11-18 信越化学工業株式会社 反射防止膜材料、反射防止膜を有する基板及びパターン形成方法
JP2004335873A (ja) 2003-05-09 2004-11-25 Toshiba Corp パターン形成方法
TWI281690B (en) 2003-05-09 2007-05-21 Toshiba Corp Pattern forming method, and manufacturing method for semiconductor using the same
TWI363251B (en) 2003-07-30 2012-05-01 Nissan Chemical Ind Ltd Sublayer coating-forming composition for lithography containing compound having protected carboxy group
JP2005292528A (ja) 2004-04-01 2005-10-20 Jsr Corp レジスト下層膜形成組成物、レジスト下層膜およびパターン形成方法
EP1845132B8 (en) 2006-04-11 2009-04-01 Shin-Etsu Chemical Co., Ltd. Silicon-containing film-forming composition, silicon-containing film, silicon-containing film-bearing substrate, and patterning method
JP4716037B2 (ja) 2006-04-11 2011-07-06 信越化学工業株式会社 ケイ素含有膜形成用組成物、ケイ素含有膜、ケイ素含有膜形成基板及びこれを用いたパターン形成方法
KR101423057B1 (ko) 2006-08-28 2014-07-25 닛산 가가쿠 고교 가부시키 가이샤 액상첨가제를 포함하는 레지스트 하층막 형성 조성물
JP4910168B2 (ja) 2006-09-07 2012-04-04 Ｊｓｒ株式会社 レジスト下層膜形成用組成物及びパターン形成方法
JP4793592B2 (ja) 2007-11-22 2011-10-12 信越化学工業株式会社 金属酸化物含有膜形成用組成物、金属酸化物含有膜、金属酸化物含有膜形成基板及びこれを用いたパターン形成方法
CN101945925A (zh) * 2008-02-15 2011-01-12 三菱化学株式会社 共轭聚合物、不溶性聚合物、有机场致发光元件材料、有机场致发光元件用组合物、聚合物的制造方法、有机场致发光元件、有机el显示器、以及有机el照明
JP5399347B2 (ja) * 2010-09-01 2014-01-29 信越化学工業株式会社 ケイ素含有膜形成用組成物、ケイ素含有膜形成基板及びこれを用いたパターン形成方法
KR20120112043A (ko) * 2011-03-30 2012-10-11 캐논 가부시끼가이샤 유기 발광장치의 제조방법
JP2013131641A (ja) * 2011-12-21 2013-07-04 Sharp Corp 半導体素子およびその製造方法、固体撮像素子およびその製造方法、回転塗布装置、電子情報機器
JP5925721B2 (ja) 2012-05-08 2016-05-25 信越化学工業株式会社 有機膜材料、これを用いた有機膜形成方法及びパターン形成方法
JP5894106B2 (ja) 2012-06-18 2016-03-23 信越化学工業株式会社 レジスト下層膜形成用化合物、これを用いたレジスト下層膜材料、レジスト下層膜形成方法、パターン形成方法
US8986921B2 (en) * 2013-01-15 2015-03-24 International Business Machines Corporation Lithographic material stack including a metal-compound hard mask
JP5913191B2 (ja) 2013-05-08 2016-04-27 信越化学工業株式会社 レジスト下層膜形成方法及びパターン形成方法
KR101656934B1 (ko) * 2014-07-29 2016-09-22 울산대학교 산학협력단 초음파 스핀 코터 및 이를 이용한 스핀 코팅 방법

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005213105A (ja) * 2004-01-30 2005-08-11 Matsushita Electric Ind Co Ltd 多結晶金属酸化物薄膜とその製造方法及び不揮発性メモリ
US20080090170A1 (en) * 2006-10-04 2008-04-17 Ikuo Yoneda Pattern forming template and pattern forming method
US20100072889A1 (en) * 2007-05-29 2010-03-25 Asahi Glass Company, Limited Photosensitive composition, partition walls and black matrix

Also Published As

Publication number Publication date
US9984891B2 (en) 2018-05-29
TW201738662A (zh) 2017-11-01
US20170309493A1 (en) 2017-10-26
JP2017195296A (ja) 2017-10-26
KR20170120516A (ko) 2017-10-31
JP6534959B2 (ja) 2019-06-26

Similar Documents

Publication Publication Date Title
TWI624732B (zh) 半導體裝置用基板之製造方法
WO2009096371A1 (ja) 微細パターンマスクおよびその製造方法、ならびにそれを用いた微細パターンの形成方法
TWI721125B (zh) 預圖案化微影模版、基於使用該模版的輻射圖案化之方法及形成該模版之方法
JP4852360B2 (ja) 多層リソグラフィプロセスにおいて用いられる複素環芳香族構造物を含む基層組成物、リソグラフィ構造物、材料層または材料要素を基板上に形成させる方法
JP6284925B2 (ja) 誘導自己組織化用のケイ素系ハードマスク層
TWI281690B (en) Pattern forming method, and manufacturing method for semiconductor using the same
TW201110196A (en) Methods of forming electronic devices
US8084185B2 (en) Substrate planarization with imprint materials and processes
JP6470079B2 (ja) パターン形成方法
JP2008258562A (ja) パターン形成方法
KR101096194B1 (ko) 반도체 소자의 패턴 형성 방법
TWI278915B (en) Pattern forming method, lower layer film forming composition and manufacturing method of semiconductor device
US20140094034A1 (en) Pattern forming method
US9280046B2 (en) Method of fabricating mask
JP6357753B2 (ja) ナノインプリントモールドの製造方法
JP2004145262A (ja) 半導体装置の製造方法及びパターンの形成方法
JP5661562B2 (ja) 微細パターンマスクおよびその製造方法、ならびにそれを用いた微細パターンの形成方法
TWI817027B (zh) 旋塗且藉cvd法沉積之有機膜的平坦化方法
US8138059B2 (en) Semiconductor device manufacturing method
JPWO2018155377A1 (ja) レジストプロセス用膜形成材料、パターン形成方法及びポリシロキサン
JP2001092152A (ja) 半導体装置の製造方法
TW201710794A (zh) 保形中間層的製作方法
JPS62247523A (ja) 半導体装置の製造方法
JPH05121311A (ja) レジストパターンの形成方法
TW201932633A (zh) 用於在半導體製程中形成微細矽圖案的新穎蝕刻方法