TWI613814B - 增強型高電子遷移率電晶體元件 - Google Patents

增強型高電子遷移率電晶體元件 Download PDF

Info

Publication number
TWI613814B
TWI613814B TW105139205A TW105139205A TWI613814B TW I613814 B TWI613814 B TW I613814B TW 105139205 A TW105139205 A TW 105139205A TW 105139205 A TW105139205 A TW 105139205A TW I613814 B TWI613814 B TW I613814B
Authority
TW
Taiwan
Prior art keywords
field plate
sub
nitride field
patterns
main pattern
Prior art date
Application number
TW105139205A
Other languages
English (en)
Other versions
TW201820628A (zh
Inventor
維克 韋
Vivek Ningaraju
陳柏安
Po-An Chen
Original Assignee
新唐科技股份有限公司
Nuvoton Technology Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 新唐科技股份有限公司, Nuvoton Technology Corporation filed Critical 新唐科技股份有限公司
Priority to TW105139205A priority Critical patent/TWI613814B/zh
Priority to US15/691,761 priority patent/US20180151712A1/en
Priority to CN201710805303.4A priority patent/CN108122968B/zh
Application granted granted Critical
Publication of TWI613814B publication Critical patent/TWI613814B/zh
Publication of TW201820628A publication Critical patent/TW201820628A/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H01L29/404—Multiple field plate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
    • H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
    • H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H01L29/7787—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Junction Field-Effect Transistors (AREA)

Abstract

提供一種增強型高電子遷移率電晶體元件，其包括基板、通道層、阻障層、氮化物場板、P型半導體層、閘極、源極與汲極。通道層配置於基板上。阻障層配置於通道層上。氮化物場板配置於阻障層上且包括一主圖案以及位於主圖案側邊的多個次圖案。P型半導體層配置於氮化物場板的主圖案上。閘極配置於P型半導體層上。源極與汲極配置於閘極兩側的阻障層上。

Description

增強型高電子遷移率電晶體元件
本發明是有關於一種半導體元件，且特別是有關於一種增強型（enhancement mode）高電子遷移率電晶體（high electron mobility transistor；HEMT）元件。
近年來，以III-V族化合物半導體為基礎的HEMT元件因為其低阻值、高崩潰電壓以及快速開關切換頻率等特性，在高功率電子元件領域被廣泛地應用。
一般來說，HEMT元件可分為消耗型或常開型電晶體元件，以及增強型或常關型電晶體元件。增強型電晶體元件因為其提供的附加安全性以及其更易於由簡單、低成本的驅動電路來控制，因而在業界獲得相當大的關注。
有鑒於此，本發明提供一種增強型HEMT元件，藉由配置氮化物場板於P型半導體層與阻障層之間，可有效分散電場，提升元件的可靠度。
本發明提供一種增強型HEMT元件，其包括基板、通道層、阻障層、氮化物場板、P型半導體層、閘極、源極與汲極。通道層配置於基板上。阻障層配置於通道層上。氮化物場板配置於阻障層上且包括一主圖案以及位於主圖案側邊的多個次圖案。P型半導體層配置於氮化物場板的主圖案上。閘極配置於P型半導體層上。源極與汲極配置於閘極兩側的阻障層上。
在本發明的一實施例中，上述氮化物場板的次圖案位於閘極與汲極之間的阻障層上。
在本發明的一實施例中，上述氮化物場板的次圖案的寬度實質上相等。
在本發明的一實施例中，上述氮化物場板的次圖案的寬度隨著接近汲極而逐漸減少。
在本發明的一實施例中，上述氮化物場板的主圖案的寬度大於次圖案中至少一者的寬度。
在本發明的一實施例中，上述氮化物場板的次圖案的厚度實質上相等。
在本發明的一實施例中，上述氮化物場板的次圖案的厚度隨著接近汲極而逐漸減少。
在本發明的一實施例中，上述氮化物場板的主圖案的厚度大於或等於次圖案中至少一者的厚度。
在本發明的一實施例中，上述氮化物場板的次圖案的摻雜濃度實質上相等。
在本發明的一實施例中，上述氮化物場板的次圖案的摻雜濃度隨著接近汲極而逐漸減少。
在本發明的一實施例中，上述氮化物場板的主圖案的摻雜濃度大於或等於次圖案中至少一者的摻雜濃度。
在本發明的一實施例中，上述氮化物場板的平均摻雜濃度低於P型半導體層的平均摻雜濃度。
在本發明的一實施例中，上述氮化物場板的次圖案之間的間隙實質上相等。
在本發明的一實施例中，上述氮化物場板的次圖案之間的間隙隨著接近汲極而逐漸減少。
在本發明的一實施例中，上述氮化物場板的主圖案的一邊界突出於P型半導體層的一邊界，且氮化物場板的主圖案的另一邊界對齊於P型半導體層的另一邊界。
在本發明的一實施例中，上述阻障層與氮化物場板的組成實質上相同。
在本發明的一實施例中，上述阻障層未經摻雜，而氮化物場板摻雜有P型摻質。
在本發明的一實施例中，上述氮化物場板的厚度介於約20埃至400埃之間。
在本發明的一實施例中，上述氮化物場板的摻雜濃度為約10 15至10 18原子/cm 3。
在本發明的一實施例中，上述氮化物場板的材料包括AlGaN、AlInN、AlN或AlGaInN或其組合。
基於上述，將本發明的氮化物場板引入增強型HEMT元件中，可有效分散電場，提升元件的可靠度。更具體地說，本發明的氮化物場板具有凸出於P型半導體層的主圖案以及位於閘極與汲極之間的多個次圖案。主圖案有助於降低閘極轉角處的電場。次圖案用以形成二維電子氣密度較低的區域。以此配置方式，能有效分散電場、提高擊穿電壓並減少漏電流。
為讓本發明的上述特徵和優點能更明顯易懂，下文特舉實施例，並配合所附圖式作詳細說明如下。
圖1至圖8是依照本發明一些實施例所繪示的多種增強型HEMT元件的剖面示意圖。圖1至圖8的增強型HEMT元件類似，其差別在於氮化物場板的圖案分布、厚度、摻雜濃度等參數不盡相同。將詳細說明如下。
請參照圖1至圖8，本發明的增強型HEMT元件包括基板100、緩衝層102、通道層104、阻障層106、P型半導體層110、閘極G、源極S與汲極D。
通道層104形成在基板100上。在一實施例中，基板100的材料包括藍寶石、Si、SiC或GaN。在一實施例中，通道層104的材料包括III族氮化物，例如III-V族化合物半導體材料。在一實施例中，通道層104的材料包括GaN。此外，通道層104可以是經摻雜或未經摻雜的層。
緩衝層102可配置於基板100和通道層104之間，用以減少基板100和通道層104之間的晶格常數差異和熱膨脹係數差異。在一實施例中，緩衝層102的材料包括III族氮化物，例如III-V族化合物半導體材料，並可具有單層或多層結構。在一實施例中，緩衝層的材料包括AlN、GaN、AlGaN、InGaN、AlInN、AlGaInN或其組合。
阻障層106配置於通道層104上。在一實施例中，阻障層106的材料包括III族氮化物，例如III-V族化合物半導體材料，並可具有單層或多層結構。在一實施例中，阻障層106包括AlGaN、AlInN、AlN或AlGaInN或其組合。在一實施例中，阻障層106可以是經摻雜或未經摻雜的層。
閘極G配置在阻障層106上。閘極G的材料包括金屬或金屬氮化物（例如Ta、TaN、Ti、TiN、W、Pd、Ni、Au、Al或其組合）、金屬矽化物（例如WSi x）或其他可與III-V族化合物半導體形成蕭特基接觸（Schottky contact）的材料。
源極S與汲極D配置在閘極G兩側的阻障層106上，如圖1至圖8所示。然而，本發明並不以此為限。在另一實施例中，源極S及/或汲極D中至少一者可延伸至通道層104中並電性連接至二維電子氣（2DEG）。源極S與汲極D的材料包括金屬（例如Al、Ti、Ni、Au或其合金），或其他可與III-V族化合物半導體形成歐姆接觸（ohmic contact）的材料。
P型半導體層110配置於阻障層106與閘極G之間，用以形成二維電子氣的斷開區或者具有相對低的電子密度的區域。在一實施例中，P型半導體層110的材料包括III族氮化物，例如III-V族化合物半導體材料。在一實施例中，P型半導體層110的材料包括GaN、AlGaN、InN、AlInN、InGaN或AlInGaN，並摻雜有P型摻質（例如Mg）。在一實施例中，P型半導體層110可為P型GaN層或P型Al xGa 1-xN層，其中x為0~1，例如0.05~1。在一實施例中，P型半導體層110的厚度介於約100埃至3,000埃之間，且其摻雜濃度為約10 18至10 21原子/cm 3。
特別要注意的是，本發明的增強型HEMT元件更包括氮化物場板108，用以降低閘極轉角處的高電場，以避免漏電流並提升元件的可靠度。在一實施例中，氮化物場板108配置於阻障層106上且包括一個主圖案107以及位於主圖案側邊的多個次圖案109a~109d。在一實施例中，P型半導體層110配置於氮化物場板108的主圖案107上。更具體地說，氮化物場板108的主圖案107的一邊界突出於P型半導體層110的一邊界，而氮化物場板108的主圖案107的另一邊界對齊於P型半導體層110的另一邊界。
此外，氮化物場板108的次圖案109a~109d位於閘極G與汲極D之間的阻障層106上，以進一步均勻分散閘極與汲極之間的高電場聚集效應。
在一實施例中，氮化物場板108的材料包括III族氮化物，例如III-V族化合物半導體材料。在一實施例中，氮化物場板108的材料包括AlGaN、AlInN、AlN或AlGaInN或其組合，並摻雜有P型摻質（例如Mg）。在一實施例中，阻障層106與氮化物場板108的組成實質上相同。在一實施例中，阻障層106與氮化物場板108的組成元素大致上相同，僅摻雜濃度不同。在一實施例中，阻障層106與氮化物場板108的材料相同，阻障層106為未經摻雜，而氮化物場板108摻雜有P型摻質。
在一實施例中，阻障層106與氮化物場板108的材料均包括Al yGa 1-yN，其中y為0~1，例如0.1~1。在另一實施例中，阻障層106的材料包括Al yGa 1-yN，氮化物場板108的材料包括Al zGa 1-zN，其中y、z均為0~1，且y不等於z。在一實施例中，y大於z。在另一實施例中，y小於z。
在一實施例中，氮化物場板108的厚度約20埃至400埃之間，且其摻雜濃度為約10 15至10 18原子/cm 3。在一實施例中，氮化物場板108的平均摻雜濃度低於P型半導體層110的平均摻雜濃度。
在一實施例中，氮化物場板108的次圖案109a~109d的寬度實質上相等，如圖1的增強型HEMT元件10所示。在另一實施例中，氮化物場板108的次圖案109a~109d的寬度隨著接近汲極D而逐漸減少，如圖2的增強型HEMT元件20所示。更具體地說，如圖2所示，次圖案109a的寬度大於次圖案109b的寬度，次圖案109b的寬度大於次圖案109c的寬度，且次圖案109c的寬度大於次圖案109d的寬度。此外，氮化物場板108的主圖案107的寬度大於次圖案109a~109d中至少一者的寬度。
在一實施例中，氮化物場板108的次圖案109a~109d的厚度實質上相等，如圖1的增強型HEMT元件10、圖2的增強型HEMT元件20所示。在另一實施例中，氮化物場板108的次圖案109a~109d的厚度隨著接近汲極D而逐漸減少，如圖3的增強型HEMT元件30、圖4的增強型HEMT元件40所示。更具體地說，如圖3及圖4所示，次圖案109a的厚度大於次圖案109b的厚度，次圖案109b的厚度大於次圖案109c的厚度，且次圖案109c的厚度大於次圖案109d的厚度。此外，氮化物場板108的主圖案107的厚度大於或等於次圖案109a~109d中至少一者的厚度。
在一實施例中，氮化物場板108的次圖案109a~109d之間的間隙實質上相等，如圖1的增強型HEMT元件10、圖2的增強型HEMT元件20、圖3的增強型HEMT元件30、圖4的增強型HEMT元件40所示。在另一實施例中，氮化物場板108的次圖案109a~109d之間的間隙隨著接近汲極D而逐漸減少，如圖5的增強型HEMT元件50、圖6的增強型HEMT元件60、圖7的增強型HEMT元件70、圖8的增強型HEMT元件80所示。更具體地說，如圖5至圖8所示，次圖案109a與次圖案109b之間的間隙大於次圖案109b與次圖案109c之間的間隙，且次圖案109b與次圖案109c之間的間隙大於次圖案109c與次圖案109d之間的間隙。此外，主圖案107與次圖案109a之間的間隙大於或等於次圖案109a~109d之間的間隙中的至少一者。
在一實施例中，氮化物場板108的次圖案109a~109d的摻雜濃度可實質上相等。在另一實施例中，氮化物場板108的次圖案109a~109d的摻雜濃度隨著接近汲極D而逐漸減少。以上兩種摻雜濃度的態樣適用於圖1至圖8的增強型HEMT元件10~80中。此外，氮化物場板108的主圖案107的摻雜濃度大於或等於次圖案109a~109d中至少一者的摻雜濃度。
在上述實施例中，是以氮化物場板具有一個主圖案與四個次圖案為例來說明之，但並不用以限定本發明。在另一實施例中，本發明的氮化物場板可具有一個、二個、三個或大於四個次圖案。另外，本發明的氮化物場板的次圖案的圖案分布、厚度、摻雜濃度不以上述實施例為限，可依製程需要調整，只要能達到有效分散電場，提升元件的可靠度即可。
綜上所述，在本發明實施例中，以閘極下方的P型半導體層來空乏阻障層中所形成的二維電子氣，以形成增強型或常關型HEMT元件。此外，藉由配置本發明的氮化物場板於P型半導體層與阻障層之間，可有效分散電場，提升元件的可靠度。更具體地說，本發明的氮化物場板具有凸出於P型半導體層的主圖案以及位於閘極與汲極之間的多個次圖案。主圖案有助於降低閘極轉角處的電場。次圖案用以形成二維電子氣密度較低的區域。以此配置方式，能有效分散電場、提高擊穿電壓並減少漏電流。
雖然本發明已以實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明的精神和範圍內，當可作些許的更動與潤飾，故本發明的保護範圍當視後附的申請專利範圍所界定者為準。
10、20、30、40、50、60、70、80‧‧‧增強型HEMT元件
100‧‧‧基板
102‧‧‧緩衝層
104‧‧‧通道層
106‧‧‧阻障層
107‧‧‧主圖案
108‧‧‧氮化物場板
109a、109b、109c、109d‧‧‧次圖案
110‧‧‧P型半導體層
D‧‧‧汲極
G‧‧‧閘極
S‧‧‧源極
圖1至圖8是依照本發明一些實施例所繪示的多種增強型HEMT元件的剖面示意圖。
10‧‧‧增強型HEMT元件
100‧‧‧基板
102‧‧‧緩衝層
104‧‧‧通道層
106‧‧‧阻障層
107‧‧‧主圖案
108‧‧‧氮化物場板
109a、109b、109c、109d‧‧‧次圖案
110‧‧‧P型半導體層
D‧‧‧汲極
G‧‧‧閘極
S‧‧‧源極

Claims (10)

  1. 一種增強型高電子遷移率電晶體元件，包括：一通道層，配置於一基板上；一阻障層，配置於該通道層上；一氮化物場板，配置於該阻障層上且包括一主圖案以及位於該主圖案側邊的多個次圖案；一P型半導體層，配置於該氮化物場板的該主圖案上；一閘極，配置於該P型半導體層上；以及一源極與一汲極，配置於該閘極兩側的該阻障層上，其中該氮化物場板的該主圖案與該些次圖案彼此分開。
  2. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該些次圖案位於該閘極與該汲極之間的該阻障層上。
  3. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該些次圖案的寬度實質上相等。
  4. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該些次圖案的寬度隨著接近該汲極而逐漸減少。
  5. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該主圖案的寬度大於該些次圖案中至少一者的寬度。
  6. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該些次圖案的厚度實質上相等。
  7. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該些次圖案的厚度隨著接近該汲極而逐漸減少。
  8. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該主圖案的厚度大於或等於該些次圖案中至少一者的厚度。
  9. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的平均摻雜濃度低於該P型半導體層的平均摻雜濃度。
  10. 如申請專利範圍第1項所述的增強型高電子遷移率電晶體元件，其中該氮化物場板的該主圖案的一邊界突出於該P型半導體層的一邊界，且該氮化物場板的該主圖案的另一邊界對齊於該P型半導體層的另一邊界。
TW105139205A 2016-11-29 2016-11-29 增強型高電子遷移率電晶體元件 TWI613814B (zh)

Priority Applications (3)

Application Number Priority Date Filing Date Title
TW105139205A TWI613814B (zh) 2016-11-29 2016-11-29 增強型高電子遷移率電晶體元件
US15/691,761 US20180151712A1 (en) 2016-11-29 2017-08-31 Enhancement mode hemt device
CN201710805303.4A CN108122968B (zh) 2016-11-29 2017-09-08 增强型高电子迁移率晶体管元件

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
TW105139205A TWI613814B (zh) 2016-11-29 2016-11-29 增強型高電子遷移率電晶體元件

Publications (2)

Publication Number Publication Date
TWI613814B true TWI613814B (zh) 2018-02-01
TW201820628A TW201820628A (zh) 2018-06-01

Family

ID=62014510

Family Applications (1)

Application Number Title Priority Date Filing Date
TW105139205A TWI613814B (zh) 2016-11-29 2016-11-29 增強型高電子遷移率電晶體元件

Country Status (3)

Country Link
US (1) US20180151712A1 (zh)
CN (1) CN108122968B (zh)
TW (1) TWI613814B (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331719A (zh) * 2020-04-30 2021-02-05 英诺赛科（珠海）科技有限公司 半导体器件以及制造半导体器件的方法

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP7021038B2 (ja) * 2018-09-18 2022-02-16 株式会社東芝 半導体装置
TWI692867B (zh) * 2018-10-04 2020-05-01 新唐科技股份有限公司 高電子遷移率電晶體元件及其製造方法
CN110137253A (zh) * 2019-04-25 2019-08-16 芜湖启迪半导体有限公司 一种耐高压的hemt器件及制备方法
CN110600548A (zh) * 2019-09-20 2019-12-20 中国电子科技集团公司第十三研究所 增强型异质结场效应晶体管
CN111370483B (zh) * 2020-02-27 2023-05-26 常熟理工学院 一种具有多场板结构的氮化镓功率器件及其制备方法
US20220130988A1 (en) * 2020-10-27 2022-04-28 Texas Instruments Incorporated Electronic device with enhancement mode gallium nitride transistor, and method of making same
TWI803845B (zh) * 2021-03-24 2023-06-01 新唐科技股份有限公司 半導體結構
KR20220138756A (ko) * 2021-04-06 2022-10-13 삼성전자주식회사 파워 소자 및 그 제조방법
WO2024030127A1 (en) * 2022-08-03 2024-02-08 Vishay Siliconix Llc P-gan high electron mobility transistor field plating
CN115732563A (zh) * 2022-11-29 2023-03-03 西安电子科技大学 一种热电优化的鳍式氧化镓mosfet结构及制作方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201428964A (zh) * 2012-12-07 2014-07-16 Sony Corp 半導體裝置及其製造方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3111985B2 (ja) * 1998-06-16 2000-11-27 日本電気株式会社 電界効果型トランジスタ
JP4712683B2 (ja) * 2006-12-21 2011-06-29 パナソニック株式会社 トランジスタおよびその製造方法
KR101666910B1 (ko) * 2009-04-08 2016-10-17 이피션트 파워 컨버젼 코퍼레이션 증가형 ＧａＮ ＨＥＭＴ 장치 및 그 제조 방법
KR20140115585A (ko) * 2013-03-21 2014-10-01 서울반도체 주식회사 멀티 필드 플레이트 트랜지스터 및 그 제조 방법
JP6170007B2 (ja) * 2014-04-10 2017-07-26 トヨタ自動車株式会社 スイッチング素子
CN104201201B (zh) * 2014-09-16 2017-03-15 电子科技大学 一种用于GaN基HEMT器件的自适应偏置场板
CN104269434B (zh) * 2014-09-19 2018-01-05 苏州捷芯威半导体有限公司 一种高电子迁移率晶体管

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201428964A (zh) * 2012-12-07 2014-07-16 Sony Corp 半導體裝置及其製造方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112331719A (zh) * 2020-04-30 2021-02-05 英诺赛科（珠海）科技有限公司 半导体器件以及制造半导体器件的方法

Also Published As

Publication number Publication date
TW201820628A (zh) 2018-06-01
CN108122968A (zh) 2018-06-05
US20180151712A1 (en) 2018-05-31
CN108122968B (zh) 2020-09-04

Similar Documents

Publication Publication Date Title
TWI613814B (zh) 增強型高電子遷移率電晶體元件
US8890212B2 (en) Normally-off high electron mobility transistor
TWI661554B (zh) 增強型高電子遷移率電晶體元件及其形成方法
US20150179741A1 (en) Semiconductor device
US11881479B2 (en) Nitride semiconductor device
WO2005024955A1 (ja) 半導体装置
US9502548B1 (en) Semiconductor device
TW201705445A (zh) 半導體裝置
KR20140012507A (ko) 고전자 이동도 트랜지스터 및 그 제조방법
US9252253B2 (en) High electron mobility transistor
US20150263155A1 (en) Semiconductor device
JP2023001273A (ja) 窒化物半導体装置
US9647102B2 (en) Field effect transistor
TWI624872B (zh) 氮化物半導體元件
TWI679770B (zh) 氮化鎵高電子移動率電晶體及其閘極結構
KR20230000718A (ko) 고전자이동도 트랜지스터 및 그 제조 방법
JP6639260B2 (ja) 半導体装置
KR101668445B1 (ko) 반도체 소자 및 그의 제조방법
JP7308593B2 (ja) 窒化物半導体装置
CN114342088B (zh) 半导体装置及其制造方法
JP2011151176A (ja) 高電子移動度トランジスタ
TWI701836B (zh) 增強型高電子遷移率電晶體元件及其製造方法
JP4444188B2 (ja) ＧａＮ系半導体装置
JP2017098307A (ja) 半導体装置及びその製造方法
KR20210107064A (ko) 반도체 구조 및 이의 제조 방법