TWI611460B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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TWI611460B
TWI611460B TW105133750A TW105133750A TWI611460B TW I611460 B TWI611460 B TW I611460B TW 105133750 A TW105133750 A TW 105133750A TW 105133750 A TW105133750 A TW 105133750A TW I611460 B TWI611460 B TW I611460B
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layer
etch stop
conductive element
stop layer
dielectric material
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TW201725606A (zh
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吳永旭
陳海清
蔡榮訓
眭曉林
包天一
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台灣積體電路製造股份有限公司
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Abstract

在基板上方形成互連結構的層。此層含有層間介電質(interlayer dielectric；ILD)材料及配置在層間介電質中的金屬接線。在層間介電質上形成第一蝕刻停止層，但不形成於金屬接線上。經由選擇性原子層沉積製程形成第一蝕刻停止層。在第一蝕刻停止層上方形成第二蝕刻停止層。高蝕刻選擇性存在於第一蝕刻停止層與第二蝕刻停止層之間。形成導孔以使金屬接線至少部分地對準並電耦接至金屬接線。第一蝕刻停止層是用於避免層間介電質在導孔形成期間被蝕刻穿透。

Description

半導體裝置及其製造方法
本揭露是關於一種半導體裝置及其製造方法，特別是關於一種利用選擇性蝕刻停止層形成自對準導孔之半導體裝製及其製造方法。
半導體積體電路(semiconductor integrated circuit；IC)工業已經歷了快速增長。積體電路材料及設計的技術進步已生產了數代積體電路，其中每一代皆比上一代具有更小且更加複雜的電路。然而，此等進步已增加了處理及製造積體電路的複雜性，且為了實現此等進步，需要積體電路處理及製造中的類似發展。在積體電路發展過程中，功能密度(亦即，單位晶片面積中的互連裝置數目)大體上增加，而幾何形狀尺寸(亦即，可使用製造製程產生的最小組件(或接線))減小。
半導體製程中，可形成導電元件來為IC的各組件提供電互連。舉例而言，可藉由在層間介電質(interlayer dielectric；ILD)中蝕刻開口及用導電材料填充此等開口來形成使不同金屬層互連的導電導孔。然而，隨著半導體製造技術節點不斷進化，臨界尺寸及間距變得越來越小，且製程窗口變 得更加緊密。因此，可能發生上覆誤差(例如，導孔不對準)，此可導致諸如可靠性測試邊限減小或裝置效能降低之問題。
因此，儘管習知導孔形成製程已大體上對於所欲用途足夠，但此等製程尚未在每一態樣中皆令人滿意。
本揭露之一實施例為一種半導體裝置。半導體裝置包括形成在基板上方的互連結構之第一層。第一層含有第一介電材料及配置在第一介電材料中的第一導電元件。半導體裝置包括第一蝕刻停止層，此第一蝕刻停止層配置在第一層之第一介電材料上，但不配置在第一層之第一導電元件上。半導體裝置包括配置在第一層上方的第二導電元件。將第二導電元件與第一導電元件至少部分地對準並電耦接至第一導電元件。
本揭露之另一實施例為一種半導體裝置。半導體裝置包括配置在基板上方的互連結構之MX互連層。MX互連層含有第一介電材料及配置在第一介電材料中的複數個第一金屬接線。半導體裝置包括第一蝕刻停止層，此第一蝕刻停止層配置在第一介電材料上，但不配置在第一金屬接線上。第一蝕刻停止層含有氧化鉿、氧化鋯或氧化鋁。半導體裝置包括配置在第一蝕刻停止層上方的第二蝕刻停止層，其中第二蝕刻停止層含有碳氧化矽(SiOC)或氮氧化矽(SiON)。半導體裝置包括配置在MX互連層上方的互連結構之MX+1互連層。MX+1互連層含有第二介電材料及配置在第二介電材料中的第二金屬接線。半導體裝置包括導孔，此導孔將第一金屬接線之至少一者 與第二金屬接線電互連。導孔延伸穿過第二蝕刻停止層，但不穿過第一蝕刻停止層。
本揭露之又一實施例為一種製造半導體裝置的方法。在第一介電材料中形成第一導電元件。經由選擇性原子層沉積(ALD)製程，在第一介電材料上形成第一蝕刻停止層，但不形成於第一導電元件上。在第一導電元件上方形成第二導電元件。將第二導電元件形成為與第一導電元件至少部分地對準並電耦接至第一導電元件。
50‧‧‧半導體裝置
60‧‧‧基板
70‧‧‧介電層
80‧‧‧導電元件
90‧‧‧研磨製程
100‧‧‧蝕刻停止層
110‧‧‧選擇性原子層沉積製程
120‧‧‧厚度
130‧‧‧蝕刻停止層
140‧‧‧厚度
150‧‧‧介電材料
160‧‧‧導孔
160A‧‧‧區段
160B‧‧‧區段
180‧‧‧導電元件
200‧‧‧金屬封端層
220‧‧‧厚度
300‧‧‧蝕刻停止層
310‧‧‧選擇性原子層沉積製程
320‧‧‧厚度
330‧‧‧凹部
340‧‧‧硬遮罩層
350‧‧‧硬遮罩沉積製程
360‧‧‧厚度
500‧‧‧方法
510‧‧‧步驟
520‧‧‧步驟
530‧‧‧步驟
540‧‧‧步驟
550‧‧‧步驟
560‧‧‧步驟
當結合隨附圖式閱讀時，自以下詳細描述很好地理解本揭露之態樣。應強調，根據工業中的標準實務，各特徵並未按比例繪製。事實上，為了論述清楚，可任意增加或減小各特徵之尺寸。
第1圖至第14圖為根據本揭露部分實施例的各製造階段處的半導體裝置之側視截面圖。
第15圖係圖示根據本揭露部分實施例的製造半導體裝置之方法的流程圖。
以下揭示內容提供許多不同實施例或實例，以便實施所提供標的之不同特徵。下文描述組件及排列之特定實例以簡化本揭露。當然，此等僅為實例且不欲視為限制。舉例而言，以下描述中在第二特徵上方或第二特徵上形成第一特徵可 包括以直接接觸形成第一特徵及第二特徵的實施例，且亦可包括可在第一特徵與第二特徵之間形成額外特徵以使得第一特徵及第二特徵可不處於直接接觸的實施例。另外，本揭露可在各實例中重複元件符號及/或字母。此重複係出於簡明性及清晰之目的，且本身並不指示所論述之各實施例及/或配置之間的關係。
另外，為了便於描述，本文可使用空間相對性術語(諸如「之下」、「下方」、「下部」、「上方」、「上部」等)來描述諸圖中所圖示一個元件或特徵與另一元件(或多個元件)或特徵(或多個特徵)之關係。除了諸圖所描繪之定向外，空間相對性術語意欲包含使用或操作中元件之不同定向。機構可經其他方式定向(旋轉90度或處於其他定向上)且因此可類似解讀本文所使用之空間相對性描述詞。
作為半導體製造的一部分，需要形成電互連以使半導體裝置之各微電子元件(例如，源極/汲極、閘極等)電互連。大體而言，此涉及在多層中(諸如在電絕緣層中)形成開口，及隨後用導電材料填充此等開口。隨後研磨導電材料以形成電互連，諸如金屬接線或導孔。
然而，隨著半導體技術世代繼續發展縮小製程，精確對準或上覆可因日益減小的溝槽尺寸而成為問題。舉例而言，將導孔與上方或下方的所欲金屬接線精確對準可更加困難。當發生導孔不對準或上覆問題時，習知製造方法可導致導孔開口下方的介電材料(例如，層間介電質)不良的過度蝕刻。當稍後用金屬材料填充導孔開口時，導孔開口的形狀類似於虎 牙。此類「虎牙」導孔可導致裝置效能降低。可需要使用較緊密的製程窗口避免此等問題，但此亦可劣化裝置效能。
為改良導孔對準及在導孔形成期間避免層間介電質之過度蝕刻，本揭露提出一種新穎方法及結構，使用蝕刻停止層之選擇性沉積來擴大製程窗口，而無需犧牲效能。現將參看第1圖至第15圖更詳細地論述本揭露之各態樣。
第1圖至第4圖係為本揭露之部分實施例在各製造階段處的半導體裝置50之局部側視截面圖。在5奈米或更低的半導體技術世代下製造半導體裝置50。半導體裝置50可包括積體電路(IC)晶片、晶片上系統(system on chip；SoC)或上述之部分，且可包括各種被動及主動微電子裝置，諸如電阻器、電容器、電感器、二極體、金屬氧化物半導體場效電晶體(metal-oxide semiconductor field effect transistors；MOSFET)、互補金屬氧化物半導體(complementary metal-oxide semiconductor；CMOS)電晶體、雙極接合電晶體(bipolar junction transistors；BJT)、橫向擴散MOS(laterally diffused MOS；LDMOS)電晶體、高功率MOS電晶體或其他類型的電晶體。
半導體裝置50包括基板60。在一些實施例中，基板60為摻有p型摻雜劑(諸如硼)的矽基板(例如，p型基板)。或者，基板60可為另一適宜半導體材料。舉例而言，基板60可為摻有n型摻雜劑(諸如磷或砷)的矽基板(n型基板)。基板60可包括其他元素性半導體，諸如鍺及金剛石。基板60可視情況包括化合物半導體及/或合金半導體。進一步地，基板60可包括 磊晶層，可為了效能增強而產生應變，並可包括絕緣體上矽(silicon-on-insulator；SOI)結構。
在一些實施例中，基板60為實質導電或半導電基板。電阻可小於約103歐姆-米。在一些實施例中，基板60含有金屬、金屬合金或具有式MXa的金屬氮化物/硫化物/硒化物/氧化物/矽化物，其中M為金屬，而X為氮(N)、硫(S)、硒(Se)、氧(O)、矽(Si)，且其中「a」的範圍約0.4至2.5內。舉例而言，基板60可含有鈦(Ti)、鋁(Al)、鈷(Co)、釕(Ru)、氮化鈦(TiN)、氮化鎢(WN2)或氮化組(TaN)。
在一些其他實施例中，基板60含有介電材料，其中介電常數處於自約1至約40範圍內。在一些其他實施例中，基板60含有矽、金屬氧化物或金屬氮化物，其中式為MXb，其中M為金屬或矽，及X為氮(N)或氧(O)，且其中「b」的範圍約0.4至2.5內。舉例而言，基板60可含有二氧化矽(SiO2)、氮化矽、氧化鋁、氧化鉿或氧化鑭。
應理解，可在基板60中形成複數個汲極/源極，並可在基板60上方形成複數個閘極。然而，為簡化之原因，本文並未特定說明此等汲極/源極或閘極。
在基板60上方形成介電層70。可使用沉積製程形成介電層70。在各實施例中，介電層70可含有低介電常數介電材料。低介電常數介電材料可指示具有介電常數低於二氧化矽之介電常數(約為3.9)的介電材料。作為非限制性實例，低介電常數介電材料可包括摻氟二氧化矽、摻碳二氧化矽、多孔 二氧化矽、多孔摻碳二氧化矽、旋塗有機聚合介電材料或旋塗矽基聚合介電材料。
在介電層70中形成複數個導電元件80。導電元件80亦稱為多層互連結構之MX互連層之金屬接線。藉由在介電層70中蝕刻開口及用導電材料填充此等開口來形成導電元件80。在一些實施例中，導電材料可含有銅或鋁。執行研磨製程(諸如化學機械研磨)90以研磨介電層70及導電元件80之上表面。
現參看第2圖，在介電層70之上表面上方形成蝕刻停止層(etching stop layer)100，但不形成於導電元件80上。形成蝕刻停止層100含有金屬氧化物。經由選擇性原子層沉積(selective atomic layer deposition；SALD)製程110形成蝕刻停止層。在選擇性原子層沉積製程110中，執行交替循環。在一個循環中，接通前驅物氣體。在另一循環中，接通氧化劑氣體。將此等循環重複若干次，可精確控制此等循環以生長所欲厚度之所欲材料。
選擇性原子層沉積製程110之製程條件如下：
在一個實施例中，前驅物氣體包括四乙基甲基胺基鉿(Tetrakisethylmethylaminohafnium；TEMAHf)：
Figure TWI611460BD00001
在此實施例中，製程溫度處於自約攝氏200度至約攝氏400度範圍內。蒸氣壓在攝氏70度下為約0.1托。氧化劑氣體可含有水(H2O)、氫氣+氧氣(H2+O2)或臭氧(O3)。結果是，形成氧化鉿作為用於蝕刻停止層100的材料。蝕刻停止層100之介電常數值為約18.5，其漏電流為約4×10-12安培，且電擊穿強度(electric breakdown strength；EBD)為約7.4毫伏特/公分。
在另一實施例中，前驅物氣體包括四(乙基甲基醯胺基)鋯(tetrakis(ethylmethylamido)zirconium；TEMA-Zr)：
Figure TWI611460BD00002
在此實施例中，製程溫度處於自約攝氏200度至約攝氏400度範圍內。蒸氣壓在攝氏70度下為約0.1托。氧化劑氣體可含有水(H2O)、氫氣+氧氣(H2+O2)或臭氧(O3)。結果是，形成氧化鋯作為用於蝕刻停止層100的材料。蝕刻停止層100之介電常數值為約20，漏電流為約1×10-12安培，且電擊穿強度(EBD)為約5.6毫伏特/公分。
在又一實施例中，前驅物氣體包括三甲基鋁(Trimethyl Aluminum；TMA)：
Figure TWI611460BD00003
在此實施例中，製程溫度處於自約攝氏200度至約攝氏400度範圍內。蒸氣壓在攝氏70度下為約100托。氧化劑氣體可含有水(H2O)、氫氣+氧氣(H2+O2)或臭氧(O3)。結果是，形成氧化鋁作為用於蝕刻停止層100的材料。蝕刻停止層100之介電常數值為約8.2，漏電流小於約1×10-12安培，且電擊穿強度(EBD)為約8.2毫伏特/公分。
在又一實施例中，前驅物氣體包括四(二甲基醯胺基)鋁(Tetrakis(dimethylamido)Aluminum；TDMAA)：
Figure TWI611460BD00004
在此實施例中，製程溫度處於自約攝氏200度至約攝氏400度範圍內。蒸氣壓在攝氏70度下為約0.2托。氧化劑氣體可含有水(H2O)、氫氣+氧氣(H2+O2)或臭氧(O3)。結果是，形成氧化鋁作為用於蝕刻停止層100的材料。蝕刻停止層100之介電常數值為約8.2，漏電流小於約1×10-12安培，且電擊穿強度(EBD)為約8.2毫伏特/公分。
如第2圖所圖示，形成蝕刻停止層100以與導電元件80具有相對共面的表面(亦即，數埃內或更少)。此可以兩種 方式中的一者完成。在一個實施例中，研磨製程90(第1圖所示)可經配置以使得介電層70具有比導電元件80低的上表面。換言之，介電層70可經「過度研磨」以形成「凹部」。可隨後形成蝕刻停止層100以藉由選擇性原子層沉積製程110填充此等「凹部」以便與導電元件80相對共面。在另一實施例中，在蝕刻製程中移除介電層70以形成「凹部」，隨後藉由選擇性原子層沉積製程110由蝕刻停止層100填充此等「凹部」。
蝕刻停止層100具有厚度120。在一些實施例中，厚度120處於自約2奈米至約5奈米範圍內。厚度範圍需經調控，因為若厚度太薄，則蝕刻停止層100可無法足以服務於稍後製程(下文更詳細地論述)中的蝕刻停止功能。另一方面，若厚度120太厚，則難以控制選擇性生長(亦即，生長在介電層70之表面上，但不生長在導電元件80之表面上)，且蝕刻停止層100之一些部分可能「溢出」導電元件80之表面。因此，2至5奈米之厚度範圍表示蝕刻停止層100的最佳厚度範圍。
現參看第3圖，在蝕刻停止層100上方及導電元件80上方形成另一蝕刻停止層130。蝕刻停止層130具有與蝕刻停止層100不同的材料組成。可藉由化學氣相沉積(chemical vapor deposition；CVD)製程形成蝕刻停止層130。在一些實施例中，蝕刻停止層130含有碳氧化矽(SiOC)或氮氧化矽(SiON)。亦形成蝕刻停止層130具有厚度140。在一些實施例中，厚度140約2奈米至約8奈米範圍內。在一些實施例中，厚度140約30奈米至約60奈米範圍內。厚度140經調控使得蝕刻 停止層130可足以作為下文所論述之後續蝕刻製程中的蝕刻停止層為目的。
仍參看第3圖，在蝕刻停止層130上方形成介電材料150。介電材料150可具有與介電層70類似的材料組成。舉例而言，介電材料150亦可含有上文所論述之低介電常數介電材料。介電層70與介電材料150兩者亦可稱為互連結構之層間介電質。
現參看第4圖，在介電材料150中形成導孔160及導電元件180。導電元件180亦稱為多層互連結構之MX+1互連層之金屬接線(導孔160可或可不視為MX+1互連層的一部分)。如第4圖所示，在導孔160上方形成導電元件180(且與導孔產生直接實體接觸)。導孔160與導電元件80至少部分地對準。如第4圖所示，形成導孔160延伸穿過蝕刻停止層130，並與導電元件80之一者產生直接實體接觸。以此方式，導孔160使導電元件80及180電互連在一起。換言之，導孔160使MX互連層及MX+1互連層之金屬接線電互連在一起。
在一些實施例中，使用雙鑲嵌製程形成導孔160及導電元件180。在其他實施例中，使用單鑲嵌製程形成導孔160及導電元件180。無論如何，用於形成導孔160的鑲嵌製程包括蝕刻製程。舉例而言，在第一蝕刻製程中，在介電材料150中蝕刻凹部或開口，同時蝕刻停止層130在本文中充當蝕刻停止層以防止下方的層被蝕刻。可將八氟環丁烷(C4F8)、四氟化碳(CF4)、氮(N2)、氬(Ar)用作蝕刻劑。此後，在另一蝕刻製程中「打開」蝕刻停止層130本身以便將凹部或開口向下延伸 至導電元件80。可將八氟環丁烷(C4F8)、六氟丁二烯(C4F6)、四氟化碳(CF4)或氮(N2)用作蝕刻劑。
傳統而言，不形成蝕刻停止層100。因此，用於打開蝕刻停止層130的蝕刻製程可不慎「穿通」蝕刻停止層130及引發下方的介電層70之多個部分亦被蝕刻。此後，當用導電材料填充經蝕刻之凹部或開口以形成導孔160時，導孔160的一部分將延伸至介電層70中，類似於「虎牙」。此虎牙效應在導孔160與導電元件80之間的不對準惡化時加劇。結果是，諸如可靠性(例如，藉由時間依賴型介電質擊穿(time-dependent dielectric breakdown；TDDB)量測)之裝置效能可遭受損害，及/或可因縫隙填充孔隙產生過度接觸電阻問題。
本揭露防止因形成蝕刻停止層100而對介電層70的過度蝕刻。蝕刻停止層100之材料組成經配置以在蝕刻製程期間相對於蝕刻停止層130具有高蝕刻選擇性(例如，大於1：100)以「打開」蝕刻停止層130。以此方式，儘管「打開」蝕刻停止層130，但幾乎未移除蝕刻停止層100之部分。因此，即使導孔160與導電元件80之間存在不對準，導孔160之部分將無法穿通介電層70(因為藉由蝕刻停止層100停止)而形成上文論述之「虎牙」。換言之，蝕刻停止層100上方與導電元件80偏移的導孔160之部分即為根據本揭露的一種態樣。
由於「虎牙」導孔穿通不再是問題，可放寬用形成導孔160的製程窗口，且亦可改良裝置效能。舉例而言，由於不對準將可能不會導致「虎牙」狀導孔穿通，可使得導孔160更大(例如，更寬的橫向尺寸)以確保導孔160與導電元件80之 間存在實體接觸。較大導孔尺寸可減小接觸電阻，還可在鑲嵌製程中放寬縫隙填充窗口。
第5圖至第9圖為本揭露之另一實施例在各製造階段之半導體裝置50的側視截面圖。出於清晰性及一致性原因，第1圖至第9圖中呈現的相似元件標記為相同，且下文不一定再重複此等元件之細節。
參看第5圖，提供基板60。在基板60上方形成包括介電層70及導電元件80的MX互連層。執行研磨製程90以平坦化MX互連層之表面。
現參看第6圖，形成複數個金屬封端層200。在各別導電元件80之上表面上形成每個金屬封端層200，但不形成於介電層70之表面上。在一些實施例中，藉由選擇性化學氣相沉積製程形成金屬封端層200。在本實施例中，金屬封端層200含有鈷，但在替代實施例中，可含有其他適宜金屬材料。金屬封端層200具有厚度220。在一些實施例中，厚度220約2奈米至約5奈米範圍內。
現參看第7圖，經由選擇性原子層沉積製程110形成蝕刻停止層100。選擇性原子層沉積製程110之細節與上文參看第2圖所論述的相同，且出於簡明性原因將在本文中不再重複。選擇性原子層沉積製程110在介電層70之表面上形成蝕刻停止層100(含有金屬氧化物材料)，但不形成於金屬封端層200之表面上。亦形成蝕刻停止層100以具有厚度120，此厚度與金屬封端層200之厚度220大致相同。換言之，蝕刻停止層100之厚度120亦約2奈米至約5奈米範圍內。如上文所論述， 厚度120的值經最佳配置使得不會太薄或太厚，因為若形成太薄，蝕刻停止層100不足以提供蝕刻停止功能，及若形成太厚，亦可難以控制層的選擇性生長(不欲形成於金屬封端層200上)。
現參看第8圖，在蝕刻停止層100上方及金屬封端層200上方形成另一蝕刻停止層130。再次，蝕刻停止層130具有與蝕刻停止層100不同的材料組成。舉例而言，蝕刻停止層130可含有碳氧化矽(SiOC)或氮氧化矽(SiON)，而蝕刻停止層100可含有氧化鉿、氧化鋯或氧化鋁。亦將蝕刻停止層130形成為約2奈米至約8奈米範圍內。在一些實施例中，蝕刻停止層130之厚度140約30奈米至約60奈米範圍內，此厚度允許蝕刻停止層130足以作為下文論述之後續蝕刻製程中的蝕刻停止層之用途。如第8圖所示，亦在蝕刻停止層130上方形成介電材料150。
現參看第9圖，在介電材料150中形成(MX+1互連層之)導孔160及導電元件180。導孔160與導電元件80至少部分地對準。亦形成導孔160延伸穿過蝕刻停止層130並與金屬封端層200之一者產生直接實體接觸。由於金屬封端層200為導電的，導孔160仍將導電元件80及180電互連在一起。而且，無論導孔160如何形成，將藉由蝕刻停止層100停止用於藉由「打開」蝕刻停止層130形成導孔的蝕刻製程。換言之，介電層70將不會因導孔160的形成而被不慎「穿通」。因此，出於與上文參看第4圖所論述的類似的原因，第9圖所示之實施例亦 避免「虎牙」問題及可提供更好的縫隙填充效能、放寬的製程窗口及改良的裝置效能。
第10圖至第14圖係根據本揭露之又一實施例在各製造階段之半導體裝置50之側視截面圖。出於清晰性及一致性原因，第1圖至第15圖中呈現的相似元件標記為相同，且下文不一定再重複此等元件之細節。
參看第10圖，提供基板60。在基板60上方形成包括介電層70及導電元件80的MX互連層。執行研磨製程以平坦化MX互連層之表面。在導電元件80之上表面上形成(例如，藉由選擇性化學氣相沉積製程)複數個金屬封端層200，但不形成於介電層70之表面上。形成金屬封端層200具有厚度220，此厚度處於自約2奈米至約5奈米範圍內。
現參看第11圖，經由選擇性原子層沉積製程310形成蝕刻停止層300。選擇性原子層沉積製程310之細節類似於上文參看第2圖所論述之選擇性原子層沉積製程110。然而，可執行額外循環以增加蝕刻停止層300之厚度。換言之，仍在介電層70之表面上形成蝕刻停止層300(含有金屬氧化物材料)，但不形成於金屬封端層200之表面上，但蝕刻停止層300具有厚度320，此厚度比金屬封端層200之厚度220厚。在一些實施例中，蝕刻停止層300之厚度320約6奈米至約10奈米範圍內。由於增加的厚度320，蝕刻停止層300及金屬封端層200形成凹部330。
現參看第12圖，在蝕刻停止層300上方及金屬封端層200上方形成硬遮罩層340，從而填充凹部330。藉由硬遮 罩沉積製程350形成硬遮罩層340。在一些實施例中，硬遮罩沉積製程350包括具有以下製程條件的旋塗介電質製程：
‧溶膠-凝膠：乙醇/矽氧烷寡聚物。
‧旋轉速度：1000-4000轉/分鐘(revolutions per minute；RPM)。
‧烘焙溫度：攝氏80度至攝氏350度。
‧紫外線(UV)固化：攝氏350度至攝氏400度，長達約60-120秒。
硬遮罩層340具有與蝕刻停止層300不同的材料組成。舉例而言，硬遮罩層340可含有氧化矽，而蝕刻停止層300可含有氧化鉿、氧化鋯或氧化鋁。亦將硬遮罩層340形成為比蝕刻停止層300厚至少數倍。在一些實施例中，硬遮罩層340之厚度360約20奈米至約40奈米範圍內。
現參看第13圖，執行研磨製程(諸如化學機械研磨製程)蝕刻掉硬遮罩層340的多個部分，直至硬遮罩層340與蝕刻停止層300具有共面表面。此後，在硬遮罩層340之表面上及蝕刻停止層300上形成介電材料150。
現參看第14圖，在介電材料150中形成(MX+1互連層之)導孔160及導電元件180。藉由執行蝕刻製程形成導孔160以在介電材料150中蝕刻開口，同時硬遮罩層340(以及蝕刻停止層300)充當蝕刻停止層。此後，在另一蝕刻製程中「打開」硬遮罩層340，同時蝕刻停止層300充當蝕刻停止層以防止介電層70因硬遮罩層340與蝕刻停止層300之間的高蝕刻選擇性(例如，>100：1)而被不慎過度蝕刻。或者，可執行單個蝕 刻製程以蝕刻介電材料150及配置在導電元件80上方的硬遮罩部分。只要蝕刻停止層300與硬遮罩層340/介電材料150之間存在足夠的蝕刻選擇性，蝕刻停止層300便可防止蝕刻下方的介電層70。
因此，在填充蝕刻開口後，配置在導電元件80之一者上方的硬遮罩層340的部分由導孔160之區段160B有效替換，而在介電材料150中配置導孔160之另一區段160A。而且，由於金屬封端層200為導電的，導孔160仍將導電元件80及180電互連在一起。以此方式，儘管步驟不同，但第10圖至第14圖所示之此實施例仍避免「虎牙」問題且可提供更好的縫隙填充效能，放寬的製程窗口，及更好的裝置效能。
第15圖係圖示根據本揭露之各態樣的製造半導體裝置之方法500的流程圖。將方法500之步驟中的一或更多者執行為5奈米技術世代或更小的半導體技術世代的製造製程的一部分。
方法500包括步驟510，在第一介電材料中形成第一導電元件。
方法500包括步驟520，經由選擇性原子層沉積(atomic layer deposition；ALD)製程在第一介電材料上形成第一蝕刻停止層，但不形成於第一導電元件上。
方法500包括步驟530，在第一蝕刻停止層上方形成第二蝕刻停止層。第二蝕刻停止層及第一蝕刻停止層具有不同材料組成。在一些實施例中，將第二蝕刻停止層形成為處於自約2奈米至約8奈米範圍內。舉例而言，第二蝕刻停止層可比 第一蝕刻停止層厚5倍至10倍。在一些實施例中，第一蝕刻停止層及第二蝕刻停止層之材料組成經配置以使得第一蝕刻停止層與第二蝕刻停止層具有實質上不同的蝕刻速率。換言之，高蝕刻選擇性(例如，大於100：1)存在於兩個蝕刻停止層之間。在一些實施例中，形成第一蝕刻停止層以含有氧化鉿、氧化鋯或氧化鋁。在一些實施例中，形成第二蝕刻停止層以含有碳氧化矽(SiOC)或氮氧化矽(SiON)。
方法500包括步驟540，在第二蝕刻停止層上方形成第二介電層。在一些實施例中，第一介電層與第二介電層兩者皆含有低介電常數介電材料。
方法500包括步驟550，經由一或更多個蝕刻製程在第二介電層中形成開口，其中開口延伸穿過第二蝕刻停止層，但不穿過第一蝕刻停止層，及其中使開口與第一導電元件至少部分地對準。
方法500包括步驟560，藉由填充開口在第一導電元件上方形成第二導電元件。
應理解，可在方法500之步驟510至560之前、期間或之後執行額外製程以完成半導體裝置之製造。舉例而言，第三導電元件位於第二導電元件上方。第一導電元件為互連結構之MX互連層之第一金屬接線。第三導電元件為互連結構之MX+1互連層之第二金屬接線。第二導電元件為將第一導電元件與第三導電元件互連在一起的導孔。出於簡明性原因，本文並未詳細論述額外製造步驟。
基於上文論述，可看出，本揭露提供優於形成導孔之習知方法及裝置的優勢。然而，應理解，其他實施例可提供額外優勢，且本文不一定揭示所有優勢，以及沒有特定優勢對於所有實施例為必需。如上文所論述，一個優勢是，藉由形成額外蝕刻停止層，本揭露可防止層間介電層之不慎過度蝕刻。因此，放寬對於導孔的上覆或對準需求。可使得此導孔更大，從而允許更好的縫隙填充效能以及減小接觸電阻。其他優勢是，本揭露不要求對現有製造方法作出許多改變。因此，並未顯著增加製造成本(若確實存在)。
本揭露之一實施例為一種半導體裝置。半導體裝置包括形成在基板上方的互連結構之第一層。第一層含有第一介電材料及配置在第一介電材料中的第一導電元件。半導體裝置包括第一蝕刻停止層，此第一蝕刻停止層配置在第一層之第一介電材料上，但不配置在第一層之第一導電元件上。半導體裝置包括配置在第一層上方的第二導電元件。將第二導電元件與第一導電元件至少部分地對準並電耦接至第一導電元件。
本揭露之另一實施例為一種半導體裝置。半導體裝置包括配置在基板上方的互連結構之MX互連層。MX互連層含有第一介電材料及配置在第一介電材料中的複數個第一金屬接線。半導體裝置包括第一蝕刻停止層，此第一蝕刻停止層配置在第一介電材料上，但不配置在第一金屬接線上。第一蝕刻停止層含有氧化鉿、氧化鋯或氧化鋁。半導體裝置包括配置在第一蝕刻停止層上方的第二蝕刻停止層，其中第二蝕刻停止層含有碳氧化矽或氮氧化矽。半導體裝置包括配置在MX互連 層上方的互連結構之MX+1互連層。MX+1互連層含有第二介電材料及配置在第二介電材料中的第二金屬接線。半導體裝置包括導孔，此導孔將第一金屬接線之至少一者與第二金屬接線電互連。導孔延伸穿過第二蝕刻停止層，但不穿過第一蝕刻停止層。
本揭露之又一實施例為一種製造半導體裝置的方法。在第一介電材料中形成第一導電元件。經由選擇性原子層沉積製程，在第一介電材料上形成第一蝕刻停止層，但不形成於第一導電元件上。在第一導電元件上方形成第二導電元件。將第二導電元件形成為與第一導電元件至少部分地對準並電耦接至第一導電元件。
前文概述了數個實施例之特徵，使得熟習此項技藝者可更好地理解隨後的詳細描述。熟習此項技藝者應瞭解，可易於使用本揭露作為設計或修改其他製程及結構的基礎以便實施本文所介紹的實施例之相同目的及/或實現相同優勢。熟習此項技藝者亦應認識到，此類等效結構並未脫離本揭露之精神及範疇，並且可在不脫離本揭露之精神及範疇的情況下在本文中實施各種變化、取代及修改。
50‧‧‧半導體裝置
60‧‧‧基板
70‧‧‧介電層
80‧‧‧導電元件
100‧‧‧蝕刻停止層
130‧‧‧蝕刻停止層
140‧‧‧厚度
150‧‧‧介電材料
160‧‧‧導孔
180‧‧‧導電元件

Claims (8)

  1. 一種半導體裝置，包含：形成在一基板上方之一互連結構之一第一層，其中該第一層含有一第一介電材料及配置在該第一介電材料中的一第一導電元件；一第一蝕刻停止層，該第一蝕刻停止層配置在該第一層之該第一介電材料上，但不配置在該第一層之該第一導電元件上；配置在該第一層上方的一第二導電元件，其中該第二導電元件與該第一導電元件至少部分地對準並電耦接至該第一導電元件；配置在該第一蝕刻停止層上方及該第一層上方的一第二蝕刻停止層，其中該第二導電元件延伸穿過該第二蝕刻停止層；以及配置在該第二蝕刻停止層上方的該互連結構之一第二層，其中該第二層包含一第二介電材料及配置在該第二介電材料中的一第三導電元件，其中該第三導電元件經配置在該第二導電元件上方並電耦接至該第二導電元件。
  2. 如請求項1所述之半導體裝置，其中：該第一層為該互連結構之一MX互連層；該第二層為該互連結構之一MX+1互連層；該第一導電元件為該MX互連層之一第一金屬接線； 該第三導電元件為該MX+1互連層之一第二金屬接線；以及該第二導電元件為將該第一導電元件與該第三導電元件互連在一起的一導孔。
  3. 一種半導體裝置，包含：配置在一基板上方的一互連結構之一MX互連層，其中該MX互連層含有一第一介電材料及配置在該第一介電材料中的複數個第一金屬接線；一第一蝕刻停止層，該第一蝕刻停止層配置在該第一介電材料上，但不配置在該些第一金屬接線上，其中該第一蝕刻停止層含有氧化鉿、氧化鋯或氧化鋁；配置在該第一蝕刻停止層上方的一第二蝕刻停止層，其中該第二蝕刻停止層含有碳氧化矽或氮氧化矽；配置在該MX互連層上方的該互連結構之一MX+1互連層，其中該MX+1互連層含有一第二介電材料及配置在該第二介電材料中的一第二金屬接線；以及一導孔，該導孔將該些第一金屬接線之至少一者與該第二金屬接線電互連，其中該導孔延伸穿過該第二蝕刻停止層，但不穿過該第一蝕刻停止層。
  4. 如請求項3所述之半導體裝置，更包含一金屬封端層，該金屬封端層經配置在該些第一金屬接線之各者上，但不配置在該第一介電材料上。
  5. 一種製造一半導體裝置的方法，該方法包含以下步驟：在一第一介電材料中形成一第一導電元件；經由一選擇性原子層沉積製程，在該第一介電材料上形成一第一蝕刻停止層，但不形成於該第一導電元件上，在該第一蝕刻停止層上方形成一第二蝕刻停止層，其中該第二蝕刻停止層與該第一蝕刻停止層具有不同材料組成；在該第二蝕刻停止層上方形成一第二介電層；經由一或更多個蝕刻製程在該第二介電層中形成一開口，其中該開口延伸穿過該第二蝕刻停止層，但不穿過該第一蝕刻停止層，其中該開口與該第一導電元件至少部分地對準；以及在該第一導電元件上方形成一第二導電元件，其中將該第二導電元件形成為與該第一導電元件至少部分地對準並電耦接至該第一導電元件。
  6. 如請求項5所述之方法，更包含在該第二導電元件上方形成一第三導電元件，其中：藉由用一導電材料填充該開口來形成該第二導電元件及該第三導電元件；該第一導電元件為一互連結構之一MX互連層之一第一金屬接線；該第三導電元件為該互連結構之一MX+1互連層之一第二金屬接線；以及 該第二導電元件為將該第一導電元件與該第三導電元件互連在一起的一導孔。
  7. 如請求項5所述之方法，其中：該第一導電元件之該形成步驟包含以下步驟：形成複數個額外第一導電元件，其中該些額外第一導電元件透過該第一介電材料與該第一導電元件分離；以及更包含在該些第一導電元件上分別形成複數個金屬封端層，但不形成於該第一介電材料上。
  8. 如請求項7所述之方法，其中將該第一蝕刻停止層形成為比該些金屬封端層厚；且更包含分別在該些金屬封端層上形成複數個硬遮罩元件，該些硬遮罩元件與該第一蝕刻停止層具有不同材料組成。
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