TWI596728B - 具有單列直插引線模塊的半導體功率器件及其製備方法 - Google Patents

具有單列直插引線模塊的半導體功率器件及其製備方法 Download PDF

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TWI596728B
TWI596728B TW105130534A TW105130534A TWI596728B TW I596728 B TWI596728 B TW I596728B TW 105130534 A TW105130534 A TW 105130534A TW 105130534 A TW105130534 A TW 105130534A TW I596728 B TWI596728 B TW I596728B
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lead
sets
top surface
clip
row
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TW105130534A
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TW201801273A (zh
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彥迅 薛
牛志強
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萬國半導體股份有限公司
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Description

具有單列直插引線模塊的半導體功率器件及其製備方法
本發明主要涉及一種半導體功率器件。更確切地說，本發明是關於具有單列直插引線模組的半導體功率器件及其製備方法。
一種電子設備，例如功率工具，可能包含多種功率器件。通常來說，那些多種功率器件的金屬-氧化物半導體場效應電晶體（MOSFET）晶片，是在多種不同的封裝中製備和組裝的。MOSFET晶片並排放置。必須在鄰近的MOSFET晶片之間，預置縫隙寬度，以便增大熱耗散。每個封裝都需要一個單獨的拾取和放置過程。在板級安裝步驟中，空間效率和時間效率都不高。板級互連產生過量的阻抗。
本發明提出了一種具有半導體晶片堆疊的半導體功率器件。每個晶片堆疊都包含一個高端MOSFET晶片、一個低端MOSFET晶片以及一個將高端MOSFET晶片源極墊連接到低端MOSFET晶片漏極墊的晶片。在一個示例中，在主功率電路（例如N-通道模組的MOSFET晶片的源極電路或漏極電路）中使用晶片互連。在另一個示例中，晶片的頂面從密封包裝中裸露出來，引線框的底面從密封包裝中裸露出來。這減少了拾取和放置過程的數量。在板級安裝步驟中，空間效率和時間效率都更高。
本發明提出了一種含有一個引線框單元、兩組或更多組單列直插引線組、兩個或多個半導體晶片堆疊以及一個成型封裝。每個半導體晶片堆疊都包括一個高端半導體晶片、一個低端半導體晶片以及一個將高端MOSFET晶片頂面連接到低端MOSFET晶片底面的夾片。
本發明還提出了一種製備半導體功率器件的方法。該方法包括製備具有多個引線框單元的引線框帶；為每個引線框單元製備兩組或更多組單列直插引線組；將兩個或多個高端半導體晶片連接到每個引線框單元；將兩個或多個高端半導體晶片都通過兩個或多個第一夾片，分別連接到各自引線；將兩個或多個低端半導體晶片分別連接到對應的兩個或多個第一夾片的每個夾片上；使封裝成型；並且分割引線框帶和密封包裝，製成半導體功率器件。
圖1表示在本發明的示例中，製備半導體功率器件的工藝100的流程圖。工藝100可以在組塊102中開始。
在組塊102中，製備圖2A所示的引線框帶200，具有多個引線框單元202和204（圖中表示出了兩個引線框單元）。
圖3A所示的兩組或更多組單列直插引線組360A、360B和360C（表示出了三組多個單列直插引線），在圖3A所示的引線框單元302的一側附近。多個單列直插引線360A包括一個源極引線362（第一引線）。多個單列直插引線360B包括一個源極引線364。多個線上引線360C包括一個源極引線366。引線框單元302與圖2A所示的引線框單元202類似。每個引線框單元都配備相同的兩組或更多組單列直插引線組。在組塊116的分割步驟中將要除去的那部分引線框單元302，沒有在圖3A中表示出來。組塊102之後可以進行組塊104。
在組塊104中，圖3A所示的兩個或多個高端半導體晶片312、314和316（表示出了三個高端半導體晶片），通過第一層導電接合材料，連接到引線框單元302上。在本發明的示例中，導電接合材料為焊膏、環氧樹脂或銀燒結材料。圖3A所示的源極墊322、324和326以及圖3A所示的柵極墊332、334和336分別在高端半導體晶片312、314和316的頂面上。漏極墊分別在高端半導體晶片312、314和316的底面上。組塊104之後可以進行組塊106。
在組塊106中，每個高端半導體晶片312、314和316都通過第一夾片442、444和446，分別連接到對應的兩組或更多組單列直插引線組360A、360B和360C的各自的源極引線362、364或366（第一引線）上。夾片442具有第一端452、橋接結構456和第二端454。橋接結構456將第一端452連接到第二端454。第一端452的底面通過第二層導電接合材料，連接到高端半導體晶片312的頂面。在本發明的示例中，高端半導體晶片312的源極墊322電連接到夾片442，並與之機械接觸。第二端454的底面通過第三層導電接合材料，連接到源極引線362的頂面。高端半導體晶片312的頂面區域472沒有被夾片442覆蓋。因此，柵極墊332易於在組塊112的引線接合步驟中接近。與之類似，高端半導體晶片314的頂面區域474沒有被夾片444覆蓋，高端半導體晶片316的頂面區域476沒有被夾片446覆蓋。組塊106之後可以進行組塊108。
在組塊108中，圖5A所示的兩個或多個低端半導體晶片512、514和516（表示出了三個低端半導體晶片），都通過第四層導電接合材料，分別連接到對應的第一夾片442、444和446。圖5A所示的源極墊522、524和526以及圖5A所示的柵極墊532、534和536分別在低端半導體晶片512、514和516的頂面上。漏極墊分別位於低端半導體晶片512、514和516的底面上。在本發明的示例中，低端半導體晶片512的漏極通過夾片442的第一端452，電連接到高端半導體晶片312的源極墊322，並與之機械接觸。由於低端半導體晶片的漏極也通過第一夾片連接到相位節引線，因此源極引線362、364和366也稱為相位節引線。在本實施例中，兩組或更多組單列直插引線組360A、360B和360C都包括一個相互隔開的相位節引線。還可選擇，將連接到高端半導體晶片和低端半導體晶片堆疊的每個相位節引線連接在一起，或共用一個公共相位節引線（圖中沒有表示出）。組塊108之後可以進行組塊110。
在組塊110，兩個或多個低端半導體晶片512、514和516的每個半導體晶片的源極墊522、524或526都接地。在本發明的示例中，低端半導體晶片512、514和516的每個源極墊522、524或526都通過第二夾片642、644和646，分別連接到對應的兩組或更多組單列直插引線組360A、360B和360C各自的接地引線662、664或666（第二引線）。夾片642具有第一端652、橋接結構656和第二端654。橋接結構656將第一端652連接到第二端654。第一端652的底面通過第五層導電接合材料，連接到低端半導體晶片512的頂面。在本發明的示例中，低端半導體晶片512的源極墊電連接到夾片642，並與之機械接觸。第二端654的底面通過第六層導電接合材料，連接到接地引線662的頂面。
在本發明的示例中，圖8A所示的連接夾片842將低端半導體晶片512、514和516頂面上的源極墊522、524或526連接到兩組或更多組單列直插引線組360A、360B和360C的圖8A所示的接地引線898。連接夾片842具有第一部分852連接到低端半導體晶片512、第二部分854連接到低端半導體晶片514以及第三部分856連接到低端半導體晶片516。連接元件862將第一部分852連接到第二部分854。連接元件864將第二部分854連接到第三部分856。
在本發明的示例中，圖9所示的接合引線982、984或986將兩個或多個低端半導體晶片512、514和516的每個頂面上源極墊522、524或526都連接到兩組或更多組單列直插引線組各自的接地引線962、964或966（第二引線）。
在本發明的示例中，圖10所示的引線1062將低端半導體晶片512的源極墊522連接到低端半導體晶片514的源極墊524。圖10所示的引線1064將低端半導體晶片514的源極墊524連接到低端半導體晶片516的源極墊526。圖10所示的引線1096將低端半導體晶片516的源極墊526連接到接地引線1098。組塊110之後可以進行組塊112。
在組塊112中，使用引線接合。圖6A所示的第一接合引線692、694或696，將所述的兩個或多個高端半導體晶片312、314和316的柵極墊332、334和336分別連接到對應的兩組或更多組單列直插引線組360A、360B和360C的各自的第三引線。第二接合引線682、684或686將所述的兩個或多個低端半導體晶片512、514和516的柵極墊532、534或536分別連接到對應的兩組或更多組單列直插引線組360A、360B和360C的各自的第四引線。可以替換接合引線682、684、686、692、694和696。在一個示例中，可以用夾片黏貼代替引線接合方法。引線接合方法有利於降低成本。當電流要求很重要時，最好使用夾片黏貼。組塊112之後可以進行組塊114。
在組塊114中，成型圖7A所示的封裝體722，覆蓋圖2A所示的引線框帶200，連接到圖3A所示的每個引線框單元302之上的兩個或多個高端半導體晶片312、314和316，圖4A所示的兩個或多個第一夾片442、444和446以及兩個或多個低端半導體晶片512、514和516。
在本發明的示例中，兩個或多個第二夾片642、644和646的至少一大部分各自夾片都嵌入在圖7A和7B所示的封裝722體中。在一個示例中，第二夾片整體嵌入在封裝體722中。在兩個示例中，圖7C和圖7D所示第二夾片742的圖7D頂面752從封裝體722中裸露出來。在本發明的示例中，橋接結構具有圖7D所示的凹槽762。橋接結構將第二夾片742的第一端連接到第二夾片742的第二端。在一個示例中，引線框單元整體嵌入在封裝體722中。在另一個示例中，引線框單元302的圖7D所示底面702從封裝體722中裸露出來。在本發明的示例中，製備半圓形切口792和794以方便用螺釘固定。
在一個示例中，連接夾片842整體嵌入在封裝中。在另一個示例中，如圖8C和8D所示，第一部分852、第二部分854和第三部分856的頂面從封裝體822中裸露出來。在圖8D中，第一部分858的頂面從封裝體822中裸露出來。組塊114之後可以進行組塊116。
在組塊116中，分割引線框帶200和封裝體722，製成半導體功率器件。在本發明的示例中，每個半導體功率器件包括兩個或多個相同的半導體晶片堆疊，封裝體充滿半導體晶片堆疊之間的空隙。在一個示例中，晶片堆疊包括安裝在引線框單元302之上的高端半導體晶片312、第一夾片442以及低端半導體晶片512。晶片堆疊還包括第二夾片642。在本發明的示例中，兩個或多個第一夾片442、444和446、兩個或多個第二夾片642、644和646以及連接夾片842都是由導電金屬材料製成。在一個示例中，導電金屬材料材料為銅。在另一個示例中，導電金屬材料為鎳。
本領域的技術人員將理解所述實施例可能存在修正。例如，夾片的第一和第二端的高度可以變化。本領域的技術人員可能還有其他修正，這些修正都被視為屬於本發明的範圍內，由權利要求書限定。
100‧‧‧工藝
102,104,106,108,110,112,114,116‧‧‧組塊
200‧‧‧引線框帶
202,204‧‧‧線框單元
302‧‧‧引線框單元
312,314,316‧‧‧高端半導體晶片
322,324,326‧‧‧源極墊
332,334,336‧‧‧柵極墊
360A,360B,360C‧‧‧單列直插引線組
362,364,366‧‧‧源極引線
442,444,446‧‧‧夾片
452‧‧‧第一端
454‧‧‧第二端
456‧‧‧橋接結構
472,474,476‧‧‧頂面區域
512,514,516‧‧‧低端半導體晶片
522,524,526‧‧‧源極墊
532,534,536‧‧‧柵極墊
642,644,646‧‧‧夾片
652‧‧‧第一端
654‧‧‧第二端
656‧‧‧橋接結構
662,664,666‧‧‧接地引線
682,684,686‧‧‧接合引線
692,694,696‧‧‧接合引線
702‧‧‧底面
722‧‧‧封裝體
742‧‧‧夾片
752‧‧‧頂面
762‧‧‧凹槽
792,794‧‧‧切口
822‧‧‧封裝體
842‧‧‧夾片
852‧‧‧第一部分
854‧‧‧第二部分
856‧‧‧第三部分
858‧‧‧第一部分
862,864‧‧‧連接元件
898‧‧‧接地引線
962,964,966‧‧‧接地引線
982,984,986‧‧‧接合引線
1062,1064‧‧‧引線
1096,1098‧‧‧引線
圖1表示在本發明的示例中，製備半導體功率器件的工藝流程圖； 圖2A表示在本發明的示例中，引線框帶的AA平面的俯視圖，圖2B為垂直於AA平面的剖面圖； 圖3A、4A、5A、6A、7A和7C表示一系列剖面圖，圖3B、4B、5B、6B、7B和7D表示垂直於BB、CC、DD、EE、FF和GG平面的一系列剖面圖，分別表示製備半導體功率器件的各種工藝步驟； 圖8A表示在本發明的示例中，半導體功率器件的HH平面的俯視圖，圖8B表示垂直於HH平面的剖面圖； 圖8C表示在本發明的示例中，半導體功率器件的II平面的俯視圖，圖8D表示垂直於II平面的剖面圖； 圖9表示在本發明的示例中，半導體功率器件的俯視圖； 圖10表示在本發明的示例中，半導體功率器件的俯視圖。
100‧‧‧工藝
102,104,106,108,110,112,114,116‧‧‧組塊

Claims (15)

  1. 一種半導體功率器件包括： 一個引線框單元，具有頂面，以及與頂面相對的底面； 兩組或更多組單列直插引線組，位於引線框單元側邊附近排成一列，每組單列直插引線組包括多數個單列直插引線； 兩個或多個半導體晶片堆疊，每個半導體晶片堆疊都包括： 一個具有頂面和底面的高端半導體晶片，高端半導體晶片的底面通過第一層導電接合材料，連接到引線框單元的頂面； 一個具有第一端和第二端的第一夾片，第一夾片的第一端的底面通過第二層導電接合材料，連接到高端半導體晶片頂面上的源極墊，第一夾片的第二端底面通過第三層導電接合材料，連接到兩組或更多組單列直插引線組中對應的一組單列直插引線組中的第一引線的頂面；以及 一個具有頂面和底面的低端半導體晶片，低端半導體晶片的底面通過第四層導電接合材料，連接到第一夾片第一端的頂面；以及 成型封裝； 其中所述的兩個或多個半導體晶片堆疊中的每個低端半導體晶片的頂面上的源極墊都接地；並且 其中所述的兩個或多個半導體晶片堆疊中的每個高端和低端半導體晶片和第一夾片，以及至少部分引線框單元都嵌入在成型封裝中。
  2. 如申請專利範圍第1項所述的半導體功率器件，其中所述的兩個或多個半導體晶片堆疊的每個堆疊都包括： 一個具有第一端和第二端的第二夾片，第二夾片第一端的底面通過第五層導電接合材料，連接到低端半導體晶片頂面上的源極墊，第二夾片第二端的底面通過第六層導電接合材料，連接到兩組或更多組單列直插引線組中對應的單列直插引線組中的第二引線頂面； 其中第二引線為接地引線；並且 其中至少部分第二夾片嵌入在成型封裝中。
  3. 如申請專利範圍第2項所述的半導體功率器件，其中第一接合引線將高端半導體晶片的柵極墊連接到兩組或更多組單列直插引線組中對應的單列直插引線組中的第三引線；並且 其中第二接合引線將低端半導體晶片的柵極墊連接到兩組或更多組單列直插引線組中對應的單列直插引線組中的第四引線。
  4. 如申請專利範圍第2項所述的半導體功率器件，其中引線框單元的底面從成型封裝中裸露出來。
  5. 如申請專利範圍第2項所述的半導體功率器件，其中第二夾片的頂面從成型封裝中裸露出來。
  6. 如申請專利範圍第2項所述的半導體功率器件，其中橋接結構將第二夾片的第一端連接到第二夾片的第二端；並且 其中橋接結構具有一個凹槽。
  7. 如申請專利範圍第1項所述的半導體功率器件，包括一個連接夾片，將兩個或多個半導體晶片堆疊的每個低端半導體晶片頂面上的源極墊都連接到兩個或多個單列直插引線組中的接地引線。
  8. 如申請專利範圍第7項所述的半導體功率器件，其中連接夾片的頂面從成型封裝中裸露出來。
  9. 一種用於製備半導體功率器件的方法，該方法包括以下步驟： 製備一個具有多個引線框單元的引線框帶； 在每個引線框單元側邊附近製備兩組或更多組單列直插引線組，所述的兩組或更多組單列直插引線組排列成行，每組單列直插引線組包括多數個單列直插引線； 將兩個或多個高端半導體晶片的底面，通過第一層導電接合材料，連接到所述的每個引線框單元的頂面； 將兩個或多個第一夾片的第一端的底面分別連接到對應的兩個或多個高端半導體晶片的頂面，將兩個或多個第一夾片的第二端的底面分別連接到對應的兩組或更多組單列直插引線組中的第一引線頂面； 將兩個或多個低端半導體晶片的底面，分別連接到對應的所述兩個或多個第一夾片的第一端； 將兩個或多個低端半導體晶片的每個頂面上的源極墊電連接到接地端； 封裝成型，覆蓋引線框帶的頂面，所述兩個或多個高端半導體晶片連接到所述的每個引線框單元，兩個或多個第一夾片分別連接到對應的兩個或多個高端半導體晶片，兩個或多個低端半導體晶片分別連接到對應的兩個或多個第一夾片；並且 分割引線框帶和封裝，製成半導體功率器件； 其中每個半導體功率器件都具有兩個或多個高端半導體晶片。
  10. 如申請專利範圍第9項所述的用於製備半導體功率器件的方法，其中將兩個或多個低端半導體晶片的每個頂面上的源極墊電連接到接地端包括以下子步驟： 將兩個或多個第二夾片的第一端的底面分別連接到對應的兩個或多個低端半導體晶片頂面上的源極墊，將兩個或多個第二夾片的第二端的底面分別連接到對應的兩組或更多組單列直插引線組中的第二引線的頂面； 其中兩組或更多組單列直插引線組中的第二引線為接地引線；並且 其中至少部分的兩個或多個第二夾片的各自夾片嵌入在封裝中。
  11. 如申請專利範圍第10項所述的用於製備半導體功率器件的方法，其中兩個或多個第一接合引線將兩個或多個高端半導體晶片中所述的每個晶片的柵極墊都分別連接到對應的兩組或更多組單列直插引線組中的第三引線；並且 其中第二接合引線將兩個或多個低端半導體晶片中所述的每個晶片的柵極墊都分別連接到對應的兩組或更多組單列直插引線組中的第四引線。
  12. 如申請專利範圍第10項所述的用於製備半導體功率器件的方法，其中多個引線框單元的底面都從封裝中裸露出來。
  13. 如申請專利範圍第10項所述的用於製備半導體功率器件的方法，其中兩個或多個第二夾片的頂面都從封裝中裸露出來。
  14. 如申請專利範圍第9項所述的用於製備半導體功率器件的方法，其中將兩個或多個低端半導體晶片的每個頂面上的源極墊電連接到接地端，並與之機械接觸包括以下子步驟： 將兩個或多個低端半導體晶片中所述的每個晶片頂面上的源極墊用一連接夾片連接到兩組或更多組單列直插引線組的接地引線。
  15. 一種半導體功率器件包括： 一個引線框單元，具有頂面以及與頂面相對的底面； 兩組或更多組單列直插引線組，在引線框單元側面附近排列成行； 兩個或多個半導體晶片堆疊，每個堆疊包括： 一個具有頂面和底面的高端半導體晶片，高端半導體晶片的底面 通過第一層導電接合材料，連接到引線框單元的頂面； 一個具有第一端和第二端的第一夾片，第一夾片第一端的底面通過第二層導電接合材料，連接到高端半導體晶片頂面上的源極墊，第一夾片第二端的底面通過第三層導電接合材料，連接到相位節引線的頂面；以及 一個具有頂面和底面的低端半導體晶片，低端半導體晶片的底面通過第四層導電接合材料，連接到第一夾片第一端的頂面；以及 一個成型封裝； 其中兩個或多個半導體晶片堆疊中所述的每個堆疊的低端半導體晶片頂面上的源極墊都電連接到接地端；並且 其中兩個或多個半導體晶片堆疊中所述的每個堆疊的高端、低端半導體晶片和第一夾片，以及至少部分的引線框單元都嵌入在成型封裝中。
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