TWI532143B - 半導體組件及其製造方法 - Google Patents

半導體組件及其製造方法 Download PDF

Info

Publication number
TWI532143B
TWI532143B TW100121480A TW100121480A TWI532143B TW I532143 B TWI532143 B TW I532143B TW 100121480 A TW100121480 A TW 100121480A TW 100121480 A TW100121480 A TW 100121480A TW I532143 B TWI532143 B TW I532143B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
electrical connector
semiconductor
bonding
pad
Prior art date
Application number
TW100121480A
Other languages
English (en)
Other versions
TW201212200A (en
Inventor
舒泰許 克里斯南
王順偉
Original Assignee
半導體組件工業公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 半導體組件工業公司 filed Critical 半導體組件工業公司
Publication of TW201212200A publication Critical patent/TW201212200A/zh
Application granted granted Critical
Publication of TWI532143B publication Critical patent/TWI532143B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L24/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L24/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/0601Structure
    • H01L2224/0603Bonding areas having different sizes, e.g. different heights or widths
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0618Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/06181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37117Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/37124Aluminium [Al] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/37001Core members of the connector
    • H01L2224/37099Material
    • H01L2224/371Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/37138Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/37147Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/36Structure, shape, material or disposition of the strap connectors prior to the connecting process
    • H01L2224/37Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
    • H01L2224/3754Coating
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/4005Shape
    • H01L2224/4009Loop shape
    • H01L2224/40095Kinked
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/40Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
    • H01L2224/401Disposition
    • H01L2224/40151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/40221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/40225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/40227Connecting the strap to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/34Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
    • H01L2224/39Structure, shape, material or disposition of the strap connectors after the connecting process
    • H01L2224/41Structure, shape, material or disposition of the strap connectors after the connecting process of a plurality of strap connectors
    • H01L2224/4101Structure
    • H01L2224/4103Connectors having different sizes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73221Strap and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73263Layer and strap connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838Bonding techniques
    • H01L2224/83801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/84Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
    • H01L2224/848Bonding techniques
    • H01L2224/84801Soldering or alloying
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/13Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304Transistor
    • H01L2924/1306Field-effect transistor [FET]
    • H01L2924/13091Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10Details of semiconductor or other solid state devices to be connected
    • H01L2924/11Device type
    • H01L2924/14Integrated circuits
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/156Material
    • H01L2924/15786Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787Ceramics, e.g. crystalline carbides, nitrides or oxides
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181Encapsulation

Description

半導體組件及其製造方法
本發明大體上係關於電子器件,且更特定言之係關於半導體晶粒封裝及用於封裝半導體晶粒之方法。
在過去,半導體工業使用各種封裝組態以增加一系統中的半導體晶粒之封裝密度。對於電子裝置之所增加需求增加了更小、更輕且又更多功能的半導體裝置之需求且導致具有增加的半導體封裝密度與更小的輪廓及安裝覆蓋區之半導體封裝之一需求。在一些實施例中,半導體晶粒以附接至該半導體晶粒之黏著劑之一插入層垂直堆疊於彼此之頂部上以將該半導體晶粒耦合在一起。晶粒附接至一玻璃環氧類型印刷電路板基板或其他類似基板。接著該半導體晶粒線接合至該基板以在該基板與該半導體晶粒之間形成電互連。此一封裝組態之一實例係揭示於在2003年11月18日頒予Thomas B. Glenn等人之美國專利第6,650,019號中。具有經堆疊積體電路晶粒之一電子總成之另一實例係揭示於在2006年4月18日頒予Todd P. Oman之美國專利第7,030,317號中。
因此,具有一半導體組件及堆疊半導體晶粒以製造該半導體組件而沒有增加該半導體組件之覆蓋區之方法係有利的。其將進一步有利於具有成本效益及時間效應而實施該半導體組件及方法。
在一實施例中,一半導體組件包括具有一組件承接區域及複數個接合墊之一基板;具有第一表面及第二表面之一第一半導體晶片,該第一半導體晶片之該第一表面耦合至該組件承接區域;具有第一端及第二端之一第一電連接器,該第一端鄰近於該第一半導體晶片之該第二表面;具有第一表面及第二表面之一第二半導體晶片,該第二半導體晶片之該第一表面耦合至該第一電連接器之該第一端,其中該第一導電體之該第一端係定位於該第一半導體晶片與該第二半導體晶片之間;具有第一端及第二端之一第二電連接器,該第二電連接器之該第一端鄰近於該第二半導體晶片之該第二表面;及具有第一表面及第二表面之一第三半導體晶片,該第三半導體晶片之該第一表面耦合至該第二電連接器之該第一端,其中該第二電連接器之該第一端係在該第二半導體晶片與該第三半導體晶片之間。
在另一實施例中,一半導體組件包括具有一晶片承接區域及複數個接合墊之一基板;耦合至該晶片承接區域之一第一半導體晶片,該第一半導體晶片具有第一表面及第二表面,其中該第二表面包含一閘極接點及一源極接點;一第一電連接器,其耦合於該第一半導體晶片之該第二表面與該複數個接合墊之一第一接合墊之間;耦合至該第一電連接器之一第二半導體晶片,該第二半導體晶片具有第一表面及第二表面,其中該第二半導體晶片之該第二表面包含一閘極接點及一源極接點;及一第二電連接器,其耦合於該第一半導體晶片之該閘極接點與該複數個接合墊之一第一接合墊之間,及一第三電連接器,其耦合於該源極接點及該第一電連接器之間。
在另一實施例中,一種用於製造一半導體組件之方法包括提供具有一組件承接區域及複數個接合墊之一支撐結構;將一第一半導體晶片耦合至該支撐結構之該組件承接區域,該第一半導體晶片具有第一接合墊及第二接合墊;將該第一半導體晶片之該第一接合墊電耦合至該複數個接合墊之一第一接合墊且將該第一半導體晶片之該第二接合墊電耦合至該複數個接合墊之至少一第二接合墊;以一第一電連接器將該第一半導體晶片耦合至該複數個接合墊之一第三接合墊;將一第二半導體晶片耦合至該第一電連接器,該第二半導體晶片具有一第一接合墊及一第二接合墊;及將該第二半導體晶片之該第一接合墊電耦合至該複數個接合墊之一第四接合墊,將該第二半導體晶片之該第二接合墊電耦合至該複數個接合墊之至少一第五接合墊,及以一第二電連接器將該第二半導體晶片耦合至該複數個接合墊之一第六接合墊。
將從結合附圖閱讀以下詳細描述而更好地理解本發明,其中相同參考符號指明相同元件。
一般而言,本發明提供一種半導體組件及一種用於製造該半導體組件之方法。根據本發明之實施例,一半導體組件包括具有一組件承接區域及複數個接合墊之一基板。一半導體晶片48係附接至該組件承接區域18。具有若干端或接觸區帶64及68之一電連接器62係耦合至半導體晶片48及基板12。一半導體晶片78係安裝或附接至電連接器62之端64使得端64係定位於半導體晶片48與半導體晶片78之間。具有若干端或接觸區帶94及98之一電連接器92係耦合至半導體晶片78與基板12。一半導體晶片118係安裝於端94之上或附接至端94使得端94係在半導體晶片78與半導體晶片118之間。
圖1係根據本發明之實施例之在製造之一早期階段之一半導體組件10之一部分之一俯視圖。圖1中展示一支撐結構12,例如,諸如一印刷電路板,其具有一表面14、一組件承接區域18、形成於組件承接區域18的一部分之一組件接觸結構19、若干接合墊組20、22、24及26、若干接合墊組28、30、32及34及接合墊36、38、40及42。接合墊組20包括接合墊20G及接合墊20S;接合墊組22包括接合墊22G及接合墊22S;接合墊組24包括接合墊24G及接合墊24S;且接合墊組26包括接合墊26G及接合墊26S。同樣地,接合墊組28包括接合墊28G及接合墊28S;接合墊組30包括接合墊30G及接合墊30S;接合墊組32包括接合墊32G及接合墊32S;且接合墊組34包括接合墊34G及接合墊34S。此外,在接合墊組20與28之間形成接合墊36,在接合墊組22與30之間形成接合墊38,在接合墊組24與32之間形成接合墊40,且在接合墊組26與34之間形成接合墊42。舉例而言,接合墊20G、22G、24G、26G、28G、30G、32G及34G充當用於閘極電極之接合墊且可稱為閘極接合墊或閘極墊;接合墊20S、22S、24S、26S、28S、30S、32S及34S充當用於源極電極之接合墊且可稱為源極接合墊或源極墊;且接合墊36、38、40及42充當用於汲極電極之接合墊且可稱為汲極接合墊或汲極墊。應注意,基板12具有相對主表面14及16,其中表面16展示於圖3中。
組件接觸結構19、接合墊組20、22、24、26、28、30、32及34及接合墊36、38、40及42可由包含一層或多層之一導電材料之金屬化系統組成。用於組件接觸結構19、接合墊組20至34及接合墊36至42之金屬化系統之合適金屬包含銅、鋁、鋁合金、其等之組合或類似物。或者,支撐結構12可為一引線框、一陶瓷基板、包括一樹脂(諸如環氧、聚醯亞胺、三嗪,或酚醛樹脂、環氧玻璃複合物)之一結構或類似物。支撐基板12上的接合墊之佈局或定位不為本發明之實施例之一限制。
一組件(例如,諸如具有相對表面49及51(展示於圖3中)之一半導體晶片48)安裝至組件承接區域18中的組件接觸結構19。半導體晶片48可使用焊料、一導電膏、傳導膜或類似物而附接至組件接觸結構19。表面49及51係在半導體晶片48之相對側上。當耦合至組件接觸結構19之該組件為一半導體晶片時,組件承接區域18可稱為一半導體晶片承接區域或一晶片承接區域。半導體晶片48具有充當一閘極接點之一閘極接合墊50及充當一源極接點之一源極接合墊52。閘極接合墊50係藉由一接合線54連接至閘極接合墊20G且源極接合墊52係藉由對應的接合線56連接至源極接合墊20S。儘管展示複數個接合線56及展示三個源極接合墊20S,但是接合線56之數量及源極接合墊20S之數量不為本發明之限制。可有一個、兩個或更多個接合線56及一個、兩個、三個或更多個接合墊20S。應注意,如整個應用所使用之術語接合線亦可稱為線接合或接合線。
圖2係圖1中所示之但在製造之一稍後階段之一半導體組件10之一等角視圖。圖3係沿著圖2之剖面線3至3截取之半導體組件10之一截面圖。為了簡潔起見,將一起描述圖2及圖3。如參考圖1所討論,閘極接點50係藉由一接合線54連接至接合墊20G且源極接點52係藉由接合線56連接至接合墊20S。具有端64及68及一中心區帶66之一電連接器62將源極電極52耦合至支撐結構12之接合墊40。端64可稱為一插入物區帶,此係因為其可定位於至少兩個半導體晶片之間,亦即,一半導體晶片可定位於插入物區帶64之下且另一半導體晶片可定位於插入物區帶64之上。電連接器62可為一夾子、一線、一帶(例如,諸如一鋁帶)或類似物。端68係透過(例如)一焊料層71接合至接合墊40且插入物區帶64可藉由一電絕緣材料之一層63連接至半導體晶片48。介電質材料63之合適實例包含一陶瓷材料、熱界面材料、導熱膜、氧化層、氮化矽層、氧化鋁或類似物。端68可稱為一接觸區帶,此係因為其使得與接合墊40電接觸。舉例而言,插入物區帶64為一矩形形狀區帶。用於電連接器62之合適材料包含銅、鋁、金屬及塗覆有一貴金屬之金屬合金連接器、錫、鋼、銅合金、鈹、金、銀、鋁合金、黃銅、黃銅合金或類似物。
圖3繪示半導體晶片48係透過一導電且導熱晶粒附接材料60連接至組件接觸結構19。合適晶粒附接材料包含焊料、一傳導膏、一傳導膜或類似物。表面51接觸晶粒附接材料60。舉例而言,半導體晶片48包括一絶緣閘極半導體裝置,其中表面51充當一汲極接點。因此,該汲極接點接觸晶粒附接材料60。閘極接合墊50及源極接合墊52係形成於表面49上或由表面49形成。
圖3進一步繪示支撐結構12,其具有形成於表面14上或由表面14形成之源極接合墊20S、24S、28S及32S及汲極接合墊36及40及連接至導熱體21之組件接觸結構19,該導熱體自組件接觸結構19延伸至表面16。導熱體21適於移除來自安裝於組件接觸結構19上或安裝高於組件接觸結構19之組件之熱。
圖4係在製造之一稍後階段之圖2及圖3之半導體組件10之一等角視圖。圖5係沿著圖4之剖面線5至5截取之半導體組件10之一截面圖及圖6係沿著圖4之剖面線6至6截取之半導體組件10之一截面圖。為了簡潔起見,將一起描述圖4至圖6。圖4中展示安裝至電連接器62之具有相對表面79及81之一半導體晶片78。半導體晶片78係透過一導電晶粒附接材料83連接至插入物區帶64。合適晶粒附接材料包含焊料、一傳導膏、一傳導膜或類似物。晶粒附接材料83可與晶粒附接材料60相同。半導體晶片78具有充當一閘極接點之一閘極接合墊80及充當一源極接點之一源極接合墊82。閘極接點80係藉由一接合線84連接至閘極接合墊22G且源極接點82係藉由對應接合線86連接至源極接合墊22S。儘管展示複數個接合線86及展示三個源極接合墊22S,但是接合線86之數量及源極接合墊22S之數量不為本發明之限制。可有一個、兩個或更多個接合線86及一個、兩個、三個或更多個接合墊22S
具有端94及98及一中心區帶96之一電連接器92將源極電極82連接至支撐結構12之接合墊36。端94可稱為一插入物區帶,此係因為其可定位於至少兩個半導體晶片之間,亦即,一半導體晶片可定位於插入物區帶94之下且另一半導體晶片可定位於插入物區帶94之上。電連接器92可為一夾子、一線、一帶(例如,諸如一鋁帶)或類似物。端98係透過(例如)一焊料層71接合至接合墊36且插入物區帶94可藉由一層介電質材料104連接至半導體晶片78。介電質材料104之合適實例包含一陶瓷材料、熱界面材料、導熱膜、氧化層、氮化矽層、氧化鋁或類似物。介電質層104可由與介電質層63相同之材料組成。端98可稱為一接觸區帶,此係因為其使得與接合墊36電接觸。舉例而言,插入區帶94為一矩形形狀區帶。用於電連接器92之合適材料包含銅、鋁、金屬及塗覆有一貴金屬之金屬合金連接器、錫、鋼、銅合金、鈹、金、銀、鋁合金、黃銅、黃銅合金或類似物。
圖7係在製造之一稍後階段之半導體組件10之一等角視圖。圖7中展示安裝至電連接器92之具有相對表面119及121之一半導體晶片118。應注意,半導體晶片118可透過一介電質材料(例如,諸如介電質層63及104之材料)附接至電連接器92之插入物區帶94。半導體晶片118具有充當一閘極接點之一閘極接合墊120及充當一源極接點之一源極接合墊122。閘極接合墊120係藉由一接合線124連接至閘極接合墊26G且源極接合墊122係藉由對應接合線126連接至源極接合墊26S。儘管展示複數個接合線126及展示三個源極接合墊26S,但是接合線126之數量及源極接合墊26S之數量不為本發明之限制。可有一個、兩個或更多個接合線126及一個、兩個、三個或更多個接合墊26S
圖8係根據本發明之另一實施例之在製造之一早期階段之一半導體組件150之一部分之一俯視圖。圖8中展示一支撐結構12A,例如,諸如具有一表面14、一組件承接區域18、形成於組件承接區域18之一部分中的一組件接觸結構19、接合墊20G1、20S1、22G1、22S1、24G1、24S1、26G1、26S1、28G1、28S1、30G1、30S1、32G1、32S1及34G1、34S1及接合墊36、38、40及42之一印刷電路板。應注意,除了接合墊組20S、22S、24S、26S、28S、30S、32S及34S分別已被接合墊20S1、22S1、24S1、26S1、28S1、30S1、32S1及34S1代替外,基板12A類似於基板12。為了一致起見,圖1中展示之參考符號20G、22G、24G、26G、28G、30G、32G及34G分別已被參考符號20G1、22G1、24G1、26G1、28G1、30G1、32G1及34G1代替。
類似於圖1至圖3中所示之半導體組件10,一組件(例如,諸如具有相對表面49及51(展示於圖3中)之一半導體晶片48)係安裝至組件承接區域18中的組建接觸結構19。當連接至組件接觸結構19之該組件為一半導體晶片時,組件承接區域18可稱為一半導體晶片承接區域或一晶片承接區域。半導體晶片48具有一閘極接點50及一源極接點52。閘極接點50係藉由一接合線54連接至閘極接合墊20G1且源極接點52係藉由一電連接器152連接至源極接合墊20S1。舉例而言,電連接器152具有接觸端154及158及一中心部分156。電連接器152可由與電連接器62及92相同之材料製成。接觸端154可透過一導電材料(例如,諸如焊料)連接至源極接點52。接觸端158可透過一導電材料(例如,諸如焊料)連接至接合墊20S1
圖9係圖8中所示之但在製造之一稍後階段之半導體組件150之一等角視圖。除了接合線52已被具有接觸端154及158之電連接器152代替外,圖9類似於圖2。如上文所述,接觸端154係經由一導電材料(例如,諸如焊料)電連接至源極接點52且接觸端158係透過一導電材料(例如,諸如焊料)電連接至接合墊20S1。接合線及電連接器可稱為互連或電互連。
圖10係圖9中所示之但在製造之一稍後階段之半導體組件150之一等角視圖。除了接合線56及86分別已被電連接器152及162代替外,圖10類似於圖4。參考圖8已描述電連接器152。舉例而言,電連接器162具有接觸端164及168及一中心部分166。接觸端164可透過一導電材料(例如,諸如焊料)連接至源極接點82(展示於圖5中)。接觸端168可透過一導電材料(例如,諸如焊料)連接至接合墊22S1。接合線及電連接器可稱為互連或電互連。
圖11係圖10中所示之但在製造之一稍後階段之半導體組件150之一等角視圖。除了接合線126已被電連接器172代替外,圖11類似於圖7,該電連接器172具有接觸端174及178及在接觸端174與178之間的一中心區帶176。接觸端178係電連接至接合墊26S1且接觸端174係連接至源極接點122。接合線及電連接器可稱為互連或電互連。
圖12係根據本發明之另一實施例之一半導體組件200之一等角視圖。圖12之描述連續自圖7之描述。應注意,圖1至圖7之半導體組件已藉由參考符號10而識別。為了簡潔起見,圖12之半導體組件之描述之參考數字已變成參考符號200。圖12中展示將源極接點122連接至接合墊38之一電連接器202。電連接器202具有端204及208及一中心區帶206。端204可稱為一插入物區帶,此係因為其可定位於至少兩個半導體晶片之間,亦即,一半導體晶片可定位於插入物區帶204之下且另一半導體晶片可定位於插入物區帶204之上。電連接器202可為一夾子、一線、一帶(例如,諸如一鋁帶)或類似物。端208係透過(例如)一焊料層接合至接合墊38且插入物區帶204可藉由一層介電質材料(例如,諸如介電質層63或介電質層104(展示於圖6中))連接至半導體晶片118。舉例而言,插入物區帶204為一矩形形狀區帶。用於電連接器202之合適材料包含銅、鋁、金屬及塗覆有一貴金屬之金屬合金連接器、錫、鋼、銅合金、鈹、金、銀、鋁合金、黃銅、黃銅合金或類似物。
圖13係圖12之但在製造之一稍後階段之半導體組件200之一等角視圖。圖13中展示安裝至電連接器202之具有相對表面219及221之一半導體晶片218。半導體晶片218具有充當一閘極接點之一閘極接合墊220及充當一源極接點之一源極接合墊222。閘極接合墊220係藉由一接合線224連接至閘極接合墊30G且源極接合墊222係藉由對應接合線226連接至源極接合墊30S。接合線可稱為線接合或接合線。儘管展示複數個接合線226及展示三個源極接合墊30S,但是接合線226之數量及源極接合墊30S之數量不為本發明之限制。可有一個、兩個或更多個接合線226及一個、兩個、三個或更多個接合墊30S
圖14係圖13之但在製造之一稍後階段之半導體組件200之一等角視圖。圖4中展示將源極接點222連接至接合墊42之一電連接器242。電連接器242具有端244及248及一中心區帶246。端244可稱為一插入物區帶,此係因為其可定位於至少兩個半導體晶片之間,亦即,一半導體晶片可定位於插入物區帶244之下且另一半導體晶片可定位於插入物區帶244之上。電連接器242可為一夾子、一線、一帶(例如,諸如一鋁帶)或類似物。端248係透過(例如)一焊料層接合至接合墊42且插入物區帶244係透過一層介電質材料(例如,諸如介電質層63或介電質層104(展示於圖6中))連接至半導體晶片218。舉例而言,插入物區帶244為一矩形形狀區帶。用於電連接器242之合適材料包含銅、鋁、金屬及塗覆有一貴金屬之金屬合金連接器、錫、鋼、銅合金、鈹、金、銀、鋁合金、黃銅、黃銅合金或類似物。
圖15係圖14之但在製造之一稍後階段之半導體組件200之一等角視圖。圖15中展示安裝至電連接器242之具有表面259及261之一半導體晶片258。半導體晶片258具有充當一閘極接點之一閘極接合墊260及充當一源極接點之一源極接合墊262。閘極接合墊260係藉由一接合線264連接至閘極接合墊28G且源極接合墊262係藉由對應接合線266連接至源極接合墊28S。接合線可稱為線接合或接合線。儘管展示複數個接合線266及展示三個源極接合墊28S,但是接合線266之數量及源極接合墊28S之數量不為本發明之限制。可有一個、兩個或更多個接合線266及一個、兩個、三個或更多個接合墊28S
通常,在半導體晶片48、78、118、218及258、電連接器62、92、202及242及接合線54、56、84、86、124、126、224、226、264及266周圍形成一保護結構(未展示)。舉例而言,該保護結構為一模製化合物。應注意,保護結構之類型不為本發明之一限制。例如,該保護結構可為一蓋或帽,或類似物。或者,可能不存在該保護結構。
圖16係根據本發明之另一實施例之一半導體組件300之一等角視圖。除了接合線226係連接至導電體202而非連接至接合墊38外,半導體組件300類似於半導體組件200。
圖17係根據本發明之另一實施例之一半導體組件320之一等角視圖。除了源極區帶262係透過一導電體或夾子322而非接合線連接至導電體202外,半導體組件320類似於半導體組件300。
現應瞭解,已提供一種半導體組件及一種用於製造該半導體組件之方法。根據本發明之實施例,以一堆疊組態形成具有(例如)功率金氧半場效電晶體(MOSFET)之半導體晶粒。因此,複數個堆疊半導體晶粒係封裝於一保護材料(例如,諸如一模製化合物)中。根據本發明之實施例之製造半導體組件之一優點在於其容許堆疊三個或更多個半導體晶粒,其減小經封裝之半導體晶粒之覆蓋區。此外,該半導體晶粒可用作個別裝置或可協作以形成(例如)如圖16及圖17中所示之互補組件。此外,根據本發明之實施例使用具有一較小覆蓋區之一封裝增強半導體組件之功率能力。
儘管已在本文中揭示特定實施例,但是其不意欲將本發明限於所揭示之實施例。熟習此項技術者將認知,在不脫離本發明之精神之情況下,可作修改及變更。本發明意欲包含如落入隨附申請專利範圍之範疇內之所有此等修改及變更。
10...半導體組件
12...支撐結構
12A...支撐結構
14...表面
16...表面
18...組件承接區域
19...組件接觸結構
20...接合墊組
20G...接合墊
20S...接合墊
20G1...接合墊
20S1...接合墊
21...導熱體
22...接合墊組
22G...接合墊
22S...接合墊
22G1...接合墊
22S1...接合墊
24...接合墊組
24G...接合墊
24S...接合墊
24G1...接合墊
24S1...接合墊
26...接合墊組
26G...接合墊
26S...接合墊
26G1...接合墊
26S1...接合墊
28...接合墊組
28G...接合墊
28S...接合墊
28G1...接合墊
28S1...接合墊
30...接合墊組
30G...接合墊
30S...接合墊
30G1...接合墊
30S1...接合墊
32...接合墊組
32G...接合墊
32S...接合墊
32G1...接合墊
32S1...接合墊
34...接合墊組
34G...接合墊
34S...接合墊
34G1...接合墊
34S1...接合墊
36...接合墊
38...接合墊
40...接合墊
42...接合墊
48...半導體晶片
49...表面
50...閘極接合墊
51...表面
52...源極接合墊/源極電極
54...接合線
56...接合線
60...晶粒附接材料
62...電連接器
63...電絕緣材料
64...接觸區帶/端
66...中心區帶
68...接觸區帶/端
71...焊料層
78...半導體晶片
79...表面
80...閘極接點
81...表面
82...源極接合墊/源極電極
83...導電晶粒附接材料
84...接合線
86...接合線
92...電連接器
94...端
96...中心區帶
98...端
104...介電質材料
118...半導體晶片
119...表面
120...閘極接合墊
121...表面
122...源極接合墊
124...接合線
126...接合線
150...半導體組件
152...電連接器
154...接觸端
156...中心部分
158...接觸端
162...電連接器
164...接觸端
166...中心部分
168...接觸端
172...電連接器
174...接觸端
176...中心區帶
178...接觸端
200...半導體組件
202...電連接器/導電體
204...端/插入物區帶
206...中心區帶
208...端
218...半導體晶片
219...表面
220...閘極接合墊
221...表面
222...源極接合墊/源極接點
224...接合線
226...接合線
242...電連接器
244...端/插入物區帶
246...中心區帶
248...端
258...半導體晶片
259...表面
260...閘極接合墊
261...表面
262...源極接合墊
264...接合線
266...接合線
300...半導體組件
320...半導體組件
322...導電體/夾子
圖1係根據本發明之實施例之一半導體組件之一部分之一平面圖;
圖2係根據本發明之實施例之一半導體組件之一部分之一等角視圖;
圖3係沿著剖面線3至3截取之圖2之半導體組件之一截面圖;
圖4係在製造之一稍後階段之圖2及圖3之半導體組件之一等角視圖;
圖5係沿著剖面線5至5截取之圖4之半導體組件之一截面圖;
圖6係沿著剖面線6至6截取之圖4之半導體組件之一截面圖;
圖7係在製造之一稍後階段之圖4至圖6之半導體組件之一等角視圖;
圖8係根據本發明之實施例之一半導體組件之一部分之一平面圖;
圖9係在製造之一稍後階段之圖8之半導體組件之一等角視圖;
圖10係在製造之一稍後階段之圖9之半導體組件之一等角視圖;
圖11係在製造之一稍後階段之圖10之半導體組件之一等角視圖;
圖12係在製造之一稍後階段之圖11之半導體組件之一等角視圖;
圖13係在製造之一稍後階段之圖12之半導體組件之一等角視圖;
圖14係在製造之一稍後階段之圖13之半導體組件之一等角視圖;
圖15係在製造之一稍後階段之圖14之半導體組件之一等角視圖;
圖16係根據本發明之實施例之一半導體組件之一等角視圖;及
圖17係根據本發明之實施例之一半導體組件之一等角視圖。
12...支撐結構
14...表面
19...組件接觸結構
20...接合墊組
20G...接合墊
24...接合墊組
26...接合墊組
26G...接合墊
26S...接合墊
28...接合墊組
28G...接合墊
28S...接合墊
30...接合墊組
30G...接合墊
30S...接合墊
32...接合墊組
32G...接合墊
32S...接合墊
34...接合墊組
34G...接合墊
34S...接合墊
36...接合墊
38...接合墊
40...接合墊
42...接合墊
48...半導體晶片
54...接合線
62...電連接器
66...中心區帶
68...接觸區帶/端
78...半導體晶片
81...表面
92...電連接器
96...中心區帶
98...端
118...半導體晶片
119...表面
120...閘極接合墊
121...表面
122...源極接合墊
124...接合線
126...接合線

Claims (10)

  1. 一種半導體組件,其包括:一基板,其具有一組件承接區域及複數個接合墊;一第一半導體晶片,其具有第一表面及第二表面,該第一半導體晶片之該第一表面電耦合至該組件承接區域;一第一介電質材料,其位於該第一半導體晶片之該第二表面之一部份上;一第一電連接器,其具有第一端及第二端,該第一端位於該第一介電質材料上且鄰近於該第一半導體晶片之該第二表面;一第二半導體晶片,其具有第一表面及第二表面,該第二半導體晶片之該第一表面電耦合至該第一電連接器之該第一端,其中該第一導電體之該第一端係定位於該第一半導體晶片與該第二半導體晶片之間;一第二介電質材料,其位於該第二半導體晶片之該第二表面之一部份上;一第二電連接器,其具有第一端及第二端,該第二電連接器之該第一端位於該第二介電質材料上且鄰近於該第二半導體晶片之該第二表面;及一第三半導體晶片,其具有第一表面及第二表面,該第三半導體晶片之該第一表面電耦合至該第二電連接器之該第一端,其中該第二電連接器之該第一端係在該第二半導體晶片與該第三半導體晶片之間。
  2. 如請求項1之半導體組件,其中:該第一半導體晶片之該第一表面包含一汲極之一部分,且進一步包含在該第一半導體晶片之該第二表面之一第一部分處的一閘極接合墊及在該第一半導體晶片之該第二表面之一第二部分處的一源極接合墊;該基板上的該複數個接合墊包括第一接合墊及第二接合墊,且進一步包含耦合於該第一半導體晶片之該閘極接合墊與該基板上的該第一接合墊之間的一第三電連接器及耦合於該第一半導體晶片之該源極接合墊與該基板上的該第二接合墊之間的一第四電連接器;該第二半導體晶片之該第一表面包含一汲極之一部分,且進一步包含在該第二半導體晶片之該第二表面之一第一部分處的一閘極接合墊及在該第二半導體晶片之該第二表面之一第二部分處的一源極接合墊;該基板上的該複數個接合墊包括第三接合墊及第四接合墊,且進一步包含耦合於該第二半導體晶片之該第一部分處的該閘極接合墊與該基板上的該第三接合墊之間的一第五電連接器及耦合於該第二半導體晶片之該源極接合墊與該基板上的該第四接合墊之間的一第六電連接器;及該第三半導體晶片之該第一表面包含一汲極之一部分,且進一步包含在該第二半導體晶片之該第二表面之一第一部分處的一閘極接合墊及在該第二半導體晶片之該第二表面之一第二部分處的一源極接合墊。
  3. 如請求項2之半導體組件,其中該基板上的該複數個接合墊包括第五接合墊及第六接合墊,且進一步包含耦合於該第三半導體晶片之該第一部分處的該閘極接合墊與該基板上的該第五接合墊之間的一第七電連接器及耦合於該第三半導體晶片之該源極接合墊與該基板上的該第六接合墊之間的一第八電連接器。
  4. 如請求項3之半導體組件,其中該第一電連接器及該第二電連接器為夾子,且該第三電連接器、該第四電連接器、該第五電連接器、該第六電連接器、該第七電連接器及該第八電連接器為接合線,且其進一步包含:一第九電連接器,其具有第一端及第二端,該第九電連接器之該第一端鄰近於該第三半導體晶片之該第二表面;及一第四半導體晶片,其具有第一表面及第二表面,該第四半導體晶片之該第一表面耦合至該第九電連接器之該第一端,其中該第九電連接器之該第一端係在該第三半導體晶片與該第四半導體晶片之間。
  5. 如請求項3之半導體組件,其中該第一電連接器及該第二電連接器為夾子,且該第三電連接器、該第四電連接器、該第五電連接器、該第六電連接器、該第七電連接器及該第八電連接器為接合線,且其進一步包含:一第十二電連接器,其具有第一端及第二端,該第十二電連接器之該第一端鄰近於該第四半導體晶片之該第二表面。
  6. 如請求項5之半導體組件,其進一步包含具有第一表面及第二表面之一第五半導體晶片,該第五半導體晶片之該第一表面耦合至該第十二電連接器之該第一端,其中該第十二電連接器之該第一端係在該第四半導體晶片與該第五半導體晶片之間。
  7. 一種半導體組件,其包括:一基板,其具有一晶片承接區域及複數個接合墊;一第一半導體晶片,其電耦合至該晶片承接區域,該第一半導體晶片具有第一表面及第二表面,其中該第二表面包含一閘極接點及一源極接點;一第一介電質材料,其位於該第一半導體晶片之該第二表面之一部份上;一第一電連接器,其耦合於該第一半導體晶片之該第二表面之該部分與該複數個接合墊之一第一接合墊之間,該第一電連接器位於該第一介電質材料上;一第二半導體晶片,其電耦合至該第一電連接器,該第二半導體晶片具有第一表面及第二表面,其中該第二半導體晶片之該第二表面包含一閘極接點及一源極接點;一第二介電質材料,其位於該第二半導體晶片之該第二表面之一部份上;一第二電連接器,其具有第一及第二部分,該第二電連接器之該第一部分位於該第二介電質材料之部分上且該第二部分耦合至該複數個接合墊之一第二接合墊;及 一第三半導體晶片,其具有第一及第二表面,該第三半導體晶片之該第一表面電耦合至該第二電連接器,其中該第二電連接器之該部分介於該第二半導體晶片及該第三半導體晶片之間。
  8. 一種製造一半導體組件之方法,其包括:提供具有一組件承接區域及複數個接合墊之一支撐結構;將一第一半導體晶片耦合至該支撐結構之該組件承接區域,該第一半導體晶片具有第一接合墊及第二接合墊;將該第一半導體晶片之該第一接合墊電耦合至該複數個接合墊之一第一接合墊且將該第一半導體晶片之該第二接合墊電耦合至該複數個接合墊之至少一第二接合墊;以一第一電連接器將該第一半導體晶片耦合至該複數個接合墊之一第三接合墊;將一第二半導體晶片耦合至該第一電連接器,該第二半導體晶片具有一第一接合墊及一第二接合墊;及將該第二半導體晶片之該第一接合墊電耦合至該複數個接合墊之一第四接合墊,將該第二半導體晶片之該第二接合墊電耦合至該複數個接合墊之至少一第五接合墊,且以一第二電連接器將該第二半導體晶片耦合至該複數個接合墊之一第六接合墊。
  9. 如請求項8之方法,其進一步包含: 將一第三半導體晶片耦合至該第二電連接器,該第三半導體晶片具有一第一接合墊及一第二接合墊;將該第三半導體晶片之該第一接合墊電耦合至該複數個接合墊之一第七接合墊且將該第三半導體晶片之該第二接合墊電耦合至該複數個接合墊之一第八接合墊;以一第三電連接器將該第三半導體晶片耦合至該複數個接合墊之一第九接合墊;將一第四半導體晶片耦合至該第三電連接器,該第四半導體晶片具有一第一接合墊及一第二接合墊;將該第四半導體晶片之該第一接合墊電耦合至該複數個接合墊之一第十接合墊且將該第四半導體晶片之該第二接合墊電耦合至該複數個接合墊之一第十一接合墊;及以一第四電連接器將該第四半導體晶片耦合至該複數個接合墊之一第十二接合墊。
  10. 如請求項9之方法,其進一步包含將一第五半導體晶片耦合至該第四電連接器。
TW100121480A 2010-09-15 2011-06-20 半導體組件及其製造方法 TWI532143B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
MYPI2010004310A MY163661A (en) 2010-09-15 2010-09-15 Semiconductor component and method of manufacture

Publications (2)

Publication Number Publication Date
TW201212200A TW201212200A (en) 2012-03-16
TWI532143B true TWI532143B (zh) 2016-05-01

Family

ID=45885351

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100121480A TWI532143B (zh) 2010-09-15 2011-06-20 半導體組件及其製造方法

Country Status (4)

Country Link
CN (1) CN102403291B (zh)
MY (1) MY163661A (zh)
SG (1) SG179332A1 (zh)
TW (1) TWI532143B (zh)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6472758B1 (en) * 2000-07-20 2002-10-29 Amkor Technology, Inc. Semiconductor package including stacked semiconductor dies and bond wires
JP4309368B2 (ja) * 2005-03-30 2009-08-05 エルピーダメモリ株式会社 半導体記憶装置
JP2009094152A (ja) * 2007-10-04 2009-04-30 Hitachi Ltd 半導体装置、その製造方法及び半導体搭載用フレキシブル基板

Also Published As

Publication number Publication date
MY163661A (en) 2017-10-13
CN102403291B (zh) 2016-05-25
SG179332A1 (en) 2012-04-27
TW201212200A (en) 2012-03-16
CN102403291A (zh) 2012-04-04

Similar Documents

Publication Publication Date Title
US8451621B2 (en) Semiconductor component and method of manufacture
CN111446217B (zh) 半导体装置
KR100324333B1 (ko) 적층형 패키지 및 그 제조 방법
KR970010678B1 (ko) 리드 프레임 및 이를 이용한 반도체 패키지
US8163601B2 (en) Chip-exposed semiconductor device and its packaging method
WO2013111276A1 (ja) 電力用半導体装置
US9263375B2 (en) System, method and apparatus for leadless surface mounted semiconductor package
US8916958B2 (en) Semiconductor package with multiple chips and substrate in metal cap
JP2023033351A (ja) 半導体装置
US20100193922A1 (en) Semiconductor chip package
US9640506B2 (en) Method for manufacturing electronic devices
TWI228317B (en) Semiconductor device having clips for connecting to external elements
US20120217657A1 (en) Multi-chip module package
US20040061206A1 (en) Discrete package having insulated ceramic heat sink
TWI596728B (zh) 具有單列直插引線模塊的半導體功率器件及其製備方法
US20170186674A1 (en) Semiconductor packages and methods for forming same
JP5845634B2 (ja) 半導体装置
US20100295160A1 (en) Quad flat package structure having exposed heat sink, electronic assembly and manufacturing methods thereof
TWI620258B (zh) 封裝結構及其製程
US7768104B2 (en) Apparatus and method for series connection of two die or chips in single electronics package
US8785253B2 (en) Leadframe for IC package and method of manufacture
TWI532143B (zh) 半導體組件及其製造方法
US20050194698A1 (en) Integrated circuit package with keep-out zone overlapping undercut zone
JP2005057125A (ja) 半導体装置
US10312186B2 (en) Heat sink attached to an electronic component in a packaged device