TWI593113B - 半導體裝置及其形成方法 - Google Patents

半導體裝置及其形成方法 Download PDF

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TWI593113B
TWI593113B TW103126709A TW103126709A TWI593113B TW I593113 B TWI593113 B TW I593113B TW 103126709 A TW103126709 A TW 103126709A TW 103126709 A TW103126709 A TW 103126709A TW I593113 B TWI593113 B TW I593113B
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Taiwan
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layer
forming
conductive
sidewall
semiconductor device
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TW103126709A
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TW201535740A (zh
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莫如娜Ａ 柯德博
曹學文
李家慶
李達元
魏孝寬
洪志昌
張惠政
張文
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台灣積體電路製造股份有限公司
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Description

半導體裝置及其形成方法
本揭露係有關於一種半導體裝置及其形成方法。
互補式金氧半(complementary metal-oxide-semiconductor,CMOS)技術為一半導體技術，用於製作積體電路(ICs)。一般來說，互補式金氧半(CMOS)電晶體使用多晶矽或金屬作為N型金氧半(NMOS)與P型金氧半(PMOS)電晶體的閘電極，其中以N型摻質摻雜閘電極形成N型金氧半(NMOS)電晶體，以P型摻質摻雜閘電極形成P型金氧半(PMOS)電晶體。
根據本揭露部分觀點，提供一種半導體裝置。半導體裝置包括一閘極本體(gate body)，一導電前層(conductive prelayer)，於該閘極本體上，一導電層，於該導電前層上，以及一第一抑制膜(first inhibitor film)，於至少一部分之該導電前層與該導電層之間。在部分實施例中，該第一抑制膜具有一第一終端，鄰近該閘極本體頂部，以及一第二終端，鄰近該閘極本體底部。在部分實施例中，該第一終端為一自第一閘極本體側壁之第一距離，以及該第二終端為一自第一閘極本體側壁之第二距離。在部分實施例中，該第二距離大於該第一距離。該閘極本體包括一第一閘極本體側壁、一第二閘極本體側壁、 一閘極本體頂部以及一閘極本體底部。
根據本揭露部分觀點，提供一種半導體裝置之形成方法。該方法包括形成一導電前層(conductive prelayer)於一閘極本體(gate body)上，形成一開口於該導電前層中，藉由該導電前層之一第一側壁、該導電前層之一第二側壁與該導電前層之一底部定義該開口，形成一第一抑制膜(first inhibitor film)於該第一側壁、該第二側壁或該底部之至少其中之一上，以及形成一導電層(conductive layer)於該第一抑制膜上。在部分實施例中，該開口具有一頂部寬與一底部寬，其中該頂部寬大於該底部寬。
根據本揭露部分觀點，提供一種半導體裝置之形成方法。該方法包括形成一閘極本體(gate body)於一基板上，形成一導電前層(conductive prelayer)於該閘極本體上，形成一第一抑制膜(first inhibitor film)於該導電前層上，以及形成一導電層(conductive layer)於該第一抑制膜上。在部分實施例中，該導電層具有一頂部寬與一底部寬，該頂部寬大於該底部寬。
為讓本發明之上述目的、特徵及優點能更明顯易懂，下文特舉一較佳實施例，並配合所附的圖式，作詳細說明如下。
200‧‧‧半導體裝置
202‧‧‧半導體基板
204a、204b‧‧‧隔離結構
206‧‧‧閘極本體
208‧‧‧介面層
210‧‧‧閘介電層
212‧‧‧層間介電層
214‧‧‧功函數金屬層
216‧‧‧側壁間隙子
218‧‧‧蓋層
232‧‧‧導電前層
234‧‧‧開口
236‧‧‧導電前層的第一側壁
238‧‧‧導電前層的第二側壁
239‧‧‧導電前層的底部
240‧‧‧開口的頂部寬
241‧‧‧導電層的頂部寬
242‧‧‧開口的底部寬
243‧‧‧導電層的底部寬
244‧‧‧開口高度
250‧‧‧第一抑制膜
252‧‧‧第二抑制膜
253‧‧‧導電材料成長方向
254‧‧‧第一抑制膜的第一終端
256‧‧‧第一抑制膜的第二終端
258‧‧‧第二抑制膜的第三終端
260‧‧‧第二抑制膜的第四終端
260‧‧‧導電層
100‧‧‧半導體裝置的製造方法
102‧‧‧形成一半導體基板
104‧‧‧形成一閘極本體
106‧‧‧形成一導電前層
108‧‧‧形成一開口
110‧‧‧形成一第一抑制膜
112‧‧‧形成一導電層
310‧‧‧第一製程
320‧‧‧第二製程
330‧‧‧第三製程
第1圖係根據部分實施例，說明半導體裝置製造方法的流程圖； 第2圖係根據部分實施例，半導體裝置在製造過程中的剖面示意圖；第3圖係根據部分實施例，半導體裝置在製造過程中的剖面示意圖；第4圖係根據部分實施例，半導體裝置在製造過程中的剖面示意圖；第5a圖係根據部分實施例，半導體裝置在製造過程中的剖面示意圖；第5b圖係根據部分實施例，半導體裝置在製造過程中的剖面示意圖；第6圖係根據部分實施例，半導體裝置在製造過程中的剖面示意圖；第7圖係根據部分實施例，半導體裝置在製造過程中的剖面示意圖。
本揭露書提供許多不同實施例以實施本揭露之不同技術特徵。元件與排列方式的特定實施例描述如下，以簡化本揭露，然，其非用以限制本揭露之範圍。舉例來說，當述及一第一結構形成於一第二結構上或之上時，包括第一結構與第二結構直接接觸或間隔有一或更多其他結構之情形，使得第一結構與第二結構可能不會直接接觸。此外，本揭露書可能於許多實施例重複使用標號及/或文字。此重複僅為了簡化與清楚化，不代表所討論之不同實施例及/或結構配置之間必然有關聯。
此處提供一或多個半導體裝置以及一或多種該等半導體裝置的形成方法。在部分實施例中，一半導體裝置包括一多閘電晶體(multi-gate transistor)、鰭式多閘電晶體(fin-type multi-gate transistor)、一環繞式閘極(gate-all-around,GAA)金氧半場效電晶體(MOSFET)或一平面式金屬閘極互補式金氧半導體(CMOS)的至少其中之一。在部分實施例中，半導體裝置包括一閘極本體、一導電前層(conductive prelayer)、一抑制膜(inhibitor film)或一導電層的至少其中之一。在部分實施例中，提供包括一定向蝕刻製程(directional etching process)與一側壁鈍化製程(sidewall passivation process)的方法。在部分實施例中，該方法抑制導電前層或導電層的至少其中之一中空隙或裂縫的形成。
請參閱第1圖，根據部分實施例，說明半導體裝置(semiconductor device)200的製造方法100的流程圖。亦請參閱第2~7圖，根據部分實施例，例如根據第1圖的方法100，說明半導體裝置200在不同製造階段的剖面示意圖，在部分實施例中，以一互補式金氧半導體(CMOS)製造流程製作部分半導體裝置200。在部分實施例中，在第1圖的方法100之前、之中及之後提供額外製程。
於步驟102，形成一半導體基板202，如第2圖所示。在部分實施例中，僅提供或接收半導體基板202，其形成非為方法100的一部分。在部分實施例中，半導體基板202包括一磊晶層(epitaxy layer)、一絕緣層覆矽(silicon-on-insulator,SOI)結構、一晶圓或由一晶圓所形成的晶粒(die)的至少其中之 一。在部分實施例中，半導體基板202為一矽基板。在部分實施例中，半導體基板202包括矽鍺(silicon germanium)、碳化矽(silicon carbide)、砷化鎵(gallium arsenic)、磷化鎵(gallium phosphide)、磷化銦(indium phosphide)、砷化銦(indium arsenide)、銻化銦(indium antimonide)或其他適合的半導體材料的至少其中之一。在部分實施例中，半導體基板202包括其他結構，例如一埋入層(buried layer)或一磊晶層。半導體基板202包括一摻雜磊晶層。在部分實施例中，半導體基板202包括一半導體層，覆蓋另一不同型式的半導體層。在部分實施例中，半導體基板202為一矽鍺層覆矽層(silicon layer on a silicon germanium layer)。
在部分實施例中，藉由一第一製程310形成至少一部分半導體基板202或對其進行處理。在部分實施例中，第一製程310包括一磊晶製程、一佈植製程或一接合製程(bonding process)的至少其中之一。在部分實施例中，藉由固相磊晶(solid-phase epitaxy,SPE)或氣相磊晶(vapor-phase epitaxy)的至少其中之一成長半導體基板202。在部分實施例中，第一製程310包括佈植一摻質。在部分實施例中，摻質為n-型或p-型摻質的至少其中之一。在部分實施例中，n-型摻質包括砷或磷的至少其中之一。在部分實施例中，p-型摻質包括硼。在部分實施例中，第一製程310包括摻質置入擴散(drive-in diffusion)的熱製程。
在部分實施例中，半導體裝置200藉由隔離結構204a、204b與其他裝置電性隔離。在部分實施例中，設置隔離 結構204a、204b的至少其中之一於半導體基板202中。在部分實施例中，隔離結構204a、204b的至少其中之一為一淺溝槽隔離(STI)結構。在部分實施例中，隔離結構204a、204b包括矽的局部氧化(local oxidation of silicon,LOCOS)結構。在部分實施例中，隔離結構204a、204b的至少其中之一包括氧化矽、氮化矽、氮氧化矽、摻氟矽玻璃(FSG)或低介電常數(low-k)介電材料的至少其中之一。
於步驟104，形成一閘極本體206，如第3圖所示。在部分實施例中，閘極本體206包括一介面層(interfacial layer)208、一閘介電層210、一層間介電層(interlayer dielectric,ILD)212、一功函數金屬層(work function metal layer)214、側壁間隙子(sidewall spacers)216或一蓋層(capping layer)218的至少其中之一。
在部分實施例中，形成介面層208於側壁間隙子216上並覆蓋半導體基板202。在部分實施例中，介面層208包括一氧化矽層，其厚度介於約5埃至約50埃之間。在部分實施例中，介面層208包括矽氧化鉿(HfSiO)或氮氧化矽(SiON)的至少其中之一，其藉由原子層沈積(ALD)、化學氣相沈積(CVD)、物理氣相沈積(PVD)、熱氧化及氮化、電漿氧化或氮化的至少其中之一所形成。
在部分實施例中，形成閘介電層210於介面層208上。在另一實施例中，介面層208並未出現，而是形成閘介電層210於側壁間隙子216上並覆蓋半導體基板202。在部分實施例中，閘介電層210為一高介電常數(high-k)介電層。在部分實 施例中，藉由原子層沈積(ALD)、化學氣相沈積(CVD)、有機金屬化學(metalorganic)氣相沈積(MOCVD)、物理氣相沈積(PVD)、電漿輔助(plasma enhance)化學氣相沈積(PECVD)、電漿輔助原子層沈積(PEALD)或其他適當技術的至少其中之一形成閘介電層210。在部分實施例中，閘介電層210的厚度約5埃至約50埃。在部分實施例中，閘介電層210包括兩層或三層的高介電常數(high-k)膜。在部分實施例中，閘介電層210包括氧化鑭(LaO)、氧化鋁(AlO)、氧化鋯(ZrO)、氧化鈦(TiO)、氧化鉭(Ta2O5)、氧化釔(Y2O3)、鈦酸鍶(SrTiO3)(STO)、鈦酸鋇(BaTiO3)(BTO)、鋯酸鋇(BaZrO)、氧化鉿(HfOx)、鋯酸鉿(HfZrO)、鑭酸鉿(HfLaO)、矽酸鉿(HfSiO)、矽酸鑭(LaSiO)、矽酸鋁(AlSiO)、鉭酸鉿(HfTaO)、鈦酸鉿(HfTiO)、鈦酸鋇鍶((Ba,Sr)TiO3)(BST)、三氧化二鋁(Al2O3)、氮化矽(Si3N4)或氮氧化物的至少其中之一。在部分實施例中，實施一後高介電常數沈積回火(post high-k deposition anneal)，作為形成閘介電層210的一部分製程。
在部分實施例中，層間介電層(ILD)212包括一氧化物，其藉由一高深寬比製程(high aspect ratio process,HARP)或高密度電漿沈積製程(high density plasma(HDP)deposition process)的至少其中之一所形成。在部分實施例中，層間介電層(ILD)212的沈積填入半導體裝置200與相鄰半導體裝置之間的空隙。
在部分實施例中，形成功函數金屬層214於閘介電層210上。在部分實施例中，功函數金屬層214為一n-型或p-型 的功函數金屬。在部分實施例中，功函數金屬層214為鋁化鈦(titanium aluminide,TiAl)、三鋁化鈦(TiAl3)、鋁化鎳(nickel aluminide,NiAl)或鋁化鐵(iron aluminide,FeAl)的至少其中之一。在部分實施例中，功函數金屬層214的厚度介於約5埃至約100埃。在部分實施例中，藉由原子層沈積(ALD)、化學氣相沈積(CVD)或物理氣相沈積(PVD)製程的至少其中之一形成功函數金屬層214。
在部分實施例中，側壁間隙子(sidewall spacer)216包括氮化矽、氧化矽、碳化矽或氮氧化矽的至少其中之一。在部分實施例中，側壁間隙子(sidewall spacer)216的寬度約3奈米至約100奈米。
在部分實施例中，形成蓋層218於閘介電層210或功函數金屬層214的至少其中之一上。在部分實施例中，蓋層218包括氮化鈦(titanium nitride,TiN)、氮化鉭(tantalum nitride,TaN)或氮化矽(Si3N4)。在部分實施例中，蓋層218的厚度約5埃至約50埃。在部分實施例中，蓋層218作為一阻障，以保護閘介電層210。在部分實施例中，藉由原子層沈積(ALD)、化學氣相沈積(CVD)或物理氣相沈積(PVD)製程的至少其中之一形成蓋層218。
於步驟106，形成一導電前層(conductive prelayer)232，如第4圖所示。在部分實施例中，形成導電前層232於閘極本體206上。在部分實施例中，導電前層232包括一金屬。在部分實施例中，導電前層232包括鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、鋁化鈦(TiAl)、氮化鋁鈦(TiAlN)、 氮化鉭(TaN)、矽化鎳(NiSi)或矽化鈷(CoSi)的至少其中之一。在部分實施例中，導電前層232包括一導電材料，其具有一功函數。在部分實施例中，導電前層232包括一多晶。在部分實施例中，該多晶為一多晶矽。在部分實施例中，導電前層232包括一摻雜多晶矽，其為勻一或非均一摻雜的至少其中之一。在部分實施例中，導電前層232的厚度約3奈米至約200奈米。在部分實施例中，導電前層232具有均一厚度。在部分實施例中，藉由原子層沈積(ALD)、化學氣相沈積(CVD)、物理氣相沈積(PVD)或電鍍(plating)製程的至少其中之一形成導電前層232。
於步驟108，形成一開口234，如第5a、5b圖所示。在部分實施例中，形成開口234於導電前層232中。在部分實施例中，藉由導電前層232的第一側壁236、導電前層232的第二側壁238或導電前層232的一底部239的至少其中之一定義開口234，如第5b圖所示。在部分實施例中，開口234包括一頂部寬240、一底部寬242或一開口高度244。在部分實施例中，頂部寬240約1奈米至約1000奈米。在部分實施例中，底部寬242約2埃至約1000奈米。在部分實施例中，開口高度244約10奈米至約1000奈米。在部分實施例中，開口234實質上為一V形。在部分實施例中，開口234具有一錐形輪廓。在部分實施例中，頂部寬240大於底部寬242。在部分實施例中，頂部寬240大於底部寬242約1.3倍至約2.2倍。
在部分實施例中，藉由一第二製程320形成開口234，如第5a圖所示。在部分實施例中，第二製程320包括一蝕 刻製程。在部分實施例中，實施蝕刻製程於一罩幕元件與導電前層232露出的表面上。在部分實施例中，第二製程320包括一乾蝕刻製程。在部分實施例中，蝕刻製程為一定向蝕刻製程。在部分實施例中，定向蝕刻製程形成錐形輪廓的開口234。在部分實施例中，實施定向蝕刻製程使得頂部寬240大於底部寬242。在部分實施例中，蝕刻製程包括使用氫氟酸(HF)、氫氧化鈉(NaOH)、氯氣(Cl2)、四氟甲烷(CF4)、六氟化硫(SF6)或三氟化氮(NF3)的至少其中之一。在部分實施例中，蝕刻製程包括將導電前層232曝露於約8mTorr的六氟化硫至約250Torr的六氟化硫。
於步驟110，形成一第一抑制膜250，如第6圖所示。在部分實施例中，形成第一抑制膜250於第一側壁236、第二側壁238或底部239的至少其中之一上。在部分實施例中，形成一第二抑制膜252於第一抑制膜250、第一側壁236、第二側壁238或底部239的至少其中之一上。在部分實施例中，形成第一抑制膜250於第一側壁236上，以及形成第二抑制膜252於第二側壁238上。在部分實施例中，第一抑制膜250具有一第一終端254或一第二終端256的至少其中之一，以及第二抑制膜252具有一第三終端258或一第四終端260的至少其中之一。在部分實施例中，第一終端254或第三終端258的至少其中之一鄰近閘極本體的頂部或基板遠端，以及第二終端256或第四終端260的至少其中之一鄰近閘極本體的底部或基板。在部分實施例中，第一終端254與第三終端258以一頂部距離隔開，以及第二終端256或第四終端260以一底部距離隔開，該底部距離小於頂部距 離。
在部分實施例中，藉由一第三製程330形成第一抑制膜250或第二抑制膜252的至少其中之一。在部分實施例中，第三製程330包括一鈍化製程(passivation process)。在部分實施例中，鈍化製程包括將第一側壁236、第二側壁238或底部239的至少其中之一曝露於一鈍化氣體(passivation gas)。在部分實施例中，鈍化氣體包括氮氣(N2)、氧氣(O2)或三氟甲烷(CHF3)的至少其中之一。在部分實施例中，鈍化氣體包括約15sccm至約500sccm的氮氣、約5sccm至約150sccm的三氟甲烷或約5sccm至約150sccm的氧氣的至少其中之一。在部分實施例中，以一約100瓦至約1500瓦的功率源(power source)實施鈍化製程。在部分實施例中，以一約0瓦至約450瓦的偏壓功率(bias power)實施鈍化製程。在部分實施例中，以一約攝氏30度至約攝氏80度的溫度實施鈍化製程。在部分實施例中，至少部分的蝕刻製程與鈍化製程同時實施。在部分實施例中，一混合氣體包括鈍化氣體與蝕刻氣體。在部分實施例中，當同時實施鈍化製程與蝕刻製程時，使用該混合氣體。在部分實施例中，混合氣體包括約8sccm至約250sccm的六氟化硫(SF6)、約15sccm至約500sccm的氮氣(N2)、約5sccm至約150sccm的氯氣(Cl2)及約5sccm至約150sccm的氧氣(O2)。
在部分實施例中，第三製程330包括沈積第一抑制膜250或第二抑制膜252的至少其中之一於第一側壁236、第二側壁238或底部239的至少其中之一上。在部分實施例中，藉由原子層沈積(ALD)、化學氣相沈積(CVD)或物理氣相沈積(PVD) 製程的至少其中之一沈積第一抑制膜250或第二抑制膜252的至少其中之一。在部分實施例中，第一抑制膜250或第二抑制膜252的至少其中之一包括一氮化物、一氧化物、一矽化物或一高分子的至少其中之一。在部分實施例中，第一抑制膜250或第二抑制膜252的至少其中之一包括一非導電材料。在部分實施例中，第一抑制膜250或第二抑制膜252的至少其中之一包括氮化鎢(WNx)、氧化鎢(WOx)、矽化鎢(WSix)或烷基鎢(W(CH)x)的至少其中之一。在部分實施例中，設置第一抑制膜250或第二抑制膜252的至少其中之一，以抑制後續金屬成長於第一側壁236或第二側壁238的至少其中之一上。在部分實施例中，設置第一抑制膜250或第二抑制膜252的至少其中之一，以促進任何後續的導電材料以一底部朝頂部的方向(bottom-to-top direction)成長於開口234中，如箭頭253所示。在部分實施例中，第一抑制膜250或第二抑制膜252的至少其中之一的厚度約1埃至約200埃。
於步驟112，形成一導電層260，如第7圖所示。在部分實施例中，形成導電層260於第一抑制膜250、第二抑制膜252或導電前層232的至少其中之一上。在部分實施例中，導電層260包括一金屬。在部分實施例中，導電層260包括鋁(Al)、銅(Cu)、鎢(W)、鈦(Ti)、鉭(Ta)、氮化鈦(TiN)、鋁化鈦(TiAl)、氮化鋁鈦(TiAlN)、氮化鉭(TaN)、矽化鎳(NiSi)或矽化鈷(CoSi)的至少其中之一。在部分實施例中，導電層260包括一導電材料，其具有一功函數。在部分實施例中，導電層260包括一多晶。在部分實施例中，該多晶為一多晶矽。在部分實施例中， 導電層260包括一摻雜多晶矽，其為勻一或非均一摻雜的至少其中之一。在部分實施例中，導電前層232與導電層260包括相同導電材料。在部分實施例中，藉由原子層沈積(ALD)、化學氣相沈積(CVD)、物理氣相沈積(PVD)或電鍍(plating)製程的至少其中之一形成導電層260。在部分實施例中，藉由沈積一導電材料於開口234中鄰近底部239的位置並以箭頭253所指方向自底部填滿開口，以形成導電層260。在部分實施例中，錐形形狀的開口234抑制導電前層232及導電層260中空隙或裂縫的形成。在部分實施例中，錐形形狀的開口234有利於均勻一致地沈積導電前層232或導電層260的至少其中之一。在部分實施例中，導電層260具有一頂部寬241與一底部寬243，其中頂部寬241大於底部寬243。在部分實施例中，導電層260的頂部寬241反映出開口234的頂部寬240，以及導電層260的底部寬243反映出開口234的底部寬242。
在部分實施例中，半導體裝置200包括未特別揭露的其他層或結構，包括一源極、一汲極、一接觸窗(contact)、一內連線(interconnect)或其他適合結構的至少其中之一。在部分實施例中，對半導體裝置200實施其他後段(back end of line,BEOL)製程。
此處提供不同操作的實施例。部分或全部操作所描述的順序不應解釋為暗示該些操作一定須依賴此順序。替代的順序給出該些描述的好處是可理解的。此外，在此處所提供的每一實施例中，並非所有操作均必要存在。再者，在部分實施例中，並非所有操作均為必要。
此外，除非另有規定，否則「第一」、「第二」或其類似描述並非暗示一時間觀點、一空間觀點或順序等，該等字詞僅用來作為結構、元件、項目等的識別符號、名稱等。舉例來說，一第一通道與一第二通道通常對應通道A與通道B或兩不同或兩相同通道或同一通道。
在部分實施例中，所描述的層、結構、元件等以相對於彼此的特定尺寸說明，例如結構尺寸或方向，以達簡單及便於理解的目的，且相同的實際尺寸實質上不同於此處所描述者均是可理解的。此外，此處提及用來形成各層、區域、結構、元件等的多種現存技術，例如佈植技術、摻雜技術、塗佈技術、濺鍍技術、例如熱成長的成長技術、或例如化學氣相沈積(CVD)、物理氣相沈積(PVD)、電漿輔助化學氣相沈積(PECVD)或原子層沈積(ALD)的沈積技術。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
200‧‧‧半導體裝置
202‧‧‧半導體基板
204a、204b‧‧‧隔離結構
206‧‧‧閘極本體
208‧‧‧介面層
210‧‧‧閘介電層
212‧‧‧層間介電層
214‧‧‧功函數金屬層
216‧‧‧側壁間隙子
218‧‧‧蓋層
232‧‧‧導電前層
241‧‧‧導電層的頂部寬
243‧‧‧導電層的底部寬
250‧‧‧第一抑制膜
252‧‧‧第二抑制膜
253‧‧‧導電材料成長方向
260‧‧‧導電層
330‧‧‧第三製程

Claims (10)

  1. 一種半導體裝置之形成方法，包括：形成一導電前層(conductive prelayer)於一閘極本體(gate body)上；形成一開口於該導電前層中，藉由該導電前層之一第一側壁、該導電前層之一第二側壁與該導電前層之一底部定義該開口，該開口具有一頂部寬與一底部寬，該頂部寬大於該底部寬；形成一第一抑制膜(first inhibitor film)於該第一側壁、該第二側壁或該底部之至少其中之一上；以及形成一導電層於該第一抑制膜上。
  2. 如申請專利範圍第1項所述之半導體裝置之形成方法，其中該形成該第一抑制膜之步驟包括：將該第一側壁、該第二側壁或該底部之至少其中之一曝露於一鈍化氣體(passivation gas)。
  3. 如申請專利範圍第2項所述之半導體裝置之形成方法，其中該鈍化氣體包括氮氣(N2)、氧氣(O2)或三氟甲烷(CHF3)之至少其中之一。
  4. 如申請專利範圍第1項所述之半導體裝置之形成方法，其中該形成該開口之步驟包括：實施一定向蝕刻製程(directional etching process)，以使該頂部寬大於該底部寬。
  5. 一種半導體裝置之形成方法，包括：形成一導電前層(conductive prelayer)於一閘極本體(gate body)上；形成一開口於該導電前層中，藉由該導電前層之一第一側壁、該導電前層之一第二側壁與該導電前層之一底部定義該開口，該開口具有一頂部寬與一底部寬，該頂部寬大於該底部寬；形成一第一抑制膜(first inhibitor film)於該第一側壁上；形成一第二抑制膜(second inhibitor film)於該第二側壁上；以及形成一導電層於該第一抑制膜或該第二抑制膜之至少其中之一上。
  6. 如申請專利範圍第5項所述之半導體裝置之形成方法，其中該形成該第一抑制膜之步驟或該形成該第二抑制膜之步驟之至少其中之一包括：將該第一側壁曝露於一第一鈍化氣體(first passivation gas)；或將該第二側壁曝露於一第二鈍化氣體(second passivation gas)之至少其中之一。
  7. 如申請專利範圍第6項所述之半導體裝置之形成方法，其中該第一鈍化氣體或該第二鈍化氣體之至少其中之一包括氮氣(N2)、氧氣(O2)或三氟甲烷(CHF3)之至少其中之一。
  8. 如申請專利範圍第5項所述之半導體裝置之形成方法，其中該形成該開口之步驟包括：實施一定向蝕刻製程(directional etching process)，以使該頂部寬大於該底部寬。
  9. 一種半導體裝置，包括：一閘極本體(gate body)，於一基板上；一導電前層(conductive prelayer)，於該閘極本體上，其中該導電前層具有一側壁；一第一抑制膜(first inhibitor film)，於該導電前層之該側壁上；以及一導電層，於該第一抑制膜上，該導電層具有一頂部寬與一底部寬，該頂部寬大於該底部寬。
  10. 如申請專利範圍第9項所述之半導體裝置，更包括一第二抑制膜(second inhibitor film)，於該導電前層與該導電層之間。
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US10014382B2 (en) 2018-07-03
US20150262827A1 (en) 2015-09-17
US11211465B2 (en) 2021-12-28
US20180308944A1 (en) 2018-10-25
TW201535740A (zh) 2015-09-16

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