TW201601202A - 半導體元件及其製作方法 - Google Patents

半導體元件及其製作方法 Download PDF

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TW201601202A
TW201601202A TW103121078A TW103121078A TW201601202A TW 201601202 A TW201601202 A TW 201601202A TW 103121078 A TW103121078 A TW 103121078A TW 103121078 A TW103121078 A TW 103121078A TW 201601202 A TW201601202 A TW 201601202A
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layer
gate structure
patterned
substrate
germanium
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許家福
邱春茂
徐世杰
柯建村
陳俊隆
郭龍恩
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聯華電子股份有限公司
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Priority to US14/328,720 priority patent/US9196699B1/en
Priority to US14/919,738 priority patent/US9385206B2/en
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Abstract

本發明是揭露一種製作半導體元件的方法。首先提供一基底，然後形成一閘極結構於基底上、沉積一襯墊層於閘極結構與該基底上以及利用一包含氟甲烷(CH3F)、氧氣(O2)及氦氣(He)之氣體進行蝕刻製程，以於閘極結構旁形成一側壁子。

Description

半導體元件及其製作方法
本發明是關於一種半導體元件，尤指一種側壁子底部具有一錐形輪廓的半導體元件。
在習知半導體產業中，多晶矽係廣泛地應用於半導體元件如金氧半導體(metal-oxide-semiconductor，MOS)電晶體中，作為標準的閘極填充材料選擇。然而，隨著MOS電晶體尺寸持續地微縮，傳統多晶矽閘極因硼穿透(boron penetration)效應導致元件效能降低，及其難以避免的空乏效應(depletion effect)等問題，使得等效的閘極介電層厚度增加、閘極電容值下降，進而導致元件驅動能力的衰退等困境。因此，半導體業界更嘗試以新的閘極填充材料，例如利用功函數(work function)金屬來取代傳統的多晶矽閘極，用以作為匹配高介電常數(High-K)閘極介電層的控制電極。
然而，在現今金屬閘極電晶體製作過程中，特別是在製作出閘極結構並接著形成後續側壁子的過程中，所使用的蝕刻氣體容易因過蝕刻、底切等現象，而蝕穿側壁子滲入閘極結構底部，造成閘極結構底部高介電常數介電層以及/或底部金屬阻隔層(bottom barrier metal,BBM)腐蝕(erosion)的情形，進而影響元件效能。因此 如何改良現今製程以解決上述問題即為現今一重要課題。
本發明較佳實施例是揭露一種製作半導體元件的方法。首先提供一基底，然後形成一閘極結構於基底上、沉積一襯墊層於閘極結構與該基底上以及利用一包含氟甲烷(CH3F)、氧氣(O2)及氦氣(He)之氣體進行蝕刻製程，以於閘極結構旁形成一側壁子。
本發明另一實施例是揭露一種半導體元件，包含一基底、一閘極結構設於基底上以及一側壁子設於閘極結構旁，其中側壁子之底部具有一錐形輪廓。
12‧‧‧基底
14‧‧‧淺溝隔離
16‧‧‧介質層
18‧‧‧堆疊結構
20‧‧‧高介電常數介電層
22‧‧‧底部金屬阻隔層
24‧‧‧矽層
26‧‧‧硬遮罩
28‧‧‧閘極結構
30‧‧‧輕摻雜汲極
32‧‧‧襯墊層
34‧‧‧側壁子
36‧‧‧中間部
38‧‧‧底部
40‧‧‧錐形輪廓
42‧‧‧凸面曲線
44‧‧‧主側壁子
46‧‧‧源極/汲極區域
48‧‧‧接觸洞蝕刻停止層
50‧‧‧層間介電層
52‧‧‧功函數金屬層
54‧‧‧低阻抗金屬層
56‧‧‧導電層
第1圖至第5圖為本發明較佳實施例製作一半導體元件之示意圖。
請參照第1圖至第5圖，第1圖至第5圖為本發明較佳實施例製作一半導體元件之示意圖。如第1圖所示，首先提供一基底12，例如一晶圓(wafer)或矽覆絕緣(SOI)基底等，且基底中設有複數個淺溝隔離(shallow trench isolation,STI)14。隨後全面性覆蓋一介質層16於基底12與淺溝隔離14上，並再形成一堆疊結構18於基底12上，其中形成堆疊結構18的方式包含依序於介質層上16形成一高介電常數介電層20、一底部金屬阻隔(bottom barrier metal,BBM)層22、一矽層24以及一硬遮罩26。
在本實施例中，介質層16較佳包含矽化物層，例如二氧 化矽(SiO2)、氮化矽(SiN)或氮氧化矽(SiON)，但不排除可選自高介電常數的介電材料，底部金屬阻隔層22較佳包含氮化鈦(TiN)，矽層24較佳包含單晶矽、摻雜多晶矽或非摻雜多晶矽，而硬遮罩26可選自由碳化矽(SiC)、氮氧化矽(SiON)、氮化矽(SiN)、氮碳化矽(SiCN)以及氮硼化矽(SiBN)等所構成的群組，但不侷限於此。本實施例之硬遮罩26雖較佳為一單層硬遮罩，但並不侷限於此，又可選擇性採用一由例如氧化矽及氮化矽所構成的複合式硬遮罩，此變化型也屬本發明所涵蓋的範圍。
另外，本實施例是以金屬閘極置換製程中後閘極(gate last)製程之先高介電常數介電層(high-k first)製程為例，故高介電常數介電層20較佳為一具有I型剖面之高介電常數介電層，其材料包含介電常數大於4的介電材料，例如係選自氧化鉿(hafnium oxide，HfO2)、矽酸鉿氧化合物(hafnium silicon oxide，HfSiO4)、矽酸鉿氮氧化合物(hafnium silicon oxynitride，HfSiON)、氧化鋁(aluminum oxide，Al2O3)、氧化鑭(lanthanum oxide，La2O3)、氧化鉭(tantalum oxide，Ta2O5)、氧化釔(yttrium oxide，Y2O3)、氧化鋯(zirconium oxide，ZrO2)、鈦酸鍶(strontium titanate oxide，SrTiO3)、矽酸鋯氧化合物(zirconium silicon oxide，ZrSiO4)、鋯酸鉿(hafnium zirconium oxide，HfZrO4)、鍶鉍鉭氧化物(strontium bismuth tantalate,SrBi2Ta2O9,SBT)、鋯鈦酸鉛(lead zirconate titanate,PbZrxTi1-xO3,PZT)、鈦酸鋇鍶(barium strontium titanate,BaxSr1-xTiO3,BST)、或其組合所組成之群組。
在本實施例中，形成高介電常數介電層20的方法包括原子層沉積(atomic layer deposition,ALD)製程或有機金屬化學氣相沉 積法(metal-organic chemical vapor deposition,MOCVD)，但不以此為限。
然後如第2圖所示，形成一圖案化遮罩，例如一圖案化光阻層(圖未示)於硬遮罩26上，並利用此圖案化光阻層當作遮罩進行一圖案轉移製程，以單次蝕刻或逐次蝕刻方式去除部分未被圖案化光阻層所遮蓋的硬遮罩26、矽層24、底部金屬阻隔層22以及高介電常數介電層20，以於介質層16上形成一閘極結構28。換句話說，閘極結構28較佳包含圖案化之高介電常數介電層20、圖案化之底部金屬阻隔層22、圖案化之矽層24以及圖案化之硬遮罩26。
如第3圖所示，然後進行一側壁子製程，例如可先形成一襯墊層32並覆蓋閘極結構28與介質層16，其中襯墊層32較佳包含二氧化矽或氮化矽，但不侷限於此。然後如第4圖所示，進行一蝕刻製程，以於閘極結構28旁形成一側壁子34。
一般而言，現行沉積完襯墊層32後通常是採用包含三氟甲烷(CHF3)、二氟甲烷(CH2F2)、氧氣(O2)及氟甲烷(CH3F)之蝕刻氣體搭配較低的偏壓功率(bias power)來去除部分襯墊層以形成一側壁子。然而以此配方的蝕刻氣體搭配較低偏壓功率容易產生過度的側向蝕刻(lateral etching)，進而侵蝕到閘極結構中的高介電常數介電層等材料層。
為改良上述習知製程中的缺點，本發明較佳於襯墊層32形成後利用一包含氟甲烷(CH3F)、氧氣(O2)及氦氣(He)之蝕刻氣體以單次或多次蝕刻方式去除部分襯墊層32以形成一側壁子34。依據 本發明之較佳實施例，以上述包含氟甲烷(CH3F)、氧氣(O2)及氦氣(He)等氣體進行蝕刻製程所搭配的偏壓功率較佳高於上述現行以三氟甲烷(CHF3)、二氟甲烷(CH2F2)、氧氣(O2)及氟甲烷(CH3F)等氣體所進行蝕刻製程的偏壓功率，且利用此配方的蝕刻氣體所形成的側壁子34包含一中間部36與一底部38，其中底部38之寬度較佳大於中間部36之寬度。需注意的是，相較於現行製程所常見具有L形狀的側壁子、整個側壁子為垂直狀但不具任何外凸輪廓、或外側側壁呈現一凹面曲線(concave curve)的側壁子，本發明之側壁子的底部38，沿遠離閘極結構28的水平方向上，較佳呈現一約略錐形的輪廓(tapered profile)，特別是該錐形輪廓40又包含一凸面曲線(convex curve)42。更具體而言，如第3圖所示，側壁子34的內側側壁雖同樣貼附閘極結構28側壁呈現垂直狀態，但側壁子34的外側側壁，例如中間部36的外側側壁較佳呈現凹面曲線而底部38的外側側壁呈現凸面曲線，或中間部36的外側側壁與底部38的外側側壁較佳呈現相反的曲線。本發明除了可利用底部38外凸的部分提升側壁子34底部的結構性及其與基底12的接合面積，又可同時避免閘極結構28裡的高介電常數介電層20受到側壁子製程之蝕刻氣體的侵蝕而耗損。至此即完成本發明較佳實施例製作一半導體元件的流程。
請再參照第4圖，本發明另揭露一種半導體元件結構，其主要包含一基底12、一介質層16設於基底12上、一閘極結構28設於介質層16上以及一側壁子34設於閘極結構28旁與部分介質層16上。如圖中所示，閘極結構28包含一圖案化之高介電常數介電層20、一圖案化之底部金屬阻隔層22設於圖案化之高介電常數介電層20上、一圖案化之矽層24設於圖案化之底部金屬阻隔層22上以及一圖案化之硬遮罩26設於圖案化之矽層24上。
依據本發明之較佳實施例，介質層16包含二氧化矽，圖案化之底部金屬阻隔層22包含氮化鈦，圖案化之矽層24包含非晶矽或多晶矽，而側壁子34則包含二氧化矽或氮化矽。此外，側壁子34包含一中間部36與一底部38，且底部之寬度較佳大於中間部之寬度。更具體而言，側壁子34的底部較佳呈現一約略錐形的輪廓(tapered profile)，且該錐形輪廓40又包含一凸面曲線(convex curve)42。以另一角度來看，側壁子34的內側側壁雖貼附閘極結構28側壁呈現垂直狀態，但側壁子34的外側側壁，例如中間部36的外側側壁較佳呈現凹面曲線而底部38的外側側壁則呈現凸面曲線，或中間部36的外側側壁與底部38的外側側壁較佳呈現相反的曲線。
迨形成側壁子34後，可繼續進行後續電晶體製程，例如可進行一輕摻雜離子佈植製程，以於側壁子34兩側的基底12中形成一輕摻雜汲極30。輕摻雜離子佈植製程所植入之離子可依據電晶體的型態有所調整，例如若所製備的電晶體為NMOS電晶體時可將N型摻質植入基底，反之若製備的電晶體為PMOS電晶體時可將P型摻質植入基底12。需注意的是，本實施例雖於製作側壁子34後才於基底12中形成輕摻雜汲極30，但不侷限於此順序，形成輕摻雜汲極30的時間點又可選擇在形成側壁子34之前，此變化型也屬本發明所涵蓋的範圍。
隨後如第5圖所示，形成一主側壁子44於側壁子34側壁，然後再形成一源極/汲極區域46於主側壁子44兩側的基底12中。依據本發明之一實施例，形成主側壁子44的方法可比照前述形 成側壁子34，例如可先形成一襯墊層後再利用包含氟甲烷(CH3F)、氧氣(O2)及氦氣(He)的蝕刻氣體去除部分襯墊層以形成主側壁子44，且依此製程方法所形成的主側壁子44底部將同樣如側壁子34般具有一錐形輪廓(tapered profile)，且該錐形輪廓又包含一凸面曲線(convex curve)。
接著可形成一接觸洞蝕刻停止層48覆蓋閘極結構28，並形成一層間介電層50於接觸洞蝕刻停止層48上。需注意的是，形成接觸洞蝕刻停止層48之前又可視產品需求形成磊晶層與矽化金屬層等元件，由於該些製程乃此領域者所熟知技藝，在此不另加贅述。
之後可進行一金屬閘極置換(replacement metal gate)製程，將閘極結構28轉換為一金屬閘極。金屬閘極置換製程可包括先進行一選擇性之乾蝕刻或濕蝕刻製程，例如利用氨水(ammonium hydroxide,NH4OH)或氫氧化四甲銨(Tetramethylammonium Hydroxide,TMAH)等蝕刻溶液來去除閘極結構28中的矽層24以形成一凹槽(圖未示)。之後再形成一包含U型功函數金屬層52與低阻抗金屬層54的導電層56於該凹槽內，並再搭配進行一平坦化製程以形成一金屬閘極。
在本實施例中，功函數金屬層52較佳用以調整形成金屬閘極之功函數，使其適用於N型電晶體(NMOS)或P型電晶體(PMOS)。若電晶體為N型電晶體，功函數金屬層52可選用功函數為3.9電子伏特(eV)~4.3eV的金屬材料，如鋁化鈦(TiAl)、鋁化鋯(ZrAl)、鋁化鎢(WAl)、鋁化鉭(TaAl)、鋁化鉿(HfAl)或TiAlC(碳化 鈦鋁)等，但不以此為限；若電晶體為P型電晶體，功函數金屬層52可選用功函數為4.8eV~5.2eV的金屬材料，如氮化鈦(TiN)、氮化鉭(TaN)或碳化鉭(TaC)等，但不以此為限。功函數金屬層52與低阻抗金屬層54之間可包含另一阻障層(圖未示)，其中阻障層的材料可包含鈦(Ti)、氮化鈦(TiN)、鉭(Ta)、氮化鉭(TaN)等材料。低阻抗金屬層54則可選自銅(Cu)、鋁(Al)、鎢(W)、鈦鋁合金(TiAl)、鈷鎢磷化物(cobalt tungsten phosphide，CoWP)等低電阻材料或其組合。
以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。
12‧‧‧基底
14‧‧‧淺溝隔離
16‧‧‧介質層
20‧‧‧高介電常數介電層
22‧‧‧底部金屬阻隔層
30‧‧‧輕摻雜汲極
34‧‧‧側壁子
44‧‧‧主側壁子
46‧‧‧源極/汲極區域
48‧‧‧接觸洞蝕刻停止層
50‧‧‧層間介電層
52‧‧‧功函數金屬層
54‧‧‧低阻抗金屬層
56‧‧‧導電層

Claims (17)

  1. 一種製作半導體元件的方法，包含：提供一基底；形成一閘極結構於該基底上；沉積一襯墊層於該閘極結構與該基底上；以及利用一包含氟甲烷(CH3F)、氧氣(O2)及氦氣(He)之氣體進行蝕刻製程，以於該閘極結構旁形成一側壁子。
  2. 如申請專利範圍第1項所述之方法，其中形成該閘極結構前另包含形成一介質層於該基底上。
  3. 如申請專利範圍第1項所述之方法，其中形成該閘極結構之步驟包含：形成一堆疊結構於該基底上，該堆疊結構包含一高介電常數介電層、一底部金屬阻隔層設於該高介電常數介電層上、一矽層設於該底部金屬阻隔層上以及一硬遮罩設於該矽層上；以及圖案化該堆疊結構以形成該閘極結構。
  4. 如申請專利範圍第3項所述之方法，其中該底部金屬阻隔層包含氮化鈦。
  5. 如申請專利範圍第3項所述之方法，其中該矽層包含非晶矽或多晶矽。
  6. 如申請專利範圍第1項所述之方法，其中該襯墊層包含二氧化矽 或氮化矽。
  7. 如申請專利範圍第1項所述之方法，其中該側壁子之底部包含一錐形輪廓(tapered profile)。
  8. 如申請專利範圍第1項所述之方法，其中該錐形輪廓包含一凸面曲線(convex curve)。
  9. 如申請專利範圍第1項所述之方法，其中該側壁子包含一中間部分與一底部，且該底部之寬度大於該中間部之寬度。
  10. 一種半導體元件，包含：一基底；一閘極結構設於該基底上；以及一側壁子設於該閘極結構旁，其中該側壁子之底部具有一錐形輪廓。
  11. 如申請專利範圍第10項所述之半導體元件，另包含一介質層設於該閘極結構與該基底之間。
  12. 如申請專利範圍第11項所述之半導體元件，其中該介質層包含二氧化矽。
  13. 如申請專利範圍第10項所述之半導體元件，其中該閘極結構包含一圖案化之高介電常數介電層、一圖案化之底部金屬阻隔層設於該圖案化之高介電常數介電層上、一圖案化之矽層設於該圖案化之底部金屬阻隔層上以及一圖案化之硬遮罩設於該圖案化之矽層上。
  14. 如申請專利範圍第13項所述之半導體元件，其中該圖案化之底部金屬阻隔層包含氮化鈦。
  15. 如申請專利範圍第13項所述之半導體元件，其中該圖案化之矽層包含非晶矽或多晶矽。
  16. 如申請專利範圍第10項所述之半導體元件，其中該錐形輪廓包含一凸面曲線(convex curve)。
  17. 如申請專利範圍第10項所述之半導體元件，其中該側壁子包含一中間部與該底部，且該底部之寬度大於該中間部之寬度。
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