TW201246311A - Method for fabricating semiconductor device with enhanced channel stress - Google Patents

Method for fabricating semiconductor device with enhanced channel stress Download PDF

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Publication number
TW201246311A
TW201246311A TW100116938A TW100116938A TW201246311A TW 201246311 A TW201246311 A TW 201246311A TW 100116938 A TW100116938 A TW 100116938A TW 100116938 A TW100116938 A TW 100116938A TW 201246311 A TW201246311 A TW 201246311A
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Taiwan
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channel
forming
contact
layer
stress
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TW100116938A
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Chinese (zh)
Inventor
Ching-Sen Lu
Wen-Han Hung
Tsai-Fu Chen
Tzyy-Ming Cheng
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United Microelectronics Corp
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Priority to TW100116938A priority Critical patent/TW201246311A/en
Publication of TW201246311A publication Critical patent/TW201246311A/en

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Abstract

A method for fabricating a semiconductor device with enhanced channel stress is provided. The method includes the following steps. Firstly, a substrate is provided. Then, at least one source/drain region and a channel are formed in the substrate. A dummy gate is formed over the channel. A contact structure is formed over the source/drain region. After the contact structure is formed, the dummy gate is removed to form a trench.

Description

201246311 六、發明說明: 【發明所屬之技術領域】 本發明提供一種製造半導體裝置的方法,尤指製造具有增強 通道應力之半導體裝置的方法。 【先前技術】 隨著閘極長度縮小化的停頓以及新材料尚未被驗證,遷移率 調整工程已經縣積體電路性缺善的—個最重要貢獻者。而通 道之晶格應變(strain)已經普遍被用來在生產元件過程中增強遷移 率,其中應變矽晶格所能夠提供的電洞遷移率與電子遷移率可以 達到無應變矽的4倍與1.8倍。因此,設計者可透過修改電晶體的 構造,以便對N通道金氧半電晶體之通道施加拉伸應力㈣此 stress),或者是對P通道金氧半電晶體之通道施加壓縮應力 (compression stress)。因為拉伸通道可以改進電子的遷移率,而壓 縮通道可以改進電洞的遷移率。 而在進行高介電常數絕緣層/金屬閘極,以 下簡稱HK/MG)技術中之閘極後完成製程(以下簡稱⑽-㈣時, 由於是先將衫魏酿(dummy poly)移除後再填人金屬閘極,而 根據研究已知,將多晶矽假閘極(dummy poly)移除時會對通道之拉 伸應力(tensile stress)提供加強的效果。而如何運用此一特性來加強 元件性能,進而改善習用手段之缺失,係為發展本案之主要目的。 【發明内容】 3 201246311 去具有鮮職應力之半物裝置的方 法,此方法包含下财驟。錢,提供—基板。接著,於基板上 形成至少ϋ極結構、—通道區域,於通道 ,極結構。於臟極結構上方形成一接觸結構。接著方 觸結構後再將假閘極結構去除而形成一空間。 、成 q之實施例中提供上述基板係為提供上述石夕基 板’形成龜_結構係為形成—多晶碎假_結構。 在本發明之一實施例中,形成上述假閘極結構之步驟包含 於通道區域上方軸-介面層,於介面層上方形成—高 ^緣層,於高介電常數職層上方形成—轉金朗,以及於阻 障金屬層上方形成假閘極結構。 ’更包含下列步驟:於上述假閘極 以及於第一硬罩幕上方形成一第二 在本發明之一實施例中 結構上方形成一第一硬罩幕, 硬罩幕。 在本發明之—實闕中,更包含下列步驟:於上述假間極 =構之侧壁形成-第-間隙壁結構,以及於第—間隙壁結構之側 i形成一第二間隙壁結構。 姓在本發明之一實施例中,更包含下列步驟:於上述假閘極 結構與源/汲極結構上方形成一接觸侧中止層;以及於接觸侧 中止層上方形成一内層介電層。 在本發明之一實施例中,形成上述接觸結構之方法包含下 列步驟:對⑽介電層與賴侧巾止層進行_而形成一接觸 孔結構,於接觸孔結構中填入一阻障層;以及於阻障層上方填入 一接觸導體結構而形成接觸結構。 丸,在本發明之一實施例中,上述通道區域為一N型通道,阻 户早層之材質可為一拉伸材料(tensile material),‘·該拉伸材料可為 201246311 鈦、氮化鈦或其組合,而接觸導體結構之材質可為鎢。 在本發明之一實施例中,上述通道區域為—p 、 11早層之材質可為壓縮材料((;011^1^以1^111&拉11沮1),該炝通道,阻 鈕、氮化鈕或其組合,而接觸導體結構之材質可為鋼γ材料可為 在本發明之一實施例中,上述通道區域為一 觸孔結構之底部為一凹陷。 道’接 在本發明之一實施例中,上述通道區域為— 觸孔結構之底部為一凸起。 1通道’接 在本發明之一實施例中,上述通道區域為一 觸孔結構為長條狀。 i逋道,接 在本發明之一實施例中,上述通道區域為一p 觸孔結構為多個小孔組成。 迷、’接 在本發明之-實施例中,將上述假閘極結構201246311 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention provides a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device having enhanced channel stress. [Prior Art] With the pause in the reduction of gate length and the fact that new materials have not yet been verified, the mobility adjustment project has become the most important contributor to the lack of circuitability in the county. The lattice strain of the channel has been generally used to enhance mobility during the production of components, where the strain 矽 lattice can provide a hole mobility and electron mobility that can reach 4 times and 1.8 without strain. Times. Therefore, the designer can modify the structure of the transistor to apply tensile stress to the channel of the N-channel MOS transistor (4), or apply compressive stress to the channel of the P-channel MOS transistor. ). Because the stretching channel can improve the mobility of electrons, the compression channel can improve the mobility of the hole. When the process is completed after the gate of the high dielectric constant insulating layer/metal gate, referred to as HK/MG) (hereinafter referred to as (10)-(4), since the dummy poly is removed first. Refilling the metal gate, and according to research, removing the polysilicon polydole provides a reinforcing effect on the tensile stress of the channel. How to use this feature to strengthen the component The performance, and thus the improvement of the lack of conventional means, is the main purpose of the development of this case. [Summary of the Invention] 3 201246311 The method of removing the half-material device with fresh stress, the method includes the following financial. Money, providing - substrate. Then, Forming at least a drain structure, a channel region, a channel, and a pole structure on the substrate. A contact structure is formed above the dirty electrode structure, and then the dummy gate structure is removed after the square contact structure to form a space. In the embodiment, the substrate is provided to provide the above-described structure of the tortoise-forming structure to form a polycrystalline false structure. In an embodiment of the invention, the step of forming the dummy gate structure is In the upper-channel layer above the channel region, a high-layer layer is formed above the interface layer, forming a gold-transferred layer above the high dielectric constant layer, and forming a dummy gate structure over the barrier metal layer. The following steps: forming a first hard mask and a hard mask over the structure in the embodiment of the present invention by forming a second over the first gate and the first hard mask. In the present invention, Further, the method further comprises the steps of: forming a first-gap structure on the side wall of the dummy interpole; and forming a second spacer structure on the side i of the first-gap structure. The method further includes the steps of: forming a contact side stop layer over the dummy gate structure and the source/drain structure; and forming an inner dielectric layer over the contact side stop layer. In an embodiment of the invention, The method for forming the above contact structure comprises the steps of: forming a contact hole structure on the (10) dielectric layer and the sidewall spacer, filling a barrier layer in the contact hole structure; and filling the barrier layer Contact conductor The structure is formed into a contact structure. In one embodiment of the present invention, the channel region is an N-type channel, and the material of the early layer can be a tensile material, and the tensile material can be For the 201246311 titanium, titanium nitride or a combination thereof, the material of the contact conductor structure may be tungsten. In an embodiment of the invention, the material of the channel region of -p, 11 may be a compressed material ((; ^1^ is 1^111& pull 11 1), the channel, the button, the nitride button or a combination thereof, and the material of the contact conductor structure may be steel γ material may be in an embodiment of the invention, The channel region is a recess at the bottom of the contact structure. In one embodiment of the invention, the channel region is a bump at the bottom of the contact structure. 1 channel' In one embodiment of the invention, the channel region is elongated in a contact structure. In one embodiment of the present invention, the channel region is a p-contact structure composed of a plurality of small holes. In the embodiment of the present invention, the above dummy gate structure is

==層進行一平坦化製程,用以磨除部份之内層介C 填入-在金本=之Γ實施射’更包含刊娜:於上述空間中 在本發明之-實施例中,填入上述金屬結構之方人. 入一功函數金屬結構;以及於功函數金屬結二 方填入一金屬閘極結構。 傅上 在本發明之-實施例中,上述金屬閘極結構之材質為紹。 【實施方式】 201246311 於一基板ίο上已完成有通道區域10〇及源/汲極結構1(n,並於通 道區域100上方完成介面層(InterfaceLayer,簡稱江)1〇2、高介電 常數絕緣層103、阻障金屬層(Barrier metai)i〇4,一假閘極結構 105、第一硬罩幕1〇6與第二硬罩幕1〇7、第一間隙壁結構1〇8、 第二間隙壁結構109、接觸賴中止層(c〇ntact触St〇p Layer, 簡稱CESL)ll〇以及内層介電層(Inter㈣沉,簡稱 ILD)11卜其中基板10可以用矽基板來完成,介面層1〇2可以由 二氧化矽來完成,高介電常數絕緣層1〇3則可用二氧化铪(Hf〇2) 來tl成,至於阻障金屬層1〇4可為氮化鈦(TiN),假閘極結構1〇5 可為一多晶矽假閘極(dummy poly)結構,第一硬罩幕1〇6與第二硬 罩幕107分別由氮化矽與二氧化矽來完成,第一間隙壁結構1〇8 可由二氧化賴氮切之多層結構或是單由氮化絲完成,第二 間隙壁結構109則可由二氧化石夕與氮化石夕之多層結構來完成。再 者’接觸侧巾止層110可為具高拉伸應力之氮化_,而内層 介電層111則可為二氧化石夕。 再凊參見圖lb’其係對圖la中之結構進行一平坦化製程後所 形成結構之示意圖’其中平坦化製程可為—頂切(top_eut)化學機械 研磨法(ChemiCalMeChanicalPolishing,簡稱 CMp),除了磨除部份 内層介電層m、接觸_中止層11G外,_以將二氧化石夕所完 成之第一硬罩幕107去除而露出氮切所完成之第—硬罩幕伽。 接著進行臟極結構1G1上方之接觸結構製作,即侧出接 觸孔結構U2後,依續填人阻障層113與接辦體結構ιΐ4,進而 =成如圖之戶标。為能_接觸結構來調整通道之應力,可根 據不冋電性之通道來進行材料與形狀的選擇,例如N通道 電晶體之通道需要施加拉伸應力,因此轉層113可餘伸 201246311 結構m貝,!可用鶴來完成。至於p通道金氧半電晶體之通道,其 需要施加壓縮應力來加強性能,因此阻障層113可$壓__ (compressive materiai),例如鈕(Ta)或氮化鈕(TaN)或其組合來士 成’而接觸導體結構1M則可改用銅來完成。但若是在同一曰7 上之不同區域(N通道區與p通道區)使用不同材質之阻障層^ 接觸導體結構114 ’勢必會增加製造步驟而增加成本,因此也可使 用同-材質之阻障層113與同-材質之接觸導體結構114來完 2有區域的制結構,而只是改變源/汲極結構與接觸孔結構之形 圖2之所示,N通道金氧半電晶體21之源/汲極結構 2i 使接觸孔結構212之底部可深人職極結構 之接觸L士媒j 213之拉伸應力,至於Ρ通道金氧半電晶體22 Γ之底部則可為頂部凸起之源/沒極結_,用 =應力,而該凸起源/沒極結_可用一蠢 來完成,材質可用常見的石夕錯(siGe)來完成。當缺, 接i金氧半電晶體之接觸孔結構212可為長條狀㈣,用以增 加接觸面積而加強對通道之拉伸應力,) 之接觸孔結構222可為多個m》 通、域丰電曰曰體 拉伸應力。另外,也可透過用以避免對通道提供太多 制提供給通顧力,====_的大小來控 靠近P通道金氧半電曰曰h 縮應力之接觸孔結構可較 應力之接觸孔結構則可較遠離N通道:氧ί: 提供I㈣Ϊ而減少Ν通道受到_應力之不良影響。反之,可 極「進而構可較靠近Ν通道金氧半電晶體之間 結構則可較遠離道全’而提供拉伸應力之接觸孔 到拉伸應力之不良影響i 之·,躺減少P通道受 201246311 、再請參見圖id,其係於上述阻障層m與接觸_結構m 完成後’再接著將第-硬罩幕1〇6去除而露出多晶梦假閘極结構 105後,再將多晶德閘極結構105掏除而形成一空間,接著再於 該工間内填人金屬結構⑴,轉多晶魏難⑽移除時會對通 道之拉伸應力(tensile stress)提供加強的效果,因此當已經先完 觸結構對通道應力之調整後,再加上掏除多晶德間極結構ι〇5 對通道應力之再度加強,尤其是對N通道拉伸應力的加強,便可 以達到在不需增加製程步驟的情況下得到應力加強的效果,進而 ,善習用手段的缺失。至於金屬結構115可包含有敍刻阻播層 、功函數金屬結構1151與金屬閘極結構1152 =層⑽可為氮她(TaN),P通道金氧半電晶體之功函數! ^屬可為氮化鈦(TiN),而N通道金氧钱晶體之功函數金屬可 為銘化欽(TlA1),至於金射·結構可用雖1)來完成。 最後如圖1e所示,在金屬結構115與接觸導體結構114 方完成所f的雜導躲構110,錄彳趟 不同,故不再贅述。 、自$練已無 綜上所述,在本發明對技術進行改良後,已可有效 手段,問題。雖然本發明已以較佳實施例揭露如上,然其並非用 =定士發明,任何熟習此技藝者,在不脫離本發明之精神和範 =之申之更動與潤飾’因此本發明之保護範圍當視後 附之申6月專利乾圍所界定者為準。 【圖式簡單說明】 201246311 圖2之所示,其係本案中關於N通道金氧半雷曰矽 =極結構及P通道錢半電晶體之购凸二 【主要元件符號說明】 基板10 通道區域1〇〇 源/没極結構1〇1 介面層102 高介電常數絕緣層1〇3 阻障金屬層104 假閘極結構1〇5 第一硬罩幕106 第一硬罩幕1〇7 第一間隙壁結構108 第二間隙壁結構1〇9 接觸餘刻中止層110 内層介電層111 接觸孔結構112 阻障層113 接觸導體結構114 金屬結構115 钱刻阻擋層115〇 功函數金屬結構1151 金屬閘極結構1152 9 201246311 接觸導線結構116 N通道金氧半電晶體21 接觸孔結構212 源/汲極結構211 通道213 P通道金氧半電晶體22 接觸孔結構222 源/汲極結構221 通道223== The layer is subjected to a flattening process for removing a portion of the inner layer of the C-filling - the implementation of the shot at the gold plate = the more inclusive: in the above space - in the embodiment of the invention, The metal structure of the above metal structure is incorporated into a work function metal structure; and a metal gate structure is filled in the work function metal junction. In the embodiment of the present invention, the material of the above metal gate structure is as follows. [Embodiment] 201246311 has completed the channel region 10〇 and the source/drain structure 1 (n, and completes the interface layer (InterfaceLayer, referred to as Jiang) 1〇2, high dielectric constant on the channel region 100. The insulating layer 103, the barrier metal layer (Barrier metai) i〇4, a dummy gate structure 105, the first hard mask 1〇6 and the second hard mask 1〇7, the first spacer structure 1〇8, a second spacer structure 109, a contact stop layer (c〇ntact contact St〇p Layer, abbreviated as CESL) 11 and an inner dielectric layer (Inter), wherein the substrate 10 can be completed by using a germanium substrate. The interface layer 1〇2 can be completed by cerium oxide, and the high dielectric constant insulating layer 1〇3 can be formed by using cerium oxide (Hf〇2), and the barrier metal layer 1〇4 can be titanium nitride ( TiN), the dummy gate structure 1〇5 may be a polysilicon dummy poly structure, and the first hard mask 1〇6 and the second hard mask 107 are respectively made of tantalum nitride and hafnium oxide. The first spacer structure 1〇8 may be formed by a multilayer structure of diazonium dinitride or by a single nitride wire, and the second spacer structure 109 may be made of a dioxane. The stone eve and the nitrite layer are completed in a multi-layer structure. Further, the contact side towel layer 110 may be nitrided with high tensile stress, and the inner dielectric layer 111 may be sulphur dioxide. Figure lb' is a schematic diagram of a structure formed by performing a planarization process on the structure in Fig. 1 'where the planarization process can be - top_eut chemical mechanical polishing (CMp), except for the grinding part In addition to the inner dielectric layer m and the contact/stop layer 11G, the first hard mask 107 completed by the oxidizing stone is removed to expose the first hard mask glaze completed by the nitrogen dicing. The contact structure above 1G1 is made, that is, after the side contact hole structure U2 is formed, the barrier layer 113 and the connection body structure ιΐ4 are continuously filled, and then the figure is as shown in the figure. The stress of the channel is adjusted for the contact structure. The material and shape can be selected according to the channel of non-electricity. For example, the channel of the N-channel transistor needs to apply tensile stress, so the layer 113 can be extended to the 201246311 structure m shell, which can be completed by the crane. As for p Channel MOS semi-transistor The track needs to apply compressive stress to enhance the performance, so the barrier layer 113 can be pressed __ (compressive materiai), such as button (Ta) or nitride button (TaN) or a combination thereof, and contact conductor structure 1M It can be done by using copper instead. However, if different layers of the same layer (N-channel area and p-channel area) are used, the barrier layer of different materials ^ contact conductor structure 114' will inevitably increase the manufacturing steps and increase the cost. It is also possible to use the same-material barrier layer 113 and the same-material contact conductor structure 114 to complete the structure of the region, but only to change the source/drain structure and the contact hole structure as shown in FIG. 2, N The source/drain structure 2i of the channel MOS transistor 21 enables the bottom of the contact hole structure 212 to be in contact with the tensile stress of the L-media j 213, as the Ρ channel MOS transistor 22 Γ The bottom can be the source of the top bump / no pole junction _, with = stress, and the source / no pole _ can be done with a stupid, the material can be done with the common Si Xi. When missing, the contact hole structure 212 of the NMOS transistor may be elongated (four) for increasing the contact area to enhance the tensile stress on the channel, and the contact hole structure 222 may be a plurality of m", Domain abundance of carcass tensile stress. In addition, it can also be used to avoid over-supply of the channel to provide the utilization force, and the size of the ====_ can be controlled to contact the contact hole structure of the P-channel MOSFET. The pore structure can be farther away from the N channel: oxygen ί: provides I (four) Ϊ and reduces the Ν channel is adversely affected by _ stress. On the other hand, it can be extremely "further configured to be closer to the Ν channel, the structure between the MOS and the semi-transistor can be farther away from the channel" and provide the tensile stress to the contact hole to the tensile stress. According to 201246311, please refer to the figure id, after the barrier layer m and the contact_structure m are completed, and then the first hard mask 1〇6 is removed to expose the polycrystalline dream gate structure 105, and then The polycrystalline gate structure 105 is removed to form a space, and then the metal structure (1) is filled in the chamber. When the polycrystalline Wei (10) is removed, the tensile stress of the channel is strengthened. The effect, therefore, after the adjustment of the channel stress has been completed by the structure, and the removal of the polycrystalline inter-electrode structure ι〇5 to reinforce the channel stress, especially the strengthening of the N-channel tensile stress, The effect of stress enhancement can be achieved without increasing the number of process steps, and further, the lack of good use means. As for the metal structure 115, the metal structure 115 can include a scratch-resistant layer, a work function metal structure 1151 and a metal gate structure 1152 = Layer (10) can be nitrogen (TaN), P The function of the gold oxide semi-transistor! ^ can be titanium nitride (TiN), and the work function metal of the N-channel gold-oxygen crystal can be Minghuaqin (TlA1), as for the gold shot structure available 1) Finally, as shown in FIG. 1e, the hybrid structure of the f structure is completed in the metal structure 115 and the contact conductor structure 114, and the recording is different, so it will not be described again. After the improvement of the technology of the present invention, an effective means and a problem have been made. Although the present invention has been disclosed in the preferred embodiment as above, it is not invented by the company, and anyone skilled in the art can be without departing from the invention. The spirit and the norm of the application of the change and refinement 'The scope of protection of the present invention is subject to the definition of the patent application in the attached June. [Simplified illustration] 201246311 Figure 2, which is in the case About N-channel gold oxide half-throat = pole structure and P-channel money semi-transistor purchase convex two [main component symbol description] substrate 10 channel area 1 source / no-pole structure 1〇1 interface layer 102 high dielectric Constant insulating layer 1〇3 barrier metal layer 104 false gate structure 1〇5 first hard Curtain 106 first hard mask 1〇7 first spacer structure 108 second spacer structure 1〇9 contact residual stop layer 110 inner dielectric layer 111 contact hole structure 112 barrier layer 113 contact conductor structure 114 metal structure 115 Money engraving barrier 115 〇 work function metal structure 1151 metal gate structure 1152 9 201246311 contact wire structure 116 N channel MOS semi-transistor 21 contact hole structure 212 source / drain structure 211 channel 213 P channel MOS semi-transistor 22 Contact hole structure 222 source/drain structure 221 channel 223

Claims (1)

201246311 七、申請專利範圍: 製造具有湘财應力之半物裝置的綠,财法包含下 提供一基板; 於該基板上形絲少聽結構、—通道區域; 於該通道區域上方形成一假閘極結構;以及 於該源/汲極結構上方形成一接觸結構; 形成該接觸結構後再將該假閘極結構去除而形成一空間。 專纖Μ1斯狀製造具有增強通觀力之半導體 裝置的方法’其巾提供該基㈣為提供—絲板,形成該 結構係為形成一多晶矽假閘極結構。 X ”。 3.如申請專概ϋ第丨摘述之製造具 裝置的方法,其巾形成該假_結構之步驟包含,力之+導體 於該通道區域上方形成一介面層; 於該介面層上方形成一高介電常數絕緣層; 於該高介f常數絕緣層上方形成—阻障金屬層;以及 於該阻障金屬層上方形成該假閘極結構。 之半導體 4.如申請專·圍第丨項所述之製造具有增強通道應力 裝置的方法’其中更包含下列步驟: 於該假閘極結構上方形成一第一硬罩幕;以及 於該第一硬罩幕上方形成一第二硬罩幕。 之半導體 ^如申請專概圍第1項所述之製造具有增強通道應力 裝置的方法,其中更包含下列步驟: 201246311 於該假閘極結構之側壁形成一第一間隙壁結構;以及 於該第-間隙壁結構之側壁形成一第二間隙壁結構。 侧崎版半導體 層;以^Ί閘極結構與該源7錄結構上方形成—接職刻令止 於該接觸糊中止層上方形成—内層介電層。 第6項所述之製造具有增強通道應力之铸體 其中形成該接觸結構之方法包含下列步驟: 孔結:該内層介電層與該接觸蝕刻中止層進行蝕刻而形成-接觸 於該接觸孔結構中填入一阻障層;以及 於該阻障層上方填人—接觸導體結構而形成該接觸結構。 利ΐ圍第7項所述之製造具有職通道應力之铸體 一拉伸材料(tensile material)。 丨㈣之材質為 第8項所述之製造具有增強通道應力之半導體 導體結構之材質^拉刪域、氮賴其組合,而該接觸 10.如申請專利範圍第6 區域為一 P型通道, 項所述之通道應力調整方法,其中該通道 °亥阻卩早層之材質為壓縮材料(compressive 12 201246311 material)。 11.如申請專利範圍第10項所述之製造具有增強通道應力之半 體裝置的方法,其中該壓縮材料為钽、氮化钽或其組ς, 觸導體結構之材質為銅。 λ 申請專截Μ 6綱狀製造財職麟應力之 部為其中該通道區域為—Ν型通道,該接觸孔結構之底 其中該通道區一通道,該接觸孔= 第6項之製造具有通道應力之半導體 條狀。 N型通道,該接觸孔結構為長 15. 如申請專利範圍第6項所述 裝置的方法,其中該通道區域為一增強通道應力之半導體 個小孔組成。 ‘、、、P型通道’該接觸孔結構為多 16. 如申請專利範圍第6項所述 生 裝置的方法,其帽該假_結='、㉟強通道應力之半導體 行-平坦化製程,用以磨除部=除之方法包含下列步驟:進 止層。 之5亥内層介電層與該接觸蝕刻中 201246311 1λ如申料概園第】項所述之製造具有增強通道應力 裝置的方 >办,盆cb ® ΐί7 nr r丨丨_it ^ 裝置的方法,射更包含下列步驟··於該空㈣填入 ja^ 體 •金屬結構 18.如申請專利棚第17項所述之通道應力調整方法, 金屬結構之方法包含: 其中填入該 於該空間填入一功函數金屬結構;以及 於該功函數金屬結構上方填人—金仙極結構。 19.如申請專利範圍第18項所述之製造具有增強通道應力 體裝置的方法’其中該金屬閘極結構之材質為紹。 之半導 八、圖式201246311 VII. Patent application scope: Green for manufacturing a half-object device with Xiangcai stress, the financial method includes providing a substrate; on the substrate, the wire is less listening structure, the channel region; forming a false gate above the channel region a pole structure; and forming a contact structure over the source/drain structure; forming the contact structure and removing the dummy gate structure to form a space. A method of fabricating a semiconductor device having enhanced visibility is provided by a towel which provides the substrate (4) to provide a wire plate which is formed to form a polycrystalline pseudo gate structure. X ”. 3. The method of manufacturing the device according to the application of the specification, wherein the step of forming the dummy structure comprises forming a dielectric layer over the channel region; Forming a high dielectric constant insulating layer thereon; forming a barrier metal layer over the high dielectric constant insulating layer; and forming the dummy gate structure over the barrier metal layer. The method of manufacturing a device having an enhanced channel stress as described in the above item, further comprising the steps of: forming a first hard mask over the dummy gate structure; and forming a second hard layer over the first hard mask A method of fabricating a device having an enhanced channel stress as described in claim 1, further comprising the steps of: 201246311 forming a first spacer structure on a sidewall of the dummy gate structure; Forming a second spacer structure on the sidewall of the first spacer structure. The side-span semiconductor layer; forming a gate structure and a top surface of the source 7 recording structure to terminate the contact paste Forming an inner dielectric layer over the layer. The method of manufacturing a casting having enhanced channel stress as described in claim 6 includes the following steps: hole junction: the inner dielectric layer and the contact etch stop layer are etched Forming and contacting the contact hole structure with a barrier layer; and filling the contact layer with the contact conductor structure to form the contact structure. The manufacturing of the contact channel described in claim 7 The casting material is a tensile material. The material of the material (4) is the material of the semiconductor conductor structure having the enhanced channel stress described in Item 8, the combination of the nitrogen and the nitrogen, and the contact 10. The sixth area of the patent application scope is a P-type channel, and the channel stress adjustment method described in the item, wherein the material of the channel is a compressive material (compressive 12 201246311 material). A method of fabricating a half-body device having enhanced channel stress, wherein the compressive material is tantalum, tantalum nitride or a group thereof, and the material of the contact conductor structure is copper. Please make a special section of the 6th dimension to create a section of the financial stress. The channel area is a Ν-type channel. The bottom of the contact hole structure is a channel of the channel area. The contact hole = the manufacturing of the sixth item has channel stress. The method of the device of claim 6, wherein the channel region is a semiconductor aperture that enhances channel stress. ', ,, P-type channel 'the contact hole structure is more than 16. The method of the raw device described in claim 6 of the patent, the cap of the fake _ junction = ', 35 strong channel stress semiconductor line - flattening process for grinding The division = division method includes the following steps: the entry layer. The dielectric layer of the 5th inner layer and the side of the contact etching process described in the article 201246311 1λ, as described in the item 】], the device having the enhanced channel stress device, the pot cb ® ΐί7 nr r丨丨_it ^ device The method further comprises the following steps: filling the ja^ body and the metal structure in the empty space (4). The channel stress adjustment method according to claim 17 of the patent application shed, the method of the metal structure comprises: filling in the The space is filled with a work function metal structure; and the metal structure is filled above the work function metal structure. 19. A method of fabricating a device having an enhanced channel stress device as described in claim 18, wherein the material of the metal gate structure is. Semi-guided
TW100116938A 2011-05-13 2011-05-13 Method for fabricating semiconductor device with enhanced channel stress TW201246311A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI671805B (en) * 2014-06-18 2019-09-11 聯華電子股份有限公司 Semiconductor device and method for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TWI671805B (en) * 2014-06-18 2019-09-11 聯華電子股份有限公司 Semiconductor device and method for fabricating the same

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