TWI591783B - 晶片封裝體及其製造方法 - Google Patents

晶片封裝體及其製造方法 Download PDF

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Publication number
TWI591783B
TWI591783B TW103113345A TW103113345A TWI591783B TW I591783 B TWI591783 B TW I591783B TW 103113345 A TW103113345 A TW 103113345A TW 103113345 A TW103113345 A TW 103113345A TW I591783 B TWI591783 B TW I591783B
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Taiwan
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solder balls
size
wafer
chip package
solder
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TW103113345A
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English (en)
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TW201440187A (zh
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黃玉龍
張恕銘
劉滄宇
何彥仕
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精材科技股份有限公司
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Publication of TW201440187A publication Critical patent/TW201440187A/zh
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Description

晶片封裝體及其製造方法
本發明係有關於半導體裝置，且特別是有關於一種晶片封裝體及其製造方法。
晶片封裝製程是形成電子產品過程中之一重要步驟。晶片封裝體除了將晶片保護於其中，使免受外界環境污染外，還提供晶片內部電子元件與外界之電性連接通路。
由於電子產品持續縮小化，形成更多功能且體積更小的晶片封裝體已成為重要課題。然而，更多功能且體積更小的晶片封裝體具有更密集的電路設計，使得晶片的翹曲更加嚴重，導致晶片上之複數銲球無法每一顆皆順利的接合至封裝基材上。因此，使得晶片封裝體的耐用性不佳，並降低晶片效能。
本發明實施例係提供一種晶片封裝體，包括：一封裝基材；一晶片；以及複數個銲球，設於此封裝基材及此晶片之間，以將此晶片接合至此封裝基材上，其中這些銲球包含一第一尺寸及不同於此第一尺寸之第二尺寸。
本發明實施例更提供一種晶片封裝體之製造方法，包括：於一晶圓上形成複數晶片；量測此晶圓上之這些晶片之翹曲；裝設複數銲球於此晶圓上之這些晶片上，其中這些銲球包含一第一尺寸及一第二尺寸，且這些具有此第一尺寸之銲球及這些具有此第二尺寸之銲球係依照此翹曲程度之量測結果分佈；接合此晶圓至一封裝基材上；以及切割此晶圓，形成複數晶片封裝體。
本發明實施例又提供一種晶片封裝體之製造方法，包括：於一晶圓上形成複數晶片；量測此晶圓上之這些晶片之翹曲；切割此晶圓，形成複數分離的晶片；裝設複數銲球於這些分離的晶片上，其中這些銲球包含一第一尺寸及一第二尺寸，且這些具有此第一尺寸之銲球及這些具有此第二尺寸之銲球係依照此翹曲程度之量測結果分佈；以及接合這些分離的晶片此晶圓至一基材上。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂，下文特舉出較佳實施例，並配合所附圖式，作詳細說明如下：
100‧‧‧半導體基材
100a‧‧‧半導體基材之表面
101‧‧‧量測
102‧‧‧晶片
104‧‧‧銲球
104a‧‧‧銲球
104b‧‧‧銲球
104c‧‧‧銲球
104a’‧‧‧銲球
104b’‧‧‧銲球
104c’‧‧‧銲球
120‧‧‧封裝基材
140‧‧‧晶片封裝體
304a’‧‧‧銲球
304b’‧‧‧銲球
304c’‧‧‧銲球
340‧‧‧晶片封裝體
440‧‧‧晶片封裝體
d1‧‧‧間距
d2‧‧‧間距
SC‧‧‧切割道
第1A~1E圖顯示為根據本發明一實施例之以晶圓級封裝製程所製造之晶片封裝體之製程剖面圖。
第2圖顯示為晶片裝設銲球後之仰視圖。
第3圖顯示根據本發明另一實施例之以晶圓級封裝製程所製造之晶片封裝體之製程剖面圖。
第4A~4B圖顯示為根據本發明一實施例之以晶片級封裝製程所製造之晶片封裝體之製程剖面圖。
以下將詳細說明本發明實施例之製作與使用方式。然應注意的是，本發明提供許多可供應用的發明概念，其可以多種特定形式實施。文中所舉例討論之特定實施例僅為製造與使用本發明之特定方式，非用以限制本發明之範圍。此外，在不同實施例中可能使用重複的標號或標示。這些重複僅為了簡單清楚地敘述本發明，不代表所討論之不同實施例及/或結構之間必然具有任何關連性。再者，當述及一第一材料層位於一第二材料層上或之上時，包括第一材料層與第二材料層直接接觸或間隔有一或更多其他材料層之情形。
本發明一實施例之晶片封裝體可用以封裝近接感測器(proximity sensor)。然其應用不限於此。其中上述晶圓級封裝製程主要係指在晶圓階段完成封裝步驟後，再予以切割成獨立的封裝體，然而，在一特定實施例中，例如將已分離之半導體晶片重新分布在一承載晶圓上，再進行封裝製程，亦可稱之為晶圓級封裝製程。另外，上述晶圓級封裝製程亦適用於藉堆疊(stack)方式安排具有積體電路之多片晶圓，以形成多層積體電路(multi-layer integrated circuit devices)之晶片封裝體。在一實施中，上述切割後的封裝體係為一晶片尺寸封裝體(CSP；chip scale package)。晶片尺寸封裝體(CSP)之尺寸可僅略大於所 封裝之晶片。例如，晶片尺寸封裝體之尺寸不大於所封裝晶片之尺寸的120%。
第1A~1E圖顯示為根據本發明一實施例之以晶圓級封裝製程所製造之晶片封裝體之製程剖面圖。如第1A圖所示，提供半導體基材100，其具有表面100a。半導體基材100例如可為半導體晶圓。因此，標號100亦可代表半導體晶圓。適合的半導體晶圓可包括矽晶圓、矽鍺晶圓、砷化鎵晶圓、或其相似物。
半導體基材100上可包含複數晶片102形成於其上。在本發明之實施例中，晶片102可包含主動元件或被動元件(active or passive elements)、數位電路或類比電路(digital or analog circuits)等積體電路的電子元件(electronic components)，例如是有關於光電元件(opto electronic devices)、微機電系統(Micro Electro Mechanical System；MEMS)、微流體系統(micro fluidic systems)、或利用熱、光線及壓力等物理量變化來測量的物理感測器(Physical Sensor)。特別是可選擇使用晶圓級封裝(wafer scale package；WSP)之晶片。例如，可側用晶圓級封裝之影像感測元件、發光二極體(light-emitting diodes；LEDs)、太陽能電池(solar cells)、射頻元件(RF circuits)、加速計(accelerators)、陀螺儀(gyroscopes)、微制動器(micro actuators)、表面聲波元件(surface acoustic wave devices)、壓力感測器(process sensors)噴墨頭(ink printer heads)、或功率金氧半場效電晶體模組(power MOSFET modules)等半 導體晶片。在本實施例中，這些晶片102可由任意合適之製程製造，例如晶圓級的CMOS製程。
由於每一晶片102上係已搭載各種功能性電路，隨這些電路的設計，晶片102係會具有一定程度的翹曲，例如晶片外側向上翹曲、晶片外側向下翹曲或其他不規則的翹曲。一般而言，為了分散晶片102翹曲所導致的應力，半導體基材100亦會具有與晶片102相對應的翹曲形狀。在某些實施例中，半導體基材100上的複數晶片102可為具有相同功能或相同設計的晶片。因此，以上視角度而言，半導體基材100上的每一晶片102係可視為一重複單元，連續地在半導體基材100上排列。也就是說，搭載晶片102的半導體基材100可如第1A圖所示，具有實質上為波浪狀的表面100a。需注意的是，第1A圖中僅顯示晶片外側向下翹曲之實施例，但本領域具有通常知識者應可由此以公知常識推知半導體基材100於晶片102之外側向上翹曲或其他不規則的翹曲時的表面波浪形狀。此外，在一實施例中，晶片102與晶片102之間可具一間隔(未顯示)，以作為切割道SC。
接著，參見第1B圖，其顯示為量測101各晶片102之表面100a的電路分佈的資訊。在一實施例中，可以表面散射量測儀、或其他量測方式量測101。值得注意的是，在此由量測各晶片102之表面100a的電路分佈的資訊，係可計算出半導體基材100經切割後之各分離的晶片102可能的翹曲形狀及程度。
接著，參見第1C圖，其顯示依照前述之計算得到之資訊，將銲球104設於半導體基材100上之各晶片102上。在一實施例中，銲球104可至少包含一第一尺寸及一不同於第一尺寸之第二尺寸。銲球104亦甚至可依據需要具有各種尺寸，例如更包含不同於第一尺寸及第二尺寸之第三尺寸或更多尺寸。在一實施例中，具有第一尺寸之銲球104a及具有第二尺寸之銲球104b之尺寸大小係與晶片之翹曲程度及方向具有正向或反向關聯。或者，銲球104可至少包含一第一高度及一不同於第一高度之第二高度及其他更多不同的高度(以下為便於說明，各種不同高度均一併以各種不同尺寸通稱)。銲球104可包含共晶銲球、無鉛銲球、或前述之組合。例如，在某些實施例中，可依照前述之計算得到之資訊，將不同尺寸的銲球104a、104b分別設置於晶片102將會相對翹曲較輕微及相對翹曲較劇烈的部分上，或反之亦可。因此，在每一晶片102上，係至少具有第一尺寸之銲球104a及具有第二尺寸之銲球104b。或者，在某些實施例中，可設置有第三尺寸之銲球104c及其他更多尺寸的銲球。各尺寸之銲球之數量可依晶片翹曲程度或區域有不同的比例，並可依照實際需求做任意調整。
在某些實施例中，相鄰具有第一尺寸之銲球104a之間的間距d1係可不同於相鄰具有第二尺寸之銲球104b之間的間距d2。例如，參見第2圖，其係顯示晶片102在經第1C圖示之裝設銲球104後之仰視圖。如第2圖所示，具有第一尺寸之銲球104a之間的間距d1係不同於其與該些 具有該第二尺寸之銲球104b的間距(未顯示)。然而，可知的是，上述間距的配置係是依照半導體基材100經切割後，晶片102之翹曲程度及形狀決定。
例如，第1C圖係顯示晶片外側向下翹曲之實施例，其中具有第一尺寸之銲球104a可裝設於靠近晶片102之靠近中央處，而具有第二尺寸之銲球104b可裝設於具有第一尺寸之銲球104b可裝設於靠近晶片102之靠近外側的部分上，且可有第三尺寸之銲球104c設置於靠近晶片102之最外側。在此實施例中，第一尺寸係大於第二尺寸，且第二尺寸係大於第三尺寸。
如第2圖所示，具有第二尺寸之銲球104b及具有第三尺寸之銲球104c係可裝設靠近晶片102之角落處。或者，在其他實施例中，具有第二尺寸之銲球104b及及具有第三尺寸之銲球104c可以單排或多排的方式，沿同心環繞裝設於靠近晶片102中央處之銲球104a(未顯示)。
在本實施例中，具有第一尺寸之銲球104a可提供主要的支撐及傳遞訊號的功能。具有第二尺寸之銲球104b、具有第三尺寸之銲球104c及具有其他尺寸之銲球亦可具有支撐及傳遞電子訊號的功能。或者，在其他實施例中，具有第二尺寸之銲球104b、具有第三尺寸之銲球104c及具有其他尺寸之銲球，用以作為加強支撐、補償應力或導熱，但未連接至晶片102中的功能性電路。
接著，參見第1D圖，透過銲球104a將半導體基材100放置至封裝基材120上，並沿半導體基材100上之切割 道SC對半導體基材100及封裝基材120作切割，以得到複數分離的晶片封裝體140。封裝基材120可例如為印刷電路板、具電性連接功能之矽基板、3D封裝基板等。經切割後，各分離的晶片102係會因其搭載的功能性電路的分佈而導致翹曲。因此，銲球104a、104b、104c係會與封裝基材120緊密接合。
接著，參見第1E圖，對銲球104a、104b、104c進行一回銲製程，使銲球104a、104b、104c因重力而產生形狀變化，形成銲球104a’、104b’、104c’以緊密接合晶片102及封裝基材120。例如，靠近晶片102中央處之銲球104a’係因承受晶片102之主要重量而相對於未回銲前之銲球104a變得較為寬矮。靠近晶片102外側之銲球104b’及104c’係因與封裝基材120具有較大的間距而相對於未回銲前之銲球104b、104c變得較為高窄。
如此，晶片102本身翹曲的問題係可透過銲球104a’、104b’及104c’的形變後的尺寸、裝設位置及間距調整得到補償。銲球104a’、104b’及104c’可具有相同高度。此外，銲球104a’之寬度係大於銲球104b’之寬度，且銲球104b’之寬度係大於銲球104c’之寬度。如此，可減緩或甚至消除晶片102之翹曲問題，並減少晶片102破裂的機率。也就是說，晶片102的表面係為實質上平坦的表面。
因此，依照第1A~1E圖所示之實施例所提供之製造方法，不僅可提升良率，且所形成之晶片封裝體140 的耐用性及效能均能顯著改善。
第3圖係顯示依照第1A~1E圖所示之實施例所提供之製造方法所製造之晶片封裝體340，然此晶片封裝體340之晶片102外側係承受晶片的主要重量。在此實施例中，與前述實施例相同之標號代表相似或相同的元件，因此這些具有相同之標號之元件之材料及其製造方法可參見第1A至1E圖所示之實施例中的相關討論。
在此實施例中，具有第一尺寸之銲球304a’可裝設於靠近晶片102之靠近中央處，具有第二尺寸之銲球304b’可裝設於靠近晶片102之靠近外側的部分上，且可有第三尺寸之銲球304c’設置於靠近晶片102之靠近最外側的部分上。同前述實施例，具有第二尺寸之銲球304b’及具有第三尺寸之銲球304c’係可裝設靠近晶片102之角落處。或者，在其他實施例中，具有第二尺寸之銲球304b’及及具有第三尺寸之銲球104c可以單排或多排的方式，沿同心環繞裝設於靠近晶片102中央處之銲球304a’(未顯示)。在此實施例中，銲球304a’、304b’及304c’之高度係實質上相同。銲球304a’之寬度係小於銲球304b’之寬度，且銲球304b’之寬度係小於銲球304c’之寬度。
如此，晶片102本身翹曲的問題係可透過銲球104a’、104b’及104c’的形變後的尺寸、裝設位置位及間距調整得到補償。因此，可減緩或甚至消除晶片102之翹曲問題，並減少晶片102破裂的機率。也就是說，晶片102的表面係為實質上平坦的表面。在此實施例中，具有第一 尺寸之銲球304a’可提供主要的支撐及傳遞訊號的功能。具有第二尺寸之銲球304b’、具有第三尺寸之銲球304c’及具有其他尺寸之銲球亦可具有支撐及傳遞電子訊號的功能。或者，在其他實施例中，具有第二尺寸之銲球304b’、具有第三尺寸之銲球304c’及具有其他尺寸之銲球，用以作為加強支撐、補償應力或導熱，但未連接至晶片102中的功能性電路。
第4A~4B圖顯示為根據本發明另一實施例之以晶片級封裝製程所製造之晶片封裝體之製程剖面圖。在本實施例中，在此實施例中，與前述實施例相同之標號代表相似或相同的元件，因此這些具有相同之標號之元件之材料及其製造方法可參見第1A至1E圖所示之實施例中的相關討論。
接著，參見第4A圖，可依照計算得到之資訊，將銲球104設於各分離的晶片102上。在一實施例中，銲球104可至少包含一第一尺寸及一不同於第一尺寸之第二尺寸。在一實施例中，具有第一尺寸之銲球104a及具有第二尺寸之銲球104b之尺寸大小係與晶片之翹曲程度及方向具有正向或反向關聯。或者，銲球104亦甚至可依據需要具有各種尺寸，例如更包含第三尺寸或更多尺寸。例如，在某些實施例中，可依照前述之計算得到之資訊，將不同尺寸的銲球104a、104b分別設置於晶片102將會相對翹曲較輕微的部分上及相對翹曲較劇烈的部分上，且反之亦可。因此，在每一晶片102上，係至少具有第一尺寸之銲球104a及具有 第二尺寸104b之銲球。或者，在某些實施例中，可設置有第三尺寸之銲球104c及其他更多尺寸的銲球。各尺寸之銲球之數量可依晶片翹曲程度或區域有不同的比例，並可依照實際需求做任意調整。
在某些實施例中，相鄰具有第一尺寸之銲球104a之間的間距d1係可不同於相鄰具有第二尺寸之銲球104b之間的間距d2。上述間距的配置係是依照半導體基材100經切割後，晶片102之翹曲程度及形狀決定。
接著，參見第4B圖，各自接合該些分離的晶片102至對應的封裝基材120上，以形成複數晶片封裝體440。此外，對銲球104a、104b、104c進行回銲製程，使銲球104a、104b、104c因重力而產生形狀變化，形成銲球104a’、104b’、104c’以緊密接合晶片102及封裝基材120。例如，靠近晶片102中央處之銲球104a’係因承受晶片102之主要重量而相對於未回銲前之銲球104a變得較為寬矮。靠近晶片102外側之銲球104b’及104c’係因及與封裝基材120具有較大的間距而相對於未回銲前之銲球104b及104c變得較為高窄。例如，銲球104a’之高度係小於銲球104b’之高度，且銲球104b’之高度係小於銲球104c’之高度。銲球104a’之寬度係大於銲球104b’之寬度，且銲球104b’之寬度係大於銲球104c’之寬度。
如此，晶片102本身翹曲的問題係可透過銲球104a’、104b’及104c’的形變後的尺寸、裝設位置及間距調整得到補償。例如，銲球104a’、104b’及104c’之 高度係實質上相同。銲球104a’之寬度係大於銲球104b’之寬度，且銲球104b’之寬度係大於銲球104c’之寬度。因此，可減緩或甚至消除晶片102之翹曲問題，並減少晶片102破裂的機率。也就是說，晶片102的表面係為實質上平坦的表面。因此，依照第1A~1E圖所示之實施例所提供之製造方法，不僅可提升良率，且所形成之晶片封裝體440的耐用性及效能均能顯著改善。
雖然本發明已以數個較佳實施例揭露如上，然其並非用以限定本發明，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
102‧‧‧晶片
104a’‧‧‧銲球
104b’‧‧‧銲球
104c’‧‧‧銲球
120‧‧‧封裝基材
140‧‧‧晶片封裝體

Claims (19)

  1. 一種晶片封裝體，包括：一封裝基材；一晶片；以及複數個銲球，設於該封裝基材及該晶片之間，以將該晶片接合至該封裝基材上，其中該些銲球中的每一個皆具有向外突出之側壁，其中該些銲球包含一第一尺寸及不同於該第一尺寸之第二尺寸，且該些具有該第二尺寸之銲球相對於該些具有該第一尺寸之銲球係設置於靠近該晶片之角落的位置，其中該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球之尺寸大小係與量測該晶片表面之電路分佈所得出的晶片翹曲程度及方向有關，且其中該些具有該第一尺寸之銲球的剖面寬度大於該些具有該第二尺寸之銲球的剖面寬度。
  2. 如申請專利範圍第1項所述之晶片封裝體，其中該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球之尺寸大小係與該晶片翹曲程度及方向具有正向或反向關聯。
  3. 如申請專利範圍第1項所述之晶片封裝體，其中該些具有該第一尺寸之銲球之第一高度與該些具有該第二尺寸之銲球之第二高度相同。
  4. 如申請專利範圍第1項所述之晶片封裝體，其中該些具有第一尺寸之銲球之間的間距係不同於該些具有該第二尺寸之銲球之間的間距。
  5. 如申請專利範圍第1項所述之晶片封裝體，其中該些具有 第一尺寸之銲球之間的間距係不同於該些具有第一尺寸之銲球與該些具有該第二尺寸之銲球的間距。
  6. 如申請專利範圍第1項所述之晶片封裝體，其中該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球係皆電性連接該晶片至該封裝基材。
  7. 如申請專利範圍第1項所述之晶片封裝體，其中該些具有該第一尺寸之銲球係皆電性連接該晶片至該封裝基材，且該些具有該第二尺寸之銲球係為虛置銲球。
  8. 一種晶片封裝體之製造方法，包括：於一晶圓上形成複數晶片；量測該晶圓上之該些晶片的電路分佈；裝設複數銲球於該晶圓上之該些晶片上，其中該些銲球中的每一個皆具有向外突出之側壁，其中該些銲球包含一第一尺寸及一第二尺寸，且該些具有該第二尺寸之銲球相對於該些具有該第一尺寸之銲球係設置於靠近該晶片之角落的位置，其中該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球之尺寸大小係與量測該晶片表面之電路分佈所得出的晶片翹曲程度及方向有關，且其中該些具有該第一尺寸之銲球的剖面寬度大於該些具有該第二尺寸之銲球的剖面寬度，且該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球係依照量測結果分佈；接合該晶圓至一封裝基材上；以及切割該晶圓，形成複數晶片封裝體。
  9. 如申請專利範圍第8項所述之晶片封裝體之製造方法，其 中該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球之尺寸大小係與該晶片翹曲程度及方向具有正向或反向關聯。
  10. 如申請專利範圍第8項所述之晶片封裝體之製造方法，更包含在形成該些複數封裝體後，對該些銲球進行一回銲製程。
  11. 如申請專利範圍第10項所述之晶片封裝體之製造方法，其中在經該回銲製程後，該些具有該第一尺寸之銲球相較於未回銲之前變得寬矮，且該些具有該第二尺寸之銲球相較於未回銲之前變得高窄。
  12. 如申請專利範圍第8項所述之晶片封裝體之製造方法，其中該些具有第一尺寸之銲球之間的間距係不同於該些具有該第二尺寸之銲球之間的間距，其中該些具有第一尺寸之銲球之間的間距係不同於該些具有第一尺寸之銲球與該些具有該第二尺寸之銲球的間距。
  13. 如申請專利範圍第8項所述之晶片封裝體之製造方法，其中該些具有該第一尺寸之銲球係皆電性連接該晶片至該封裝基材，且該些具有該第二尺寸之銲球係為虛置銲球。
  14. 一種晶片封裝體之製造方法，包括：於一晶圓上形成複數晶片；量測該晶圓上之晶片的電路分佈；切割該晶圓，形成複數分離的晶片；裝設複數銲球於該些分離的晶片上，其中該些銲球中的每一個皆具有向外突出之側壁，其中該些銲球包含一第一尺 寸及一第二尺寸，且該些具有該第二尺寸之銲球相對於該些具有該第一尺寸之銲球係設置於靠近該晶片之角落的位置，其中該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球之尺寸大小係與量測該晶片表面之電路分佈所得出的晶片翹曲程度及方向有關，且其中該些具有該第一尺寸之銲球的剖面寬度大於該些具有該第二尺寸之銲球的剖面寬度，且該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球係依照該電路分佈之量測結果分佈；以及各自接合該些分離的晶片至對應的基材上，形成複數晶片封裝體。
  15. 如申請專利範圍第14項所述之晶片封裝體之製造方法，其中該些具有該第一尺寸之銲球及該些具有該第二尺寸之銲球之尺寸大小係與該晶片翹曲程度及方向具有正向或反向關聯。
  16. 如申請專利範圍第14項所述之晶片封裝體之製造方法，更包含在形成該些晶片封裝體後，對該些銲球進行一回銲製程。
  17. 如申請專利範圍第16項所述之晶片封裝體之製造方法，其中在經該回銲製程後，該些具有該第一尺寸之銲球相較於未回銲之前變得寬矮，且該些具有該第二尺寸之銲球相較於未回銲之前變得高窄。
  18. 如申請專利範圍第14項所述之晶片封裝體之製造方法，其中該些具有第一尺寸之銲球之間的間距係不同於該些具有該第二尺寸之銲球之間的間距，其中該些具有第一尺寸之 銲球之間的間距係不同於該些具有第一尺寸之銲球與該些具有該第二尺寸之銲球的間距。
  19. 如申請專利範圍第14項所述之晶片封裝體之製造方法，其中該些具有該第一尺寸之銲球係皆電性連接該晶片至該封裝基材，且該些具有該第二尺寸之銲球係為虛置銲球。
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