TWI590338B - 金屬氧化物半導體裝置結構用之鰭狀物的形成方法 - Google Patents

金屬氧化物半導體裝置結構用之鰭狀物的形成方法 Download PDF

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TWI590338B
TWI590338B TW104126522A TW104126522A TWI590338B TW I590338 B TWI590338 B TW I590338B TW 104126522 A TW104126522 A TW 104126522A TW 104126522 A TW104126522 A TW 104126522A TW I590338 B TWI590338 B TW I590338B
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fin
dielectric layer
substrate
fins
upper side
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TW104126522A
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TW201611124A (zh
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馬丁 吉爾斯
塔何 甘尼
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英特爾股份有限公司
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Description

金屬氧化物半導體裝置結構用之鰭狀物的形成方法
本發明的實施例係有關金屬氧化物半導體裝置結構用之鰭狀物的形成方法。
例如微處理器等微電子積體電路包括數以百萬計的電晶體。積體電路的速度主要取決於這些電晶體的性能。因此，產業已發展出獨特的結構以增進性能，例如非平面電晶體。
例如鍺(Ge)等替代通道材料能夠造成更高性能的電晶體。這些材料與矽基板被集成在一起而成為最有用的。集成設計方案應允許在設計上能夠選取用於各電晶體的電晶體材料型式。今日，使用晶圓級或是使用中間SiGe成分的厚緩衝層之大面積地毯式(blanket)生長以容納晶格失配缺陷，取得矽上鍺之異質磊晶。厚緩衝使得難以形成用於單一電路之與Si混合的小的Ge島。相較於習知的Si晶圓，此方式也苦於相當高的缺陷密度。
200‧‧‧裝置
202‧‧‧基板
204‧‧‧矽鰭狀物
206‧‧‧介電層
208‧‧‧薄膜
220‧‧‧多晶矽閘極
400‧‧‧裝置
402‧‧‧基板
404‧‧‧矽鰭狀物
406‧‧‧介電層
408‧‧‧膜
420‧‧‧多晶矽閘極
600‧‧‧裝置
602‧‧‧基板
604‧‧‧矽鰭狀物
606‧‧‧介電層
608‧‧‧磊晶層
620‧‧‧多晶矽閘極
630‧‧‧裝置
800‧‧‧裝置
802‧‧‧基板
804‧‧‧矽鰭狀物
806‧‧‧介電層
808‧‧‧薄膜
820‧‧‧多晶矽閘極
1000‧‧‧裝置
1002‧‧‧基板
1004‧‧‧矽鰭狀物
1006‧‧‧介電層
1008‧‧‧層
1100‧‧‧互補金屬氧化物半導體積體電路
1102‧‧‧絕緣基板
1104‧‧‧單晶矽基板
1106‧‧‧絕緣層
1110‧‧‧N型非平面電晶體
1112‧‧‧閘極介電層
1120‧‧‧閘極電極
1122‧‧‧側壁
1124‧‧‧側壁
1127‧‧‧金屬膜
1128‧‧‧金屬膜
1130‧‧‧半導體本體
1131‧‧‧側壁
1132‧‧‧側壁
1134‧‧‧上表面
1135‧‧‧底表面
1140‧‧‧源極區
1142‧‧‧汲極區
1144‧‧‧通道區
1150‧‧‧p型非平面電晶體
1152‧‧‧閘極介電層
1160‧‧‧閘極電極
1162‧‧‧側壁
1164‧‧‧側壁
1170‧‧‧半導體本體
1171‧‧‧側壁
1172‧‧‧側壁
1174‧‧‧上表面
1175‧‧‧底表面
1180‧‧‧源極區
1182‧‧‧汲極區
1184‧‧‧通道區
1200‧‧‧計算裝置
1202‧‧‧板
1204‧‧‧處理器
1206‧‧‧通訊晶片
1210‧‧‧動態隨機存取記憶體
1211‧‧‧動態隨機存取記憶體
1212‧‧‧唯讀記憶體
1220‧‧‧圖形處理器
1222‧‧‧晶片組
1224‧‧‧天線
1226‧‧‧觸控螢幕顯示器
1228‧‧‧觸控螢幕控制器
1230‧‧‧電池
1232‧‧‧功率放大器
1234‧‧‧全球定位系統
1236‧‧‧羅盤
1240‧‧‧揚聲器
1250‧‧‧相機
在附圖的圖式中，以舉例說明而非限定的方式，顯示本發明的實施例，其中：圖1是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如電晶體)形成方法100；圖2A-2C顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖；圖3是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如電晶體)形成方法300；圖4A-4G顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖；圖5是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如電晶體)形成方法500；圖6A-6J顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖；圖7是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如電晶體)形成方法700；圖8A-8D顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖；圖9是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如電晶體)形成方法900；圖10A-10F顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖； 圖11顯示依據本發明的實施例之包含設有金屬閘極電極1320的n型非平面電晶體1310及p型非平面電晶體1350之互補金屬氧化物半導體(CMOS)積體電路1300的一部份；以及圖12顯示依據本發明的實施例之系統1400的方塊圖。
【發明內容及實施方式】
在下述的詳細說明中，參考以舉例方法來顯示所主張之標的可被實施於其中之具體實施例的附圖。這些實施例被充分說明，以使習於此技藝者能夠實施該標的。要瞭解，各式各樣的實施例雖然不同但不必是相互排斥的。舉例而言，在不悖離所主張之標的的精神及範圍之下，本發明之與一個實施例有關之此處所述的特定特點、結構、或特徵可以在其它實施例內被實施。此外，要瞭解，在不悖離所主張之標的的精神及範圍之下，在各揭示的實施例之內各個元件的位置或配置可以被修改。下述詳細說明因而不被視為限定性的，且該標的之範圍僅由後附的申請專利範圍所界定，且伴隨後附的申請專利範圍之完全的均等範圍來作適當的解釋。在附圖中，在多個圖式中，類似的數字意指相同的或類似的元件或功能，其中所顯示的元件不一定彼此依比例，而是個別元件可能被放大或縮小，以便更容易瞭解本說明上下文中的元件。在例如三閘極電晶體及鰭狀場效電晶體(FinFET)等非平面電晶體的製造中，非 平面半導體本體必須被用來形成設有非常小的閘極長度之能夠完全空乏的電晶體(例如，小於約30nm)。這些半導體本體通常是鰭狀的，且因而通常被稱為電晶體「鰭狀物」。舉例而言，在三閘極電晶體中，電晶體鰭狀物具有形成於塊狀半導體基板或是絕緣體上的矽基板上之上表面及二個相對的側壁。閘極介電質可被形成於半導體本體的上表面及側壁上，並且，閘極電極可被形成於半導體本體的上表面上的閘極介電質之上且相鄰於半導體本體的側壁上的閘極介電質。因此，由於閘極介電質及閘極電極係相鄰於半導體本體的三個表面，所以，形成三個分開的通道及閘極。由於形成有三個分開的通道，所以，當電晶體被開啟時，半導體本體可被完全地空乏。關於鰭狀FET電晶體，閘極材料及電極僅接觸半導體本體的側壁，使得二個分開的通道(而非三閘極電晶體中的三個通道)被形成。
本說明的實施例係有關包含三閘極電晶體及鰭狀FET電晶體之微電子裝置的製造。在至少一實施例中，本標的係有關僅在電晶體要求的本地區域中形成結晶Ge鰭狀物之方法。這些方法包含用以生長薄的Ge層的選擇性生長方法。小體積的Ge允許生長而無擴展的缺陷之成核。由於鰭狀物將延伸於降低生長層中的應力及允許穩定生長較厚的膜之薄膜磊晶期間，所以鰭狀物比塊狀基板係更加機械共容的。與先前方式相反地，選擇性生長未要求使用緩衝層。此處所述的方法包含在Si上選擇性地生長Ge以形成電晶的鰭狀體。在實施例中，選擇性生長設計允許Ge 與Si種子分離以形成絕緣體上鍺(GOI)結構。
圖1是流程圖，其顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如，電晶體)形成方法100。該方法100包含：在方塊102，在基板上形成矽鰭狀物。舉例而言，基板可藉由光阻掩罩而被圖案化，然後被蝕刻以形成矽鰭狀物。然後，在方塊104，該方法100在基板上形成介電層且該介電層係相鄰於矽鰭狀物而使得各矽鰭狀物的上側區域被曝露出。然後，在方塊106，磊晶層係生長於鰭狀物的曝露出之上側區域上。在一個實施例中，鍺係磊晶地生長於矽鰭狀物的上側區域上。在另一實施例中，矽鍺係磊晶地生長於矽鰭狀物的上側區域上。在實施例中，III-V族材料被生長於III-V族基板(例如，GaAs)或是IV族基板(例如，Ge)上。然後，該方法100繼續傳統的電晶體處理(例如，三閘極(Trigate)或鰭狀物FET處理)。舉例而言，在方塊108，本處理可包含沈積仿氧化物及閘極多晶矽、圖案化及蝕刻多晶矽閘極、沈積及蝕刻用於閘極的間隔器材料、以及形成包含磊晶源極/汲極生長的源極/汲極區。在方塊110，該處理也可包含接點的形成及以閘極氧化物/金屬閘極來取代多晶矽閘極之金屬閘極更換製程。
圖2A-2C顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖。以這些剖面視圖來顯示該方法100。如圖2A所示，裝置200包含基板202、矽鰭狀物204及介電層206。在本方法 中，將變成電晶體本體(例如，PMOS本體)的核心之薄矽鰭狀物被形成。薄矽鰭狀物也可被使用作為NMOS裝置的本體。然後，如圖2B中所示般，在矽核心上磊晶地生長薄膜208(例如，鍺、矽鍺)，以完成電晶體本體。如圖2C所示，電晶體處理繼續且包含配置於鰭狀物上的多晶矽閘極220及仿氧化物。根據傳統的處理，多晶矽閘極220可由閘極氧化物及金屬閘極來予以取代。
在一個實施例中，矽鰭狀物具有30-50奈米的高度、5-10奈米的寬度、及鰭狀物間50-100奈米的間距。膜208視膜型式而具有5-10奈米的厚度。
圖3是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如，電晶體)形成方法300。該方法300包含：在方塊302，在基板上形成矽鰭狀物。舉例而言，基板藉由光阻掩罩而被圖案化，然後被蝕刻以形成矽鰭狀物。然後，在方塊304，在鰭狀物上生長磊晶層。在一個實施例中，鍺係磊晶地生長於矽鰭狀物的上。在另一實施例中，矽鍺係磊晶地生長於矽鰭狀物上。在實施例中，III-V族材料被生長於III-V族基板(例如，GaAs)或是IV族基板(例如，Ge)上。然後，在方塊306，該方法300在基板上形成介電層且介電層係相鄰於矽鰭狀物而使得矽鰭狀物被介電層所遮蓋。在方塊308，移除介電層的上側部份及磊晶層的上側部份(例如，被蝕刻、被平坦化)而使得各鰭狀物的上側表面被曝露出。在方塊310，選擇性蝕刻移除矽鰭狀物的上側區域，但未蝕刻或實質上未蝕刻磊晶 生長層(例如，鍺、矽鍺)。在方塊312，發生介電層填充或沈積。然後，方法300繼續傳統的電晶體處理(例如，三閘極或鰭狀物FET處理)。舉例而言，在方塊314，本處理包含圖案化/蝕刻介電層、沈積仿氧化物及閘極多晶矽、圖案化及蝕刻多晶矽閘極、沈積及蝕刻用於閘極的間隔器材料、以及形成包含磊晶源極/汲極生長的源極/汲極區。在方塊316，該處理也包含接點的形成和以金屬閘極來取代多晶矽閘極之金屬閘極更換製程。
圖4A-4G顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖。以這些剖面視圖來顯示方法400。如圖4A所示，裝置400包含基板402及矽鰭狀物404。在本方法中，形成決定電晶體本體(例如，PMOS本體)的Ge鰭狀物之間的間距之薄矽鰭狀物。薄矽鰭狀物也被使用作為NMOS裝置的本體。然後，如圖4B中所示般，在矽鰭狀物上磊晶地生長薄膜層408(例如，鍺、矽鍺)。如圖4C所示，該方法400在基板上形成介電層406且介電層406係相鄰於矽鰭狀物而使得矽鰭狀物被遮蓋。如圖4D所示，移除介電層的上側部份及磊晶層的上側部份(例如，被蝕刻、被平坦化)而使得各鰭狀物的上側表面被曝露出。如圖4E所示，選擇性蝕刻移除矽鰭狀物的上側區域，但未蝕刻或實質地蝕刻磊晶生長層(例如，鍺、矽鍺)。如圖4F所示，發生介電層填充或沈積。如圖4G所示，電晶體處理繼續且包含配置於鰭狀物上的多晶矽閘極40及仿氧化物。根據傳統的處 理，多晶矽閘極420係由閘極氧化物及金屬閘極來予以取代。
在一個實施例中，矽鰭狀物具有30-50奈米的高度、10-50奈米的寬度、及鰭狀物間40-150奈米的間距405。膜408視膜型式而具有5-10奈米的厚度以及間距409視膜的型式及設計需求而為20-80奈米。在實施例中，間距409是鰭狀物之間的間距405的一半。根據所需的鍺鰭狀物的間距，設計矽鰭狀物的間距。該方法400形成具有自然間距二倍之唯鍺鰭狀物。
圖5是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如，電晶體)形成方法500。該方法500包含：在方塊502，在基板上形成矽鰭狀物。舉例而言，基板藉由光阻掩罩而被圖案化，然後被蝕刻以形成矽鰭狀物。然後，在方塊504，該方法500在基板上形成介電層且介電層係相鄰於矽鰭狀物而使得各矽鰭狀物被遮蓋。在方塊506，介電層凹陷而使得鰭狀物的上側區域被曝露出。然後，在方塊508，在鰭狀物上生長磊晶層。在一個實施例中，鍺係磊晶地生長於矽鰭狀物上。在另一實施例中，矽鍺係磊晶地生長於矽鰭狀物上。在實施例中，III-V族材料被生長於III-V族基板(例如，GaAs)或是IV族基板(例如，Ge)上。
然後，在方塊510，方法500在基板上形成介電層且介電層係相鄰於矽鰭狀物而使得矽鰭狀物及磊晶層被介電層所遮蓋。在方塊512，移除介電層的上側部份及磊晶層 的上側部份(例如，被蝕刻、被平坦化)而使得鰭狀物的上側表面被曝露出。在方塊514，選擇性蝕刻移除矽鰭狀物的上側區域，但未蝕刻或實質地蝕刻磊晶生長層(例如，鍺、矽鍺)。在方塊516，發生介電層填充或沈積。然後，方法500繼續傳統的電晶體處理(例如，三閘極或鰭狀物FET處理)。舉例而言，在方塊518，本處理包含圖案化/蝕刻介電層、沈積仿氧化物及閘極多晶矽、圖案化及蝕刻多晶矽閘極、沈積及蝕刻用於閘極的間隔器材料、以及形成包含磊晶源極/汲極生長的源極/汲極區。在方塊520，處理也包含接點的形成和以金屬閘極來取代多晶矽閘極之金屬閘極更換製程。
圖6A-6J顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖。以這些剖面視圖來顯示方法500。如圖6A所示，裝置600包含基板602及矽鰭狀物604。在本方法中，形成決定電晶體本體(例如，PMOS本體)的Ge鰭狀物間的間距之薄矽鰭狀物。薄矽鰭狀物也被使用作為NMOS裝置的本體。如圖6B中所示般，在基板上形成介電層606且介電層606係相鄰於矽鰭狀物而使得矽鰭狀物被遮蓋。如圖6C所示，移除介電層的上側部份(例如，被蝕刻、被平坦化)而使得鰭狀物的上側區域被曝露出。然後，如圖6D所示，在矽鰭狀物上磊晶地生長薄磊晶層608(例如，鍺、矽鍺)。然後，如圖6E所示，在基板上形成介電層606且介電層606係相鄰於矽鰭狀物而使得矽鰭狀物被遮蓋。然 後，如圖6F所示，移除介電層的上側部份及磊晶層的上側部份(例如，被蝕刻、被平坦化)而使得鰭狀物的上側表面被曝露出。如圖6G的裝置600或是圖6G’的裝置630所示般，選擇性蝕刻移除矽鰭狀物的上側區域，但未蝕刻或實質地蝕刻磊晶生長層(例如，鍺、矽鍺)。
如圖6H或6I所示，發生介電層填充或沈積。假使圖6C中所示的介電層蝕刻移除的介電層比圖6G中所示的矽蝕刻移除的矽還多時，製成圖6H中的裝置600。假使圖6C中所示的介電層蝕刻移除的介電層比圖6G’中所示的矽蝕刻移除的矽還少時，製成圖61中的裝置630。圖6H中所示的裝置600在鍺鰭狀物608與矽鰭狀物604之間具有重疊而圖6I中所示的裝置630並未包含此重疊。裝置630因為缺乏電晶體本體之鍺鰭狀物608與矽基板602的一部份之矽鰭狀物604之間的重疊及分離，所以裝置630將容易具有更佳的裝置性能。裝置630是絕緣體上半導體裝置。
如圖6J所示，電晶體處理繼續且包含配置於鰭狀物上的多晶矽閘極620及仿氧化物。根據傳統的處理，多晶矽閘極620係由閘極氧化物及金屬閘極來予以取代。
在一個實施例中，矽鰭狀物具有30-50奈米的初始高度、10-50奈米的寬度、及鰭狀物間40-150奈米的間距605。層608視膜型式而具有5-10奈米的厚度，間距609視膜的型式及設計需求而為20-80奈米。在實施例中，間距609是鰭狀物的間距605的一半。根據鍺鰭狀物的所示 間距，設計矽鰭狀物的間距。該方法500形成具有自然間距二倍的唯Ge鰭狀物。
該方法500類似於該方法300，但是在接著處理進行至如圖6C中所示的氧化物凹陷之後進一步處理啟始的矽鰭狀物除外。然後，在矽鰭狀物上磊晶地選擇性生長薄的Ge膜且處理如同方法300中一般繼續進行。有二種分別如圖6H及6I中所示之可能的結果結構600及630。相較於方法100及300，方法500具有較小的Ge生長面積(亦即，只有主動鰭狀物區域)之優點。此方法500允許在缺陷成核之前生長較厚的Ge膜。
圖7是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如，電晶體)形成方法700。該方法700包含：在方塊702，在基板上形成矽鰭狀物，在方塊704，在基板上形成介電層，並且，在方塊706，移除介電層的上側部份。舉例而言，基板藉由光阻掩罩而被圖案化，然後被蝕刻以形成矽鰭狀物。然後，在基板上形成介電層且介電層凹回而使得矽鰭狀物的上側表面被曝露出。在方塊708，選擇性蝕刻移除矽鰭狀物的上側區域，但未蝕刻或實質上並未蝕刻介電層。然後，在方塊710，在鰭狀物的頂部上生長磊晶層。在一個實施例中，鍺係磊晶地生長於矽鰭狀物上。在另一實施例中，矽鍺係磊晶地生長於矽鰭狀物的頂部上。在實施例中，III-V族材料被生長於III-V族基板(例如，GaAs)或是IV族基板(例如，Ge)上。然後，該方法700繼續傳統的電晶體處理(例如，三 閘極或鰭狀物FET處理)。舉例而言，在方塊712，本處理包含圖案化/蝕刻介電層、沈積仿氧化物及閘極多晶矽、圖案化及蝕刻多晶矽閘極、沈積及蝕刻用於閘極的間隔器材料、以及形成包含磊晶源極/汲極生長的源極/汲極區。在方塊714，處理也包含接點的形成及以金屬閘極來取代多晶矽閘極之金屬閘極更換製程。
圖8A-8D顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖。可以這些剖面視圖來顯示方法700。如圖8A所示，裝置800包含基板802、介電層806、及矽鰭狀物804。在本方法中，形成薄矽鰭狀物，薄矽鰭狀物將提供用來生長被用作為電晶體本體(例如，PMOS本體)的磊晶層之矽種子。薄矽鰭狀物也被使用作為NMOS裝置的本體。如圖8B所示，選擇性蝕刻移除矽鰭狀物的上側區域，但並未蝕刻或實質上並未蝕刻介電層。然後，如圖8C所示，在矽鰭狀物的頂部上磊晶地生長薄膜808(例如，鍺、矽鍺)。如圖8D所示，電晶體處理繼續且包含配置於鰭狀物上的多晶矽閘極820及仿氧化物。根據傳統的處理，多晶矽閘極1020係由閘極氧化物及金屬閘極來予以取代。
在一個實施例中，矽鰭狀物具有30-50奈米的高度、10-100奈米的寬度、及鰭狀物間40-150奈米的間距805。膜808視膜型式而具有10-100奈米的厚度且膜808具有與間距805相同的間距。
本方法700產生具有與最終所要的鍺鰭狀物間距匹配 的矽鰭狀物之裝置800。
圖9是流程圖，顯示依據本發明的一個實施例之設有鰭狀物的裝置(例如，電晶體)形成方法900。該方法900包含：在方塊902，在基板上形成矽鰭狀物，在方塊904，在基板上形成介電層，並且，在方塊906，移除介電層的上側部份。舉例而言，基板藉由光阻掩罩而被圖案化，然後被蝕刻以形成矽鰭狀物。然後，在基板上形成介電層且介電層凹回而使得矽鰭狀物的上側表面被曝露出。在方塊908，選擇性蝕刻移除矽鰭狀物的上側區域，但並未蝕刻或實質地蝕刻介電層。然後，在方塊910，形成(例如，沈積、磊晶生長)層(例如，非晶的、多晶的、缺陷被填充的結晶、等等)於鰭狀物及介電層上。在一個實施例中，鍺係形成於矽鰭狀物的頂部上。在另一實施例中，矽鍺係形成於矽鰭狀物上。在實施例中，III-V族材料被生長於III-V族基板(例如，GaAs)或是IV族基板(例如，Ge)上。在方塊912，將層平坦化。在方塊914，以高於層的熔點之某溫度，將裝置退火(例如，快速熱退火)，這允許此層的複數個區域從下層的矽種子被再結晶，以產生結晶層(例如，鍺層)。可以切換平坦化及退火的順序。然後，方法900繼續傳統的電晶體處理(例如，三閘極或鰭狀物FET處理)。舉例而言，在方塊916，本處理包含圖案化/蝕刻介電層、沈積仿氧化物及閘極多晶矽、圖案化及蝕刻多晶矽閘極、沈積及蝕刻用於閘極的間隔器材料、以及形成包含磊晶源極/汲極生長的源極/汲極區。在方塊918， 處理也包含接點的形成及以金屬閘極來取代多晶矽閘極之金屬閘極更換製程。
圖10A-10F顯示依據本發明的一個實施例之例如PMOS裝置或NMOS裝置等電晶體的鰭狀物形成之剖面視圖。以這些剖面視圖來顯示方法900。如圖10A所示，裝置1000包含基板1002、介電層1006、及矽鰭狀物1004。在本方法中，形成薄矽鰭狀物，而薄矽鰭狀物將提供用來再晶化沈積的層之矽種子，在再晶化之後，沈積的層被使用作為電晶體本體(例如，PMOS本體)。薄矽鰭狀物也被使用作為NMOS裝置的本體。如圖10B所示，選擇性蝕刻移除矽鰭狀物的上側區域，但未蝕刻或實質上未蝕刻介電層。然後，如圖10C所示，在鰭狀物上形成(例如，沈積、磊晶生長)層1008(例如，非晶的、多晶的、缺陷被填充的結晶、等等)。在一個實施例中，鍺係形成於矽鰭狀物上。在另一實施例中，矽鍺係形成於矽鰭狀物上。如圖10D所示，將層平坦化。如圖10E所示，以高於層的熔點之某溫度，將裝置退火(例如，快速熱退火)，這允許此層的複數個區域從下層的矽種子被再結晶，以產生結晶層(例如，鍺層)。如圖10F所示，電晶體處理繼續及包含沈積於鰭狀物上的仿氧化物及多晶矽閘極1020。根據傳統的處理，多晶矽閘極1020係由閘極氧化物及金屬閘極來予以取代。
在一個實施例中，矽鰭狀物具有30-50奈米的高度、10-100奈米的寬度、及鰭狀物間40-150奈米的間距 1005。膜1008視膜型式而具有10-100奈米的厚度且膜1008具有與間距1005相同的間距。本方法900產生具有與最終所要的鍺鰭狀物間距匹配的矽鰭狀物之裝置1000。
在一個實施例中，該方法900形成矽鰭狀物以及使它們凹陷在圍繞的氧化物之內。沈積鍺以填充溝槽，但這不需要是磊晶生長操作。非晶的、多晶的、或是缺陷被填充的結晶Ge沈積也是可能的。在平坦化之後，使用Ge的熔點之上的快速熱退火以剛好熔融複數個Ge區域，然後允許它們從下方的矽種子再結晶以產生結晶的Ge鰭狀物。平坦化及熔融退火的次序可以互換。快速熱或雷射退火使鰭狀物邊界處的鍺及矽的相互擴散最小。
在本揭示的實施例中，基板可以是單晶矽基板。基板也可以是其它型式的基板，例如絕緣體上矽(SOI)、鍺、砷化鎵、銻化銦、碲化鉛、砷化銦、磷化銦、砷化鎵、銻化鎵、等等，它們之中的任何一者可以與矽相結合。
閘極介電層可以由任何熟知的閘極介電材料所形成，包含但不限於二氧化矽(SiO2)、氧氮化矽(SiOxNy)、氮化矽(Si3N4)、及高k介電材料，舉例而言，高k介電材料為氧化鉿、鉿矽氧化物、氧化鑭、鑭鋁氧化物、氧化鋯、鋯矽氧化物、氧化鉭、氧化鈦、鋇鍶鈦氧化物、鋇鈦氧化物、鍶鈦氧化物、氧化釔、氧化鋁、鉛鈧鉭氧化物、及鉛鋅鈮酸鹽。
以例如化學汽相沈積(CVD)、物理汽相沈積(PVD)、 原子層沈積(ALD)、閘極介電層等習知技術，藉由例如沈積閘極電極材料，而形成閘極介電層，然後，如同習於此技藝者所知般，以習知的微影術及蝕刻技術，將閘極電極材料圖案化。
可瞭解，源極區以及汲極區(未顯示出)被形成於在閘極電極的相對立側上的電晶體鰭狀物中。源極和汲極區域係由例如N型或P型導電率之相同導電率所型形成。源極和汲極區域具有均勻的摻雜濃度或是包含不同濃度或摻雜輪廓的子區域，例如尖端區域(例如，源極/汲極延伸)。在本揭示的實施例之某些實施中，源極和汲極區具有實質上相同的摻雜濃度及輪廓，而在其它實施中它們可以被改變。
依據本發明的實施例之非平面電晶體的實例顯示於圖11中。圖11顯示互補金屬氧化物半導體(CMOS)積體電路1100的部份，積體電路1100包含形成於絕緣基板1102上之設有金屬閘極電極1120的n型非平面電晶體1110及設有金屬閘極電極1152的p型非平面電晶體1150。n型電晶體1110是載子為電子的場效電晶體以及p型電晶體1150是載子為電洞的電晶體。N型電晶體1110及p型電晶體1150經由更高層的金屬化而被耦合在一起成為有功能的CMOS電路。雖然參考圖11以顯示及說明CMOS積體電路1100，但是，本發明的實施例不限於CMOS積體電路及包含僅包括設有金屬閘極電極的p型非平面電晶體或是僅包括設有金屬閘極電極的n型非平面電晶體之電 路。在一個實施例中，使用此處所述的方法來製造圖11中所示的CMOS集成方式之PMOS裝置用的Ge鰭狀物以及以正規Si鰭狀物使用於NMOS裝置。更一般而言，在其它實施例中，揭示的方法之一用來製造具有一材料型式的NMOS鰭狀物以及另一方法製造具有不同材料型式的PMOS鰭狀物。
CMOS積體電路1100係形成在絕緣基板1102上。在本發明的實施例中，絕緣基板1102包含下單晶矽基板1104，在下單晶矽基板1104上，形成有例如氧化矽膜等絕緣層1106。但是，積體電路1100可以被形成在任何適當的絕緣基板上，例如由二氧化矽、氮化物、氧化物、及藍寶石所形成的基板。
此外，在本發明的實施例中，基板1102無需一定是絕緣基板，也可以是習知的半導體基板，例如但不限於單結晶矽基板及砷化鎵基板。
N型非平面電晶體1110包含形成於絕緣基板1102的絕緣層1106上的半導體本體1130，並且，p型非平面電晶體1150包含形成於絕緣基板1102的絕緣層1106上的半導體本體1170。半導體本體1130及1170係由任何習知的半導體材料所形成，例如但不限於矽、鍺、矽鍺(SixGey)、砷化鎵(GaAs)、InSb、GaP、GaSb、奈米碳管及奈米碳線。半導體本體1130及1170係由會因施加外部電控制而從絕緣狀態可逆地改變成導電狀態之任何習知材料所形成。當希望電晶體1110及1150的最佳電性能時，半 導體本體1130及1170理想上是單晶膜。舉例而言，當CMOS積體電路1100被使用於例如高密度電路、例如微處理器等高性能應用時，半導體本體1130及1170是單晶膜。但是，當CMOS積體電路1100被使用於例如液晶顯示器等要求較不嚴格的性能之應用時，半導體本體1130及1170可以是多晶膜。絕緣層1106使半導體本體1130及1170與單晶矽基板1102絕緣。在本發明的實施例中，半導體本體1130及1170是單晶矽膜。
半導體本體1130具有成對的橫向相對立側壁1131及1132，以界定半導體本體寬度1133的距離分開。此外，半導體本體1130具有與形成於基板1102上的底表面1135相對立的上表面1134。上表面1134與底表面1135之間的距離界定本體高度1136。在本發明的實施例中，本體高度1136實質上等於本體寬度1135。在本發明的實施例中，本體1130具有小於50奈米的高度1136以及小於20奈米的寬度1133。在本發明的實施例中，本體高度1136是在本體寬度1133的二倍至本體寬度1133的十倍之間。
類似地，半導體本體1170具有成對的橫向對立的側壁1171及1172，以界定半導體本體寬度1173的距離1173分離。此外，半導體本體1170具有與形成於基板1102上的底表面1175相對立的上表面1174。上表面1174與底表面1175之間的距離界定本體高度1176。在本發明的實施例中，本體高度1176是在本體寬度1133的二 倍至本體寬度1173的十倍之間。
N型非平面電晶體1110具有閘極介電層1112。如圖11所示，閘極介電層1112係形成於半導體本體1130的三側之上及周圍。如圖11所示，閘極介電層1112係形成於側壁1131上或相鄰於側壁1131、形成於上表面1134上、及本體1130的側壁1132上或相鄰於側壁1132。類似地，P型非平面電晶體1150具有閘極介電層1152。如圖11所示，閘極介電層1152係形成於半導體本體1170的三側之上及周圍。如圖11所示，閘極介電層1152係形成於側壁1171上或相鄰於側壁1171、形成於上表面1174上、及本體1170的側壁1172上或相鄰於側壁1172。閘極介電層1112及1152可由任何習知的閘極介電膜所形成。在本發明的實施例中，閘極介電層是二氧化矽(SiO2)、氧氮化矽(SiOxNy)、或是氮化矽(Si3N4)介電層或其組合。在本發明的實施例中，閘極介電層1112及1152是形成為厚度在5-20的氧氮化矽膜。在本發明的實施例中，閘極介電層1112及1152是例如金屬介電質的高K閘極介電層，例如但不限於氧化鉭、氧化鈦、氧化鉿、氧化鋯、氧化鋁、氧化鑭、鑭鋁氧化物及其矽酸鹽。在本發明的實施例中，介電層1112及1152是其它型式的高K介電層，例如但不限於PZT及BST。
N型非平面裝置1110具有閘極電極1120。如圖11所示，閘極電極1120係形成於閘極介電層1112上及周圍。閘極電極1120係形成於在半導體本體1130的側壁1131 上形成的閘極介電層1112上或是相鄰於閘極介電層1112、形成於在半導體本體1130的上表面1134上形成的閘極介電層1112上、以及形成為相鄰於半導體本體1120的側壁1132上形成的閘極介電層1112或是形成於其上。閘極電極1120具有成對的橫向對立的側壁1122及1124，以界定n型電晶體1110的閘極長度1126的距離分離。在本發明的實施例中，閘極電極1120的橫向對立側壁1122及1124的走向為垂直於半導體本體1130的橫向對立側壁1131及1132。類似地，如圖11所示，p型非平面裝置1150具有形成於閘極介電層1152上及周圍的閘極電極1160。如圖11所示，閘極電極1160係形成於在半導體本體1170的側壁1171上形成的閘極介電層1152上或是相鄰於閘極介電層1152、形成於在半導體本體1170的上表面1174上形成的閘極介電層1152上、以及形成為相鄰於半導體本體1170的側壁1172上形成的閘極介電層1152或是形成於其上。閘極電極1170具有成對的橫向對立的側壁1162及1164，以界定p型電晶體1150的閘極長度(Lg)1166的距離分離。在本發明的實施例中，閘極電極1160的橫向對立側壁1162及1164的走向為垂直於半導體本體1170的橫向對立側壁1171及1172。
在本發明的實施例中，閘極電極1120及1160係由包括下金屬膜1127及上金屬或摻雜的多晶矽膜1128的複合膜所形成。在本發明的實施例中，下金屬膜1127控制閘極電極材料的功函數。在本發明的實施例中，閘極電極 1120及1160的下金屬部1127被形成為至少25或是四單層的厚度，使得閘極電極材料的功函數係由下金屬膜所控制。亦即，在本發明的實施例中，下金屬膜被形成為足夠厚，而使得它不是「功函數透明的」，使得閘極電極材料的功函數係由下金屬膜1127所控制而未由上金屬膜1128所控制。在本發明的實施例中，下金屬部1127被形成為25-100之間的厚度且係由例如但不限於TaN、TiN、及摻雜鋁的碳化鈦等鈦及鉭的氮化物或是碳化物所形成。在本發明的實施例中，上金屬膜1128係由具有良好的間隙填充特徵及具有低電阻的材料所形成，例如但不限於鎢(W)、銅(Cu)、或經過摻雜的多晶矽。
N型非平面電晶體1110具有源極區1140和汲極區1142。如圖11所示，源極區1140和汲極區1142係形成於閘極電極1120的相對側上的半導體本體1108中。源極區1140和汲極區1142係由n型導電率所形成。在本發明的實施例中，源極1140和汲極區1142具有在1x1019至1x1021原子/cm3之間的n型摻雜劑濃度。源極區1140和汲極區1142是均勻濃度或是包含不同濃度或摻雜劑輸廓的子區域，例如尖端區(例如，源極/汲極延伸)。在本發明的實施例中，當非平面n型電晶體1110是對稱電晶體時，源極區1140和汲極區1142具有相同的摻雜濃度及輪廓。在本發明的實施例中，非平面n型電晶體1110係形成為不對稱電晶體，在不對稱電晶體中，源極區1140和汲極區1142的摻雜濃度輪廓會改變，以取得特定的電特 徵。
類似地，p型非平面電晶體1150具有源極區1180和汲極區1182。如圖11所示，源極區1180和汲極區1182係形成於閘極電極1160的相對側上的半導體本體1170中。源極區1180和汲極區1182係由p型導電率所形成。在本發明的實施例中，源極區1180和汲極區1182具有在1x1019至1x1021原子/cm3之間的p型摻雜劑濃度。源極區1180和汲極區1182是由均勻濃度所形成或是包含不同濃度摻雜劑輸廓的子區域，例如尖端區(例如，源極/汲極區延伸)。在本發明的實施例中，當非平面p型電晶體1150是對稱電晶體時，源極區1180和汲極區1182具有相同的摻雜濃度及輪廓。在本發明的實施例中，當p型非平面電晶體1150形成為不對稱電晶體時，則源極區1180和汲極區1182的摻雜濃度輪廓會改變，以取得特定的電特徵。
位於源極區1140與汲極區1142之間的半導體本體1130的一部份界定n型非平面電晶體1110的通道區1144。通道區1144也被界定為被閘極電極1120所圍繞的半導體本體1130的面積。類似地，位於源極區1180與汲極區1182之間的半導體本體1170的一部份1184界定p型非平面電晶體1150的通道區1184。通道區1184也被界定為被閘極電極1160所圍繞的半導體本體1170的面積。源極/汲極區典型地延伸經過稍後至閘極電極之下，舉例而言，擴散至界定稍微小於閘極電極長度(Lg)之通道區。在本發明的實施例中，通道區1144及1184是本質的 或未經摻雜的單晶鍺。在本發明的實施例中，通道區1144或1184是被摻雜的單晶鍺。當通道區1144被摻雜時，其典型上被摻雜成在本質與4x1019原子/cm3之間的p型導電率等級。當通道區1184被摻雜時，其典型上被摻雜成在本質與4x1019原子/cm3之間的n型導電率等級。在本發明的實施例中，通道區1144及1184被摻雜至1x1018-1x1019原子/cm3之間的濃度。通道區1144及1184可被均勻地摻雜或是不均勻地摻雜或是具有不同濃度，以提供特定的電性能特徵。舉例而言，假使需要時，通道區1144及1184包含習知的「環」區。
藉由在三側上設置圍繞半導體本體1130的閘極介電1112及閘極電極1120，n型非平面電晶體1110特徵在於具有三通道及三閘極，一個閘極(g1)延伸於半導體本體1130的側1131上的源極與汲極區之間，第二閘極(g2)延伸於半導體本體1130的上表面1134上的源極與汲極區之間，第三閘極(g3)延伸於半導體本體1130的側壁1132上的源極與汲極區之間。因此，非平面電晶體1110被稱為三閘極電晶體。電晶體1110的閘極寬度(Gw)是三個通道區的寬度的總合。亦即，電晶體1110的閘極寬度等於在側壁1131的半導體本體1130的高度1136、加上在上表面1134的半導體本體1130的寬度、加上在側壁1132的半導體本體1130的高度1136。類似地，藉由在三側上設置圍繞半導體本體1170的閘極介電質1152及閘極電極1160，p型非平面電晶體1150特徵在於具有三通道及三 閘極，一個通道及閘極(g1)延伸於半導體本體1170的側壁1171上的源極與汲極區之間，第二通道及閘極(g2)延伸於半導體本體1170的上表面1174上的源極與汲極區之間，第三通道及閘極(g3)延伸於半導體本體1170的側壁1172上的源極與汲極區之間。因此，非平面電晶體1150被稱為三閘極電晶體。電晶體1150的閘極寬度(Gw)是三個通道區的寬度的總合。亦即，電晶體1150的閘極寬度等於在側壁1171的半導體本體1170的高度1176、加上在上表面1174的半導體本體1170的寬度1173、加上在側壁1172的半導體本體1170的高度1176。藉由使用耦合在一起的多個裝置(例如，被單一閘極電極1120所圍繞的多個矽本體1130或是被單一閘極電極1160所圍繞的多個半導體本體1170)，取得較大寬度的n型和p型非平面電晶體。
由於通道區1144及1184在三側上被閘極電極1120和1160所圍繞，所以，電晶體1110和1150能夠以完全空乏的方式來予以操作，其中，當電晶體1110和1150被「開啟」時，通道區1150完全空乏，因而提供完全空乏電晶體之有利的電特徵及性能。亦即，當電晶體1110和1150被「開啟」時，伴隨通道區1144及1184的表面之反轉層(亦即，在半導體本體的側表面及上表面上形成反轉層)，在通道區中形成空乏區。反轉層具有與源極和汲極區相同的導電率型且在源極與汲極區之間形成導電通道，以允許電流能夠在其間流動。空乏區將自由載子從反 轉層之下空乏。空乏區延伸至通道區1144和1184的底部，因此，電晶體可說是「完全空乏的」電晶體。完全空乏的電晶體相較於非完全空乏的或部份空乏的電晶體具有增進的電性能特徵。舉例而言，以完全空乏的方式來操作電晶體1110和1150，造成電晶體理想的或非常陡峭的次臨界值斜率。此外，以完全空乏的方式來操作電晶體1110和1150，電晶體1110和1150具有增進的汲極感應障壁(DIBL)下降效應，提供造成較低漏電的較佳「關閉」狀態漏電，因而降低耗電。須瞭解，假使需要時(例如，半導體本體可製成大的，使得它們不會完全地空乏)，電晶體1110及1150不需要一定以完全空乏方式來操作。
由於通道區1144及1184的反轉層係形成於半導體本體1130和1170中的水平及垂直等二方向上，所以，本發明的實施例的電晶體1110及1150可說是非平面電晶體。由於來自閘極電極1120和1160的電場是從水平(g2)及垂直側(g1和g3)施加，所以，本發明的實施例的半導體裝置也被視為非平面裝置。電晶體1110和1150包含此處有關鍺鰭狀物形成方法所述及說明的多個本體(例如2，3，4)。
在一個實施例中，互補金屬氧化物半導體(CMOS)積體電路包含設有具有第一高度的鰭狀物本體之n型金屬氧化物半導體(NMOS)裝置以及設有具有第二高度的鍺鰭狀物本體和具有第三高度的對應矽鰭狀物本體之p型金屬氧化物半導體(PMOS)裝置。鍺鰭狀物本體形成PMOS裝置 的本體。NMOS裝置的鰭本體包括矽本體鰭狀物，矽本體鰭狀物係設有形成NMOS裝置的本體之矽鰭狀本體。鍺鰭本體具有的間距約為PMOS裝置的矽鰭狀物的間距的一半。
圖12顯示依據本發明的一個實施例之計算裝置1200。計算裝置1200包含板1202。板1202包含多個組件，這些組件包含但不限於處理器1204及至少一通訊晶片1206。處理器1204係實體地及電氣地耦合至板1202。在某些實施中，至少一通訊晶片1206也被實體地及電氣地耦合至板1202。在另外的實施中，通訊晶片1206是處理器1204的部份。
取決於其應用，計算裝置1200可包含可被或可不被實體地或電氣地耦合至板1202之其它組件。這些其它組件包含但不限於依電性記憶體(例如，動態隨機存取記憶體(DRAM)1210、1211)、非依電性記憶體(例如，唯讀記憶體(ROM)1212)、快閃記憶體、圖形處理器1220、數位訊號處理器、密碼處理器、晶片組1222、天線1224、顯示器、觸控螢幕顯示器1226、觸控螢幕控制器1228、電池1230、音頻編解碼器、視頻編解碼器、功率放大器1232、全球定位系統(GPS)裝置1234、羅盤1236、加速儀、陀螺儀、揚聲器1240、相機1250、及大量儲存裝置(例如，硬碟機、光碟(CD)、數位多樣式碟片(DVD)、等等)。
通訊晶片1206能夠對計算裝置1200進行資料傳輸的 無線通訊。「無線」一詞及其衍生詞可以被用來說明經由使用經過非固態介質之被調變的電磁輻射來傳輸資料之電路、裝置、系統、方法、技術、通訊通道、等等。此名詞並非意指相關的裝置未含有任何線，但是，在某些實施例中它們並未含有任何線。通訊晶片1206可以實施多種無線標準或協定，包含但不限於Wi-Fi(IEEE 802.11系列)、WiMAX(IEEE 802.16系列)、IEEE 802.20、長程演進(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、其衍生、以及任何其它被指定為3G、4G、5G、及之外的無線協定。計算裝置1200可包含多個通訊晶片1206。舉例而言，第一通訊晶片1206可專用於例如Wi-Fi及藍芽等較短程無線通訊，而第二通訊晶片1206可專用於例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO、及其它較長程無線通訊。
計算裝置1200的處理器1204包含封裝在處理器1204之內的積體電路晶粒。在本發明的某些實施例中，處理器的積體電路晶粒包含依據本發明的實施形成之例如電晶體(例如，PMOS、NMOS)等一或更多個裝置。「處理器」一詞意指處理來自暫存器及/或記憶體的電子資料以將電子資料轉換成可被儲存於暫存器及/或記憶體中的其它電子資料之任何裝置或裝置的一部份。
通訊晶片1206也包含封裝在通訊晶片1206之內的積體電路晶粒。依據本發明的另一實施例，通訊晶片的積體 電路晶粒包含依據本發明的實施形成之例如電晶體(例如，PMOS、NMOS)等一或更多個裝置。
在另外的實施例中，收納於計算裝置1200之內的另一組件含有包含依據本發明的實施所形成之例如電晶體(例如，PMOS、NMOS)等一或更多個裝置之積體電路晶粒。
在各式各樣的實施例中，計算裝置1200可為膝上型電腦、筆記型電腦、超薄電腦、智慧型電話、平板電腦、個人數位助理(PDA)、超薄行動PC、行動電話、桌上型電腦、伺服器、印表機、掃描器、監視器、機上盒、娛樂控制單元、數位相機、可攜式音樂播放器、或數位攝影機。在另外的實施中，計算裝置1200可為處理資料的任何其它電子裝置。

Claims (16)

  1. 一種半導體裝置之鰭狀物的製造方法，包括：在基板上形成矽鰭狀物；形成第一介電層於該基板上且相鄰於該矽鰭狀物，使得該矽鰭狀物的上側區域被曝露出；以及在該矽鰭狀物的該上側區域上磊晶地生長鍺膜，其中，該鍺膜包括鍺鰭狀物，該鍺鰭狀物具有的間距約為該矽鰭狀物之間距的一半的間距。
  2. 如申請專利範圍第1項之方法，其中，形成該第一介電層於該基板上包括：沈積該第一介電層於該基板上；使該第一介電層凹陷，以使該矽鰭狀物的該上側區域被曝露出；沈積第二介電層於該基板上；使該第二介電層凹陷，以使該矽鰭狀物的上側表面被曝露出；以及選擇性地蝕刻該矽鰭狀物之曝露出的該上側表面至該第二介電層的上側區域及該鍺膜的上側區域之下的凹陷層級。
  3. 如申請專利範圍第1項之方法，其中，該矽鰭狀物具有30至50奈米的高度。
  4. 如申請專利範圍第1項之方法，其中，該矽鰭狀物具有5至10奈米的寬度；以及，其中該鍺膜具有5至10奈米的厚度。
  5. 如申請專利範圍第1項之方法，又包括：沈積第二介電層於該基板上；使該第二介電層凹陷，以使該矽鰭狀物的上側表面曝露出；選擇性地蝕刻該矽鰭狀物之曝露出的該上側表面至該第二介電層的上側區域及該鍺膜的上側區域之下的凹陷層級；以及沈積第三介電層於該基板上。
  6. 如申請專利範圍第4項之方法，又包括：選擇性地蝕刻該矽鰭狀物之曝露出的該上側表面至該鍺膜的下側區域之下的凹陷層級；以及沈積第三介電層於該基板上。
  7. 一種半導體裝置之鰭狀物的製造方法，包括：在基板上形成矽鰭狀物；在該矽鰭狀物上磊晶地生長鍺或矽鍺的層；沈積第一介電層於該基板上；以及平坦化該第一介電層，使得該矽鰭狀物的上側表面曝露出以及使鍺或矽鍺的該層的上側表面曝露出，其中，鍺或矽鍺的該層包括鍺鰭狀物或矽鍺鰭狀物，該鍺鰭狀物或該矽鍺鰭狀物具有的間距約為該矽鰭狀物之間距的一半。
  8. 如申請專利範圍第7項之方法，又包括：選擇性地蝕刻該矽鰭狀物之曝露出的該上側表面至該第一介電層的上側區域及該層的上側區域之下的凹陷層 級。
  9. 如申請專利範圍第7項之方法，又包括：沈積第二介電層於該基板上。
  10. 如申請專利範圍第7項之方法，其中，該矽鰭狀物具有30至50奈米的高度；其中，該矽鰭狀物具有10至50奈米的寬度；以及，其中鍺或矽鍺的該層具有5至10奈米的厚度。
  11. 一種半導體裝置之鰭狀物的製造方法，包括：在基板上形成矽鰭狀物；形成介電層於該基板上且相鄰於該矽鰭狀物，使得該矽鰭狀物的上側表面被曝露出；選擇性地蝕刻該矽鰭狀物之曝露出的該上側表面至該介電層的上側區域之下的凹陷層級；在該矽鰭狀物及該介電層之曝露出的該上側表面上沈積鍺層；以及將該鍺層退火以形成結晶鍺鰭狀物，其中該鍺鰭狀物具有的間距約為該矽鰭狀物之間距的一半。
  12. 如申請專利範圍第11項之方法，又包括：平坦化該鍺層及該介電層的上側區域。
  13. 一種互補金屬氧化物半導體(CMOS)積體電路，包括：n型金屬氧化物半導體(NMOS)裝置，具有帶有第一高度的鰭狀物；以及p型金屬氧化物半導體(PMOS)裝置，具有帶有第二高 度的鍺鰭狀物及帶有第三高度之對應的矽鰭狀物。
  14. 如申請專利範圍第13項之互補金屬氧化物半導體(CMOS)積體電路，其中，該鍺鰭狀物形成p型金屬氧化物半導體(PMOS)裝置的本體。
  15. 如申請專利範圍第13項之互補金屬氧化物半導體(CMOS)積體電路，其中，該n型金屬氧化物半導體(NMOS)裝置的鰭狀物包括矽鰭狀物，其中，該矽鰭狀物形成n型金屬氧化物半導體(NMOS)裝置的本體。
  16. 如申請專利範圍第15項之互補金屬氧化物半導體(CMOS)積體電路，其中，該鍺鰭狀物具有的間距約是該p型金屬氧化物半導體(PMOS)裝置的矽鰭狀物之間距的一半。
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