TWI579923B - 半導體元件之溝槽結構及其製造方法 - Google Patents

半導體元件之溝槽結構及其製造方法 Download PDF

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TWI579923B
TWI579923B TW104137362A TW104137362A TWI579923B TW I579923 B TWI579923 B TW I579923B TW 104137362 A TW104137362 A TW 104137362A TW 104137362 A TW104137362 A TW 104137362A TW I579923 B TWI579923 B TW I579923B
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trench
layer
substrate
dielectric layer
flowable dielectric
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TW201705291A (zh
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林加明
張簡旭珂
林俊澤
王英郎
林瑋耿
劉全璞
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台灣積體電路製造股份有限公司
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Description

半導體元件之溝槽結構及其製造方法
本揭露係關於一種半導體技術，特別係關於一種半導體元件之溝槽結構及其製造方法。
諸如淺溝槽隔離結構(shallow trench isolation；STI)等溝槽結構可用來分開與阻隔半導體晶圓上的主動區域。當電路密度增加時，淺溝槽隔離結構之溝槽寬度會減少，因而增加了淺溝槽隔離結構之溝槽的深寬比。溝槽(或間隙)之深寬比可為溝槽深度(或間隙高度)除以溝槽寬度(或間隙寬度)的值。當間隙填補不完整時，會產生不必要的空隙。當不必要的空隙在移除多餘介電材料的過程中露出時，會產生不必要的缺陷。不必要的空隙亦會導致主動區域之間的隔離不當。淺溝槽隔離結構之空隙的出現也會影響良率。
依據本揭露之一實施方式，一種半導體元件之溝槽結構包含基材、隔離結構、以及襯墊層。基材具有溝槽。 隔離結構係位於溝槽中。襯墊層係位於基材與隔離結構之間。.襯墊層包含氮，且襯墊層之不同位置的氮濃度不同。
依據本揭露之另一實施方式，一種形成半導體元件之溝槽結構的方法包含於基材之溝槽中形成可流動介電層。固化可流動介電層。退火固化的可流動介電層，以形成絕緣結構以及襯墊層，其中絕緣結構係形成於溝槽中，襯墊層係形成於絕緣結構與基材之間，襯墊層包含氮，且襯墊層之不同位置的氮濃度不同。
依據本揭露之再一實施方式，一種形成半導體元件之溝槽結構的方法包含蝕刻基材以形成溝槽。利用可流動介電層填充溝槽。對可流動介電層進行氧化處理。對氧化之可流動介電層進行至少一退火處理，以形成絕緣結構以及襯墊層，其中絕緣結構係形成於溝槽中，襯墊層係形成於絕緣結構與基材之間，襯墊層包含氮，且襯墊層之氮濃度係不均勻地分布。
110‧‧‧基材
112‧‧‧頂面
114‧‧‧溝槽
114s‧‧‧側壁
114b‧‧‧底面
115b‧‧‧底部
115t‧‧‧頂部
115m‧‧‧中間部
116‧‧‧主動區域
118‧‧‧半導體鰭片
120‧‧‧隔離結構
120’‧‧‧可流動介電層
125‧‧‧襯墊層
210‧‧‧遮罩層
212‧‧‧開口
220‧‧‧保護層
222‧‧‧開口
步驟310‧‧‧固化製程
步驟320‧‧‧熱退火製程
步驟330‧‧‧蒸氣熱退火製程
步驟340‧‧‧乾式熱退火製程
D‧‧‧深度
W‧‧‧寬度
本揭露之態樣最佳可從以下的詳細說明及隨附的圖式理解。值得注意的是，依據產業上的實際應用，各個特徵並未按照比例繪製，事實上，各個特徵的尺寸可以任意的放大或縮小，以利清楚地說明。
第1至8圖係繪示依據本揭露之部分實施方式之半導體元件之溝槽結構的製造過程中，於不同階段下的剖面圖。
以下提供本揭露之多種不同的實施方式或實施例，以實現本揭露的不同技術特徵。元件的實施例和配置係如下所述以簡化本揭露。當然，這些敘述僅為示例，而非用以限制本揭露。舉例而言，第一特徵係形成於第二特徵上之敘述可包括第一特徵與第二特徵係直接接觸的實施方式，亦可包括額外特徵形成於第一與第二特徵之間的實施方式，使得第一特徵與第二特徵可非直接接觸。此外，本揭露可重複地使用元件符號於多個實施例中。此重複係為了簡潔，並非用以討論各個實施方式及/或配置之間的關係。
另外，空間相對用語，如「下」、「下方」、「低」、「上」、「上方」等，是用以方便描述一元件或特徵與其他元件或特徵在圖式中的相對關係。除了圖式中所示之方位以外，這些空間相對用語亦可用來幫助理解元件在使用或操作時的不同方位。當元件被轉向其他方位(例如旋轉90度或其他方位)時，本文所使用的空間相對敘述亦可幫助理解。
除非有其他的定義，本文中之所有用語(包含技術上或科學上的用語)的含意與本技術領域中具有通常知識者所瞭解的含意相同。更可瞭解的是，除非本文額外地定義，否則本文中的用語之含意應與字典中同樣用語的含意相符合，而不應被解讀為理想化或過度正式的含意。
隨著半導體元件尺寸的縮小，因應半導體元件製程所產生的各種不同特徵亦隨之縮小。這樣的特徵之一為形成於主動區域之間以提供隔離作用的淺溝槽隔離結構。如 上所述，由於開口縮小，但溝槽的深度並未跟著縮小，故會導致深寬比的增加。用來填充具有低深寬比之溝槽的技術係難以填充具有高深寬比之溝槽。因此，本揭露提供半導體元件之溝槽結構與其製造方法。各個實施方式的製造方法中的中間過程係繪示於圖式中，且各個實施方式的各種變化亦會於本文中討論。
第1至8圖係繪示依據本揭露之部分實施方式之半導體元件之溝槽結構的製造過程中，於不同階段下的剖面圖。參照第1圖，基材110可被提供。基材110具有頂面112。於部分實施方式中，基材110可包含矽(Si)。可選地，基材110可包含鍺(Ge)、矽鍺(silicon germanium)、砷化鎵(gallium arsenide；GaAs)、或其他適合之半導體材料。可選地，基材110可包含磊晶層。舉例而言，基材110可具有覆蓋於塊狀半導體之磊晶層。進一步而言，基材110可產生應變以提升性能。舉例而言，磊晶層之材質可為不同於塊狀半導體的半導體材料，例如，磊晶層可為覆蓋於塊狀矽的矽鍺層或覆蓋於塊狀矽鍺的矽層，而此些磊晶層之形成方法可包含選擇性磊晶成長(selective epitaxial growth；SEG)。此外，基材110可包含絕緣底半導體(semiconductor-on-insulator；SOI)結構，例如埋入式介電層(buried dielectric layer)。可選地，基材110可包含埋入式介電層，例如埋入式氧化(buried oxide；BOX)層，而此埋入式介電層之形成方法可包含，但不限於，氧離子佈植分離法(separation by implantation of oxygen； SIMOX)、晶圓接合法(wafer bonding)、選擇性磊晶成長(selective epitaxial growth；SEG)或其他適合的方法。於不同之實施方式下可包含不同的基材結構與材料。
圖案化遮罩層210(可為硬式遮罩層)係形成於基材110之頂面112上方。在溝槽114以蝕刻之方式形成於基材110的過程中(如第2圖所示)，遮罩層210的圖案可完整地保留。於部分實施方式中，溝槽114中可填入過量的可流動介電層，而在移除此多餘的可流動介電層之過程中(如第8圖所示的步驟)，遮罩層210可做為平坦化製程的擋止層。於部分實施方式中，遮罩層210可包含氮。舉例而言，遮罩層210之材質為矽氮化物(silicon nitride；SiN)。然而，諸如矽氮氧化物(SiON)、矽碳化物(silicon carbide)、或其組合等材料亦可被使用。遮罩層210的厚度可約介於200奈米到1200奈米之間。遮罩層210之形成方法可包含，但不限於，化學氣相沉積(chemical vapor deposition；CVD)、電漿輔助化學氣相沉積(plasma enhanced chemical vapor deposition；PECVD)、或低壓化學氣相沉積(low pressure chemical vapor deposition；LPCVD)。可選地，遮罩層210的形成方法可包含先形成矽氧化物，再藉由氮化處理將矽氧化物轉換為矽氮化物。
於部分實施方式中，保護層220係形成於基材110之頂面112上方，且形成於遮罩層210與基材110之間。保護層220可保護頂面112，以防止頂面112直接接觸遮罩層210。舉例而言，對於鄰近溝槽114(如第2圖所示)的部分基 材110而言，保護層220可保護形成於該部分基材110中的主動區域116。上述溝槽114可被隔離結構120(如第8圖所示)所填充。在隔離結構120形成之後，主動區域116可用來形成元件(例如電晶體或電阻等元件)。主動區域116可包含n井(n-well)或p井(p-well)，而主動區域116所包含之井的種類，可取決於主動區域所形成的元件類型以及設計條件。於部分實施方式中，保護層220之材質為熱氧化物。保護層220的厚度可約介於20奈米到100奈米之間。當遮罩層210與保護層220形成後，遮罩層210與保護層220可透過適當的微影製程與蝕刻製程以進行圖案化處理，而於頂面112上方形成開口212與開口222，以製作第2圖所示之溝槽114。
參照第2圖。透過開口212與開口222所露出之部分基材110可藉由蝕刻製程來移除，藉此可形成溝槽114於基材110中。舉例來說，此蝕刻製程可為反應性離子蝕刻(reactive ion etching；RIE)製程。溝槽114係朝向基材110之頂面112，且隔開基材110之頂面112附近的主動區域116。溝槽114具有至少一側壁114s與底面114b。側壁114s係鄰接於基材110之頂面112，並連接基材110之頂面112與溝槽114之底面114b。於部分實施方式中，溝槽114的寬度W約介於20奈米到100奈米之間。於部分實施方式中，溝槽114的深度D約介於50奈米到350奈米之間。溝槽114的深寬比可大於7。此深寬比為溝槽114之深度D(亦即本文中的溝槽高度)除以溝槽114之寬度W所得到的值。於部分實施方式中，溝槽114之深寬比可大於8，此外，溝槽114之深寬比 亦可小於7或介於7與8之間。然而，本技術領域中具有通常知識者可理解到本文所載之尺寸與數值僅為例示性的，此尺寸與數值可變化以適用於不同尺度之半導體元件。
溝槽114具有底部115b與頂部115t。底部115b比頂部115t更接近底面114b。頂部115t係鄰接於基材110之頂面112。溝槽114進一步包含中間部115m，中間部115m係位於頂部115t與底部115b之間。於部分實施方式中，頂部115t、中間部115m、與底部115b可具有實質上相等的高度。
於部分實施方式中，半導體元件可為鰭式場效電晶體。溝槽114可配置以分隔形成於基材110中的相鄰兩半導體鰭片118。換句話說，半導體鰭片118之其中一者係位於相鄰兩溝槽114之間。
參照第3圖。可流動介電材料係填溢出溝槽114外與並覆蓋於遮罩層210上，以形成可流動介電層120’。可流動介電層120’之形成方法可為旋塗式介電材料(spin on dielectric；SOD)製程、或藉由化學氣相沉積(例如：自由基-成分化學氣相沉積(radical-component CVD))來沉積可流動介電材料。舉例而言，可流動矽氧化物前驅物包含矽酸鹽(silicate)、矽氧烷(siloxane)、甲基倍半矽氧烷(methyl SilsesQuioxane；MSQ)、氫基倍半矽氧烷(hydrogen SisesQuioxane；HSQ)、甲基倍半矽氧烷/氫基倍半矽氧烷(MSQ/HSQ)、全氫矽氮烷(perhydrosilazane；TCPS)、全氫聚矽氧烷(perhydro-polysilazane；PSZ)、 正矽酸乙酯(tetraethyl orthosilicate；TEOS)、或矽烷基胺(silyl-amine；SA)。
於部分實施方式中，可流動介電層120’係藉由含矽前驅物與另一前驅物(例如：由電漿所產生之「自由基-氮」前驅物)的反應所沉積而成。於部分實施方式中，含矽前驅物為無碳的且包含矽烷基胺，例如矽氮烷(H2N(SiH3))、二矽烷胺(HN(SiH3)2)、三矽氮烷(N(SiH3)3)、或其組合。矽烷基胺可與其他氣體混合，此氣體可做為載送氣體、反應氣體、或兩者皆可。此氣體可包含，但不限於，氫氣(H2)、氮氣(N2)、氨(NH3)、氦氣(He)、以及氬氣(Ar)。矽烷基胺亦可與其他無碳的含矽氣體混和，例如：矽烷(SiH4)、二矽烷(Si2H6)、氫(例如：氫氣)、及/或氮(例如：氮氣、氨)。
氮可包含於自由基前驅物、含矽前驅物、或兩者中。當自由基前驅物中含有氮時，其可稱為自由基-氮前驅物。自由基-氮前驅物包含電漿流出物，此電漿流出物係藉由激發電漿中的更穩定的含氮前驅物所形成的。舉例而言，相對穩定之含氮前驅物(其包含氨(NH3)及/或聯胺(N2H4))可於加工室內的電漿區域或於加工室外的遠端電漿系統(remote plasma system；RPS)之中所激發，以形成自由基-氮前驅物。接著，此自由基-氮前驅物會被傳送至無電漿之基材處理區域。穩定的氮前驅物亦可包含氨(NH3)、氮氣(N2)、及氫氣(H2)的混和物。
自由基-氮前驅物亦可伴有載送氣體，例如氬或 氦等。氧亦可同時輸送至遠端電漿區域(以氧氣及/或臭氧的形式)，以調節用於形成以本技術沈積的可流動介電層120’的自由基-氮前驅物中的含氧量。
可流動介電層120’的沉積可在基材110的溫度維持於相對低溫時進行。於部分實施方式中，在可流動介電層120’沉積於基材110的過程中，可藉由冷卻基材110以維持低溫。於部分實施方式中，沉積製程的溫度約介於-40℃到200℃之間。於部分實施方式中，沉積製程的溫度約小於100℃。
於部分實施方式中，沉積製程之壓力約介於100mTorr到10Torr之間。於部分實施方式中，反應源使用包含三甲矽烷基(Si3H9N；TSA)及氨(NH3)的氣體環境。於部分實施方式中，三甲矽烷基的流率約介於100sccm到1000sccm之間，而氨的流率約介於100sccm到2000sccm之間。
沉積完成之可流動介電層120’能夠填充於窄且深的間隙中，並防止溝槽114中產生空隙與結構中斷。沉積完成之可流動介電層120’包含氫氮氧矽化物(SiOANBHC)(或氫氮氧化矽(SiONH))的可流動網狀物。於部分實施方式中，A為約介於0.8到2之間的數字，B為約介於0.01到1之間的數字，而C為約介於0.01到1之間的數字。於部分實施方式中，於遮罩層210上方之可流動介電層120’的厚度約介於1000埃(angstrom；Å)到3000埃之間。
參照第4圖。在可流動介電層120’沉積之後， 於沉積完成之可流動介電層120’之上可執行原位(in-situ)固化製程310。「原位」代表於固化製程310係在沉積可流動介電層120’之加工室中所進行的。於部分實施方式中，固化製程310可於不同的加工室中進行(或稱為異位；ex-situ)。
於部分實施方式中，固化製程310係使用臭氧(氧化處理)來進行，此臭氧之流率約介於100sccm到5000sccm之間。固化製程310亦可使用蒸氣來進行，此蒸氣之流率約介於100sccm到5000sccm之間。於部分實施方式中，固化製程310之溫度約介於10℃到500℃之間。可選地，蒸氣可於固化製程中取代臭氧。於部分實施方式中，固化製程310之壓力約介於1Torr到760Torr之間。於部分實施方式中，固化製程310之持續時間約介於10秒到2小時之間。當沉積完成之可流動介電層120’係由氫氮氧矽化物(或氫氮氧化矽)之網狀物所形成時，固化製程310可增加沉積完成之可流動介電層120’之氧含量，並移除可流動介電層120’的多數氮氫離子與氫離子。
參照第5圖。額外的熱退火製程320可被執行，其可將氫氮氧矽化物的網狀物轉變為氧化矽(或二氧化矽)的網狀物。熱退火製程的溫度約介於200℃到1100℃之間。諸如蒸氣等氧源可被提供以協助將氫氮氧矽化物的網狀物轉變為氧化矽的網狀物。
參照第6圖。當上述之熱退火製程320完成後，基材110可被施以蒸氣熱退火製程330。水蒸氣可將氫氮氧 矽化物的網狀物轉變為氫氧化矽(SiOH)及氧化矽(SiO)的網狀物。於部分實施方式中，蒸氣熱退火製程330係於加熱爐內所進行的。於部分實施方式中，蒸氣熱退火製程330之溫度約介於150℃到800℃之間。於部分實施方式中，蒸氣熱退火製程330之初始溫度約為150℃，且溫度可逐漸上升至約介於500℃至800℃之間的預定溫度。蒸氣熱退火製程330的壓力約介於500Torr到800Torr之間。蒸氣熱退火製程330之蒸氣流率約介於1slm到20slm之間。蒸氣熱退火製程330之持續時間大約介於20分鐘到2小時之間。蒸氣熱退火製程330可將可流動介電層120’中的氫氮氧矽化物的網狀物轉變為氫氧化矽(SiOH)及氧化矽(SiO)的網狀物。蒸氣熱退火製程330可造成可流動介電層120’的收縮。蒸氣熱退火製程330之持續時間與溫度會影響可流動介電層120’的收縮量。
參照第7圖。當上述蒸氣熱退火製程330完成後，乾式(無蒸氣)熱退火製程340被執行，其可將氫氧化矽(SiOH)及氧化矽(SiO)的網狀物轉變為氧化矽(或二氧化矽)的網狀物。乾式熱退火製程340中係不使用蒸氣的。於部分實施方式中，乾式熱退火製程340中可使用惰性氣體，例如氮氣。於部分實施方式中，乾式熱退火製程340的最高退火溫度約介於1000℃到1200℃之間。於部分實施方式中，乾式熱退火製程340係於加熱爐內進行的。乾式熱退火製程340之壓力約介於500Torr到800Torr之間。乾式熱退火製程340所使用之氣體可包含惰性氣體，例如氮氣、氬 氣、氦氣、或其組合。乾式熱退火製程340之持續時間約介於30分鐘到3小時之間。乾式熱退火製程340可將可流動介電層120’中的氫氧化矽(SiOH)及氧化矽(SiO)的網狀物轉變為氧化矽(或二氧化矽)的網狀物。乾式熱退火製程340亦可造成可流動介電層120’進一步地收縮。乾式熱退火製程340之持續時間與溫度會影響可流動介電層120’的收縮量。
蒸氣熱退火製程330及乾式熱退火製程340可造成可流動介電層120’的收縮。於部分實施方式中，可流動介電層120’的體積收縮約介於5%到20%之間。退火製程(步驟330與340)之持續時間會影響可流動介電層120’的收縮量。
當第6圖所示之蒸氣熱退火製程330與第7圖所示之乾式熱退火製程340完成後，襯墊層(liner layer)125可形成而覆蓋溝槽114與複數半導體鰭片118，並與溝槽114與半導體鰭片118的形狀相符。襯墊層125係藉由可流動介電層120’之沉積與退火製程所形成的。換句話說，襯墊層125與隔離結構120係共同形成的。襯墊層125可包含氮。襯墊層125之材質可為矽氮氧化物(silicon oxynitride)，但不限於此。
襯墊層125之不同位置的氮濃度不同。換句話說，襯墊層125之氮濃度係不均勻地分布。舉例而言，位於槽溝114之頂部115t的襯墊層125之氮濃度係高於位於槽溝114之底部115b的襯墊層125之氮濃度。這樣的氮濃度分佈係由於在固化製程與退火製程中，遮罩層210之氮會擴散至 可流動介電層120’中所造成的。因此，位於頂部115t之襯墊層125的氮濃度較高。此外，位於底部115b之可流動介電層120’的氮氫離子濃度係高於位於頂部115t之可流動介電層120’的氮氫離子濃度。這樣的氮氫離子濃度分佈係由於在固化製程中，可流動介電層120’的沉澱物及/或位於底部115b之氮氫離子不易移除所造成的。因此，位於底部115b之襯墊層125包含一定的氮含量。雖然位於底部115b之襯墊層125的氮濃度係低於位於頂部115t之襯墊層125的氮濃度，但位於底部115b之襯墊層125的氮濃度係高於位於中間部115m之襯墊層125的氮濃度。此外，位於頂部115t之襯墊層125的氮濃度係高於位於中間部115m之襯墊層125的氮濃度。於部分實施方式中，位於頂部115t之襯墊層125的氮濃度、位於中間部115m之襯墊層125的氮濃度，以及位於底部115b之襯墊層125的氮濃度的比例可實質上為4：1：2，但不限於此。
參照第8圖。當第7圖所示之乾式熱退火製程340完成後，第7圖所示之可流動介電層120’會轉變為二氧化矽。於溝槽114外的可流動介電層120’可藉由平坦化製程移除，以形成隔離結構120。於部分實施方式中，平坦化製程為化學機械研磨(chemical-mechanical polishing；CMP)製程。於部分實施方式中，平坦化製程可移除溝槽114外的可流動介電層120’。於部分實施方式中，平坦化製程亦可移除遮罩層210及保護層220(如第7圖所示)。於部分實施方式中，平坦化製程可移除遮罩層210，而保護層220則 可藉由蝕刻製程所移除。
當遮罩層210、保護層220與溝槽114外之多餘的可流動介電層120’被移除後，溝槽結構被形成。於部分實施方式中，閘極介電層與閘極電極層(未示於圖式)可形成於半導體鰭片118上或上方，以形成鰭式場效電晶體。
於第8圖中，溝槽結構包含基材110、隔離結構120、以及襯墊層125。基材110具有溝槽114。隔離結構120係位於溝槽114中。襯墊層125係位於在基材110與隔離結構120之間。襯墊層125包含氮，且襯墊層125之不同位置的氮濃度不同。換句話說，襯墊層125的氮濃度係不均勻地分布。於部分實施方式中，半導體元件之溝槽結構可為淺溝槽隔離結構，但不限於此。
更詳細地說，襯墊層125係鄰接於基材110與隔離結構120。襯墊層125亦覆蓋至少一半導體鰭片118。舉例而言，於第8圖中，襯墊層125覆蓋半導體鰭片118。襯墊層125可為共形層(conformal layer)，此共形層的水平部位之厚度與垂直部位之厚度相近。襯墊層125提供幾種不同的作用，例如：減少基材110中的應力；提供一些最小圓角於溝槽114之角落；以及在移除多餘的可流動介電層120’的平坦化製程中，提供一定程度的保護以防止凹陷形成。於部分實施方式中，襯墊層125之材質為矽氮氧化物(silicon oxynitride)，而隔離結構120之材質為二氧化矽。
依據上述實施方式，可流動介電層可填充溝槽。在沉積過程中，可流動介電層可流動以填充溝槽中的空 隙。此技術可用於填充具有高深寬比或低深寬比之溝槽。此外，由於襯墊層與隔離結構可在同一製程中形成，故額外預形成之襯墊層可被省略。因此，製造時間及成本可被降低。利用隔離結構所形成之襯墊層之不同位置的氮濃度不同。換句話說，襯墊層的氮濃度為不均勻地分布。
雖然上述實施方式係以淺溝槽隔離結構進行說明，但本發明所屬技術領域中具有通常知識者可理解本文亦適用於其他具有良好介電特性且可填充溝槽或間隙的結構，特別是可填充具有高深寬比之溝槽或間隙的結構。
前述多個實施方式的特徵可使本技術領域中具有通常知識者更佳地理解本揭露之各個態樣。本技術領域中具有通常知識者應可瞭解，為了達到相同之目的及/或本揭露之實施方式之相同優點，其可利用本揭露為基礎，進一步設計或修飾其他製程及結構。在本技術領域中具有通常知識者亦應瞭解，這樣的均等結構並未背離本揭露之精神及範圍，而在不背離本揭露之精神及範圍下，本技術領域中具有通常知識者可在此進行各種改變、替換及修正。
110‧‧‧基材
114‧‧‧溝槽
115t‧‧‧頂部
115m‧‧‧中間部
120‧‧‧隔離結構
125‧‧‧襯墊層
115b‧‧‧底部
118‧‧‧半導體鰭片

Claims (10)

  1. 一種半導體元件之溝槽結構，包含：一基材，具有一溝槽；一隔離結構，位於該溝槽中；以及一襯墊層，位於該基材與該隔離結構之間，其中該襯墊層位於該溝槽之頂部的含氮濃度高於位於該溝槽之底部的含氮濃度。
  2. 如請求項1所述之溝槽結構，其中該溝槽包含一底面以及至少一側壁，該襯墊層覆蓋該底面及該側壁。
  3. 如請求項1所述之溝槽結構，其中該溝槽更包含一中間部，位於該溝槽之頂部與該溝槽之底部之間，該襯墊層位於該溝槽之頂部的氮濃度係高於位於該中間部的氮濃度。
  4. 如請求項1所述之溝槽結構，其中該溝槽更包含一中間部，位於該溝槽之頂部與該溝槽之底部之間，該襯墊層位於該溝槽之底部的氮濃度係高於位於該中間部的氮濃度。
  5. 如請求項1所述之溝槽結構，其中該基材更包含： 複數半導體鰭片，其中該溝槽係位於該些半導體鰭片之其中相鄰兩者之間，其中該襯墊層覆蓋該些半導體鰭片之至少其中一者，並與該些半導體鰭片之至少其中該者的形狀相符。
  6. 一種形成半導體元件之溝槽結構的方法，包含：於一基材之一溝槽中形成一可流動介電層；固化該可流動介電層；以及退火該固化的可流動介電層，以形成一絕緣結構以及一襯墊層，其中該絕緣結構係形成於該溝槽中，該襯墊層係形成於該絕緣結構與該基材之間，該襯墊層位於該溝槽之頂部的含氮濃度高於位於該溝槽之底部的含氮濃度。
  7. 如請求項6所述之方法，更包含：於該基材中形成複數半導體鰭片，其中該溝槽係形成於該些半導體鰭片之其中相鄰兩者之間；以及於該些半導體鰭片之至少其中一者上形成一遮罩層，其中該襯墊層之一部分係形成於該遮罩層與該些半導體鰭片之至少其中該者之間，其中該遮罩層包含氮。
  8. 如請求項6所述之方法，其中該退火包含：進行一蒸氣熱退火；以及進行一乾式熱退火。
  9. 一種形成半導體元件之溝槽結構的方法，包含：蝕刻一基材以形成一溝槽；利用一可流動介電層填充該溝槽；對該可流動介電層進行氧化處理；以及對該氧化之可流動介電層進行至少一退火處理，以形成一絕緣結構以及一襯墊層，其中該絕緣結構係形成於該溝槽中，該襯墊層係形成於該絕緣結構與該基材之間，該襯墊層位於該溝槽之頂部的含氮濃度高於位於該溝槽之底部的含氮濃度。
  10. 如請求項9所述之方法，其中複數半導體鰭片係在該溝槽形成的過程中所形成的，且該溝槽係位於該些半導體鰭片之其中兩者之間，該方法更包含：形成一遮罩層於該些半導體鰭片之至少其中一者上，且該遮罩層包含氮。
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