CN106409749A - 半导体器件的沟槽结构及其制造方法 - Google Patents

半导体器件的沟槽结构及其制造方法 Download PDF

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CN106409749A
CN106409749A CN201610071466.XA CN201610071466A CN106409749A CN 106409749 A CN106409749 A CN 106409749A CN 201610071466 A CN201610071466 A CN 201610071466A CN 106409749 A CN106409749 A CN 106409749A
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lining
groove
substrate
nitrogen
dielectric layer
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CN106409749B (zh
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林加明
张简旭珂
林俊泽
王英郎
林玮耿
刘全璞
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Abstract

本发明提供一种半导体器件的沟槽结构，包括衬底、隔离结构和衬层。衬底中具有沟槽。隔离结构设置在沟槽中。衬层设置在衬底和隔离结构之间。衬层包括氮，并且衬层在空间上具有不同的氮浓度。本发明还提供了一种制造半导体器件的沟槽结构的方法。

Description

半导体器件的沟槽结构及其制造方法
技术领域
本发明总体涉及半导体领域，更具体地，涉及半导体器件的沟槽结构及其制造方法。
背景技术
诸如浅沟槽隔离件(STI)的沟槽结构用于将半导体晶圆上的各有源区域彼此分离并且隔离。随着电路密度不断增加，STI的沟槽的宽度不断减小，从而增加了STI沟槽的高宽比。将沟槽(或间隙)的高宽比定义为沟槽高度(或间隙高度)除以沟槽宽度(或间隙宽度)。不完全的间隙填充导致不期望的空隙，并且在去除多余的电介质期间暴露不期望的空隙时，不期望的间隙填充增大了包括不期望的缺陷的风险。这些空隙还可以导致各有源区域之间的不充分的隔离。STI中的空隙的存在会影响产率。
发明内容
根据本发明的一个方面，提供了一种半导体器件的沟槽结构，包括：衬底，所述衬底中具有沟槽；隔离结构，设置在所述沟槽中；以及衬层，设置在所述衬底与所述隔离结构之间，其中，所述衬层包括氮，并且所述衬层在空间上具有不同的氮浓度。
优选地，所述沟槽具有底面和至少一个侧壁，并且所述衬层覆盖所述底面和所述侧壁。
优选地，所述沟槽还具有顶部和底部，所述底部比所述顶部更靠近所述底面，并且所述衬层在所述顶部处的氮浓度高于所述衬层在所述底部处的氮浓度。
优选地，所述沟槽还具有设置在所述顶部和所述底部之间的中间部分，并且所述衬层在所述顶部处的氮浓度高于所述衬层在所述中间部分处的氮浓度。
优选地，所述沟槽还具有设置在所述顶部和所述底部之间的中间部分，并且所述衬层在所述底部处的氮浓度高于所述衬层在所述中间部分处的氮浓度。
优选地，所述衬底还包括：多个半导体鳍部，其中，所述沟槽设置在所述多个半导体鳍部中的邻近的两个半导体鳍部之间。
优选地，所述衬层共形地覆盖所述半导体鳍部中的至少一个。
优选地，所述衬层由氮氧化硅制成。
优选地，所述衬层设置为邻近所述衬底。
根据本发明的另一方面，提供了一种用于形成半导体器件的沟槽结构的方法，包括：在衬底的沟槽中形成可流动介电层；固化所述可流动介电层；以及对所述固化的可流动介电层进行退火以形成绝缘结构和衬层，其中，所述绝缘结构形成在所述沟槽中，所述衬层形成在所述绝缘结构与所述衬底之间，所述衬层包括氮，并且所述衬层在空间上具有不同的氮浓度。
优选地，所述衬层由氮氧化硅制成。
优选地，该方法还包括：在所述衬底中形成多个半导体鳍部，其中，所述沟槽形成在所述多个半导体鳍部中的邻近的两个半导体鳍部之间。
优选地，该方法还包括：在所述半导体鳍部中的至少一个上形成掩模层，其中，所述衬层的一部分形成在所述掩模层与所述半导体鳍部之间。
优选地，所述掩模层包括氮化物。
优选地，用于沉积所述可流动介电层的源气体是三甲硅烷基胺(TSA)。
优选地，所述退火包括：执行蒸汽热退火；以及执行干热退火。
优选地，使用臭氧(O3)来固化所述可流动介电层。
优选地，该方法还包括：执行平坦化工艺以去除所述沟槽外部的多余的可流动介电层。
根据本发明的又一方面，提供了一种用于形成半导体器件的沟槽结构的方法，包括：蚀刻衬底以形成沟槽；利用可流动介电层填充所述沟槽；对所述可流动介电层执行氧化处理；以及对所述氧化的可流动介电层执行至少一种退火处理以形成绝缘结构和衬层，其中，所述绝缘结构形成在所述沟槽中，所述衬层形成在所述绝缘结构与所述衬底之间，所述衬层包括氮，并且所述衬层的氮浓度非均匀分布。
优选地，在形成所述沟槽期间形成多个半导体鳍部，并且所述沟槽设置在所述多个半导体鳍部中的两个半导体鳍部之间，所述方法还包括：在所述多个半导体鳍部中的至少一个上形成掩模层，并且所述掩模层包括氮。
附图说明
当结合附图进行阅读时，根据下面详细的描述可以更好地理解本发明的各个方面。应该强调的是，根据工业中的标准实践，各种部件没有被按比例绘制。实际上，为了清楚的讨论，各种部件的尺寸可以被任意增加或减少。
图1至图8是根据本发明的一些实施例的处于各个阶段中的制造半导体器件的沟槽结构的方法的截面图。
具体实施方式
以下公开内容提供了许多不同实施例或实例，用于实现所提供主题的不同特征。以下将描述组件和布置的特定实例以简化本发明。当然，这些仅是实例并且不意欲限制本发明。例如，在以下描述中，在第二部件上方或上形成第一部件可以包括第一部件和第二部件直接接触的实施例，也可以包括形成在第一部件和第二部件之间的附加部件使得第一部件和第二部件不直接接触的实施例。另外，本发明可以在多个实例中重复参考标号和/或字符。这种重复是为了简化和清楚的目的，并且其本身不指示所讨论的各个实施例和/或配置之间的关系。
此外，为了便于描述，本文中可以使用诸如“在…下方”、“在…下面”、“下部”、“在…上面”、“上部”等空间关系术语以描述如图所示的一个元件或部件与另一元件或部件的关系。除图中所示的方位之外，空间关系术语意欲包括使用或操作过程中的器件的不同的方位。装置可以以其它方式定位(旋转90度或在其他方位)，并且在本文中使用的空间关系描述符可同样地作相应地解释。
除非以其他方式限定，否则本文所使用的所有术语(包括技术术语和科学术语)都具有与本发明所属于的领域的普通技术人员通常理解的相同的意思。还应该理解，除非本文清楚地限定，否则，诸如常用的字典中限定的那些的术语应该被理解为具有与其在相关领域和本发明的内容中的意思一致的意思，并且不应该以理想化和过于正式的形式来解释。
随着半导体器件的尺寸减小，与形成半导体器件相关的各个部件的尺寸也减小。其中一个这样的部件是形成在有源区域之间以提供隔离的浅沟槽隔离件(STI)。如所讨论的，因为沟槽的开口变小而深度却不变，所以部件尺寸的减小导致高宽比增大。用于填充具有较低高宽比的沟槽的技术难以用于充分填充具有高高宽比技术的沟槽。因此，提供了半导体器件的沟槽结构以及用于制造沟槽结构的方法。示出了制造过程的实施例的中间阶段，并且还讨论了这些实施例的变形。
图1至图8是根据本发明的一些实施例的制造半导体器件的沟槽结构的方法在各个阶段中的截面图。参考图1。提供衬底110。衬底110具有顶面112。在一些实施例中，衬底110可以包括硅(Si)。可选地，衬底110可以包括锗(Ge)、硅锗、砷化镓(GaAs)或其他适当的半导体材料。同样可选地，衬底110可以包括外延层。例如，衬底110可以具有位于块状半导体上面的外延层。此外，衬底110可以受到应变从而改善性能。例如，外延层可以包括与块状半导体的半导体材料不同的半导体材料，诸如通过包括选择性外延生长(SEG)的工艺而形成的位于块状硅上面的硅锗层或位于块状硅锗上面的硅层。此外，衬底110可以包括诸如掩埋介电层的绝缘体上半导体(SOI)结构。同样可选地，衬底110可以包括通过诸如注氧隔离(SIMOX)技术、晶圆接合、SEG的方法或其他适当的方法而形成的诸如埋氧(BOX)层的掩埋介电层。各个实施例可以包括任何种类的衬底结构和材料。
图案化的掩模层210(可以是硬掩模层)形成在衬底110的顶面112上方。掩模层210在蚀刻形成在衬底110中的沟槽114(见图2)期间维持图案的完整性。在一些实施例中，在去除多余的填充沟槽114的可流动介电层期间(在图8的工艺中进行讨论)，掩模层210用作平坦化停止层。在一些实施例中，掩模层210包括氮化物。例如，掩模层210由氮化硅(SiN)制成。然而，也可以使用诸如SiON、碳化硅或它们的组合的其他材料。掩模层210的厚度可以在从大约200nm至大约1200nm的范围内。可以通过诸如化学汽相沉积工艺沉积(CVD)、等离子体增强的化学汽相沉积(PECVD)、低压化学汽相沉积(LPCVD)的工艺来形成掩模层210。可选地，掩模层210可以首先由氧化硅制成，然后通过氮化转换为SiN。
在一些实施例中，保护层220形成在衬底110的顶面112上方以及掩模层210与衬底110之间。保护层220保护顶面112免于与掩模层210直接接触。例如，对于衬底110中邻近于被绝缘结构120(见图8)填充的沟槽114的部分，保护层220可以保护形成在衬底110的这部分中的有源区域116。在形成绝缘结构120之后，有源区域116用于形成器件(诸如晶体管、电阻器等)。取决于将要形成的器件，有源区域116可以包括由设计条件所确定的n阱和p阱中的任一种。在一些实施例中，保护层220由热氧化物制成。保护层220的厚度可以在从大约20nm至大约100nm的范围内。一旦形成掩模层210和保护层220，就通过合适的光刻和蚀刻工艺将它们图案化以在顶面112上方形成用于图2的沟槽114的开口212和222。
参考图2。通过诸如反应离子蚀刻(RIE)的蚀刻工艺来去除衬底110中通过开口212和222暴露的部分，从而在衬底110中形成沟槽114。沟槽114面向衬底110的顶面112并且分离靠近衬底110的顶面112的有源区域116。沟槽114具有至少一个侧壁114s和底面114b。侧壁114s邻近衬底110的顶面112并且连接衬底110的顶面112和沟槽114的底面114b。在一些实施例中，沟槽114的宽度W在从大约20nm至大约100nm的范围内。在一些实施例中，沟槽114的深度D在从大约50nm至大约350nm的范围内。沟槽114的高宽比(即，深度D(有时本文也称为沟槽高度)除以宽度W)可以约大于7。在其他一些实施例中，高宽比甚至可以约大于8，但是也可以约低于7或介于7与8之间。然而，本领域技术人员将认识到，贯穿说明书所列举的尺寸和值仅仅是实例，可以将其改变以适应不同规模的半导体器件。
沟槽114具有底部115b和顶部115t。底部115b比顶部115t更靠近底面114b，而顶部115t邻近衬底110的顶面112。沟槽114还具有介于顶部115t与底部115b之间的中间部分115m。在一些实施例中，顶部115t、中间部分115m和底部115b可以具有基本相同的高度。
在一些实施例中，半导体器件可以是鳍式场效应晶体管(FinFET)，并且沟槽114被配置为隔离形成在衬底110中的两个邻近的半导体鳍部118。换句话说，半导体鳍部118中的一个设置在邻近的两个沟槽114之间。
参考图3。可流动介电材料过填充沟槽114和掩模层210以形成可流动介电层120'。可以通过使用旋涂电介质(SOD)形成工艺或通过利用CVD沉积工艺(诸如自由基成分(radical-component)化学汽相沉积(CVD))来沉积可流动电介质从而形成可流动介电层120'。可流动氧化硅前体的实例包括硅酸盐、硅氧烷、甲基倍半硅氧烷(MSQ)、氢倍半硅氧烷(HSQ)、MSQ/HSQ、全氢硅氮烷(TCPS)、全氢-聚硅氮烷(PSZ)、正硅酸乙酯(TEOS)或甲硅烷基胺(SA)。
在一些实施例中，通过将含硅前体与另一前体(诸如由等离子体生成的“自由基-氮”)反应来沉积可流动介电层120'。在一些实施例中，含硅前体不含碳但是包括甲硅烷基胺，诸如H2N(SiH3)、HN(SiH3)2、N(SiH3)3或它们的组合。甲硅烷基胺可与用作载气、反应气体或两者的附加气体相混合。附加气体的实例可包括H2、N2、NH3、He和Ar等。甲硅烷基胺还可以与其他不含碳的含硅气体(诸如硅烷(SiH4)和乙硅烷(Si2H6)、氢(如，H2)和/或氮(如，N2、NH3))混合。
氮可以包括在自由基前体和含硅前体的任何一个中或包括在两者中。当氮存在于自由基前体中时，其可以称为自由基-氮前体。自由基-氮前体包括通过激发等离子体中较稳定的含氮前体而产生的等离子体废物。例如，可以在反应室等离子体区域或在处理室外的远程等离子体系统(RPS)中激活包含NH3和/或肼(N2H4)的相对稳定的含氮前体，以形成自由基-氮前体，然后将其传输至不含等离子体的衬底处理区域中。稳定的氮前体还可以是包括NH3、N2和H2的组合的混合物。
自由基-氮前体还可以附带诸如氩、氦等的载气。同时，氧(以O2和/或O3的形式)可以输送至远程等离子体区域中以调整用于形成以该技术沉积的可流动介电层120'的自由基-氮前体中的氧含量的多少。
可以在将衬底110的温度维持在相对较低的温度的同时进行可流动介电层120'的沉积。在一些实施例中，在低温条件下(在沉积期间通过冷却衬底110而维持这种低温)，将可流动介电层120'沉积在衬底110上。在一些实施例中，在大约-40℃和大约200℃之间的范围内的温度下进行沉积。在一些实施例中，在低于大约100℃的温度下进行沉积。
在一些实施例中，沉积压力在从大约100mTorr至大约10Torr的范围内。在一些实施例中，反应源使用包括三甲硅烷基胺(Si3H9N或TSA)和NH3的气体性环境。在一些实施例中，Si3H9N和NH3的流量分别在从大约100sccm至大约1000sccm之间的范围内和在从大约100sccm至大约2000sccm的范围内。
所沉积的可流动介电层120'能够填充窄而深的间隙并且防止沟槽114中的空隙和缺口。所沉积的可流动介电层120'包括SiOANBHC(或SiONH)的可流动网络结构(network)。在一些实施例中，A为在大约0.8至大约2的范围内的数字，B为在从大约0.01至大约1的范围内的数字，以及C为从大约0.01至大约1的范围内的数字。在一些实施例中，可流动介电层120'在掩模层210上面的厚度在大约1000埃至大约3000埃的范围内。
参考图4。在沉积可流动介电层120'之后，可以对所沉积的介电层120'执行原位固化工艺310。原位意味着在用于沉积可流动介电层120'的工艺室中执行固化工艺310。在一些实施例中，可以在不同的室中(或非原位)执行固化工艺310。
在一些实施例中，使用具有在大约100sccm至大约5000sccm的范围内的流率的臭氧(O3)(氧化处理)或使用具有在大约100sccm至大约5000sccm范围内的流率的蒸汽来操作固化工艺310。在一些实施例中，固化工艺310的温度在大约10℃至大约500℃的范围内。可选地，可以在固化工艺期间使用蒸汽来代替O3。在一些实施例中，固化工艺310的压力范围从大约1Torr至大约760Torr。根据一些实施例，固化工艺310的持续时间在大约10秒至大约2小时的范围内。固化工艺310增加了所沉积的可流动介电层120'的氧含量，该可流动介电层由SiOANBHC(或SiONH)的网络结构制成，并且可流动介电层120'的大部分NH离子和H离子可以被去除。
参考图5。为了将SiONH网络结构转换为SiO(或SiO2)网络结构，可以执行附加的热退火320。在大约200℃至大约1100℃的范围内的温度下进行热退火。可以提供诸如蒸汽的氧气源以帮助SiONH网络结构转换为SiO网络结构。
参考图6。在执行以上描述的热退火320之后，衬底110经受蒸汽热退火工艺330。蒸汽(H2O)将SiONH网络结构转换为SiOH和SiO网络结构。在一些实施例中，在炉中进行蒸汽热退火工艺330。在一些实施例中，在大约150℃至大约800℃的范围内的温度下进行蒸汽热退火工艺330。在温度150℃下开始蒸汽热退火工艺330，并且温度逐渐上升至大约500℃至大约800℃的预定温度。蒸汽热退火工艺330的压力在大约500Torr至大约800Torr的范围内。蒸汽的流率在约1slm到约20slm的范围内。蒸汽热退火工艺330的持续时间在大约20分钟至大约2小时的范围内。蒸汽热退火工艺330将可流动介电层120'中的SiONH网络结构转换为SiOH和SiO网络结构。蒸汽热退火工艺330导致了可流动介电层120'的收缩。蒸汽热退火工艺330的持续时间和温度影响收缩量。
参考图7。在以上描述的蒸汽热退火工艺330之后，进行“干”(没有蒸汽)热退火工艺340以将SiOH和SiO网络结构转换为SiO(或SiO2)网络结构。在干热退火工艺340期间，未使用蒸汽。在一些实施例中，在干热退火工艺340期间，使用惰性气体，诸如N2。在一些实施例中，干热退火工艺340的峰值退火温度在大约1000℃至大约1200℃的范围内。在一些实施例中，在炉中进行干热退火工艺340。干热退火工艺340的压力在大约500Torr至大约800Torr的范围内。干热退火工艺340使用的气体可以包括惰性气体，诸如N2、Ar、He或它们的组合。干热退火工艺340的持续时间在大约30分钟至大约3小时的范围内。干热退火工艺340将可流动介电层120'中的SiOH和SiO网络结构转换为SiO(或SiO2)。干热退火工艺340也导致可流动介电层120'的进一步收缩。干热退火工艺340的持续时间和温度影响收缩量。
蒸汽热退火工艺330和干热退火工艺340导致了可流动介电层120'的收缩。在一些实施例中，可流动介电层120'的体积的收缩范围从大约5％至大约20％。退火工艺(330和340)的持续时间影响收缩量。
在图6的蒸汽热退火工艺330和图7的干热退火工艺340之后，形成衬层125以共形地覆盖沟槽114和半导体鳍部118。由于可流动介电层120'的沉积和退火工艺而形成衬层125。即，衬层125与隔离结构120一起形成。衬层125包括氮，并且可以由氮氧化硅制成，但所要保护的范围并不限于此。
衬层125在空间上具有不同的氮浓度。换句话说，衬层125的氮浓度非均匀分布。例如，衬层125在沟槽114的顶部115t处的氮浓度高于衬层125在沟槽114的底部115b处的氮浓度。这是因为可以包括氮的掩模层210中的氮可以在固化和退火工艺期间扩散至可流动介电层120'。因此，衬层125在顶部115t处的氮浓度更高。另一方面，可流动介电层120'在底部115b处的NH离子的浓度比在顶部115t处高。这可能是因为在固化工艺期间底部115b处的可流动介电层120'的沉淀和/或NH离子难以被去除。因此，底部115b处的衬层125包括一定量的氮。尽管衬层125在底部115b处的氮浓度低于衬层125在顶部115t处的氮浓度，但是衬层125在底部115b处的氮浓度高于衬层125在中间部分115m处的氮浓度。同样，衬层125在顶部115t处的氮浓度高于衬层125在中间部分115m处的氮浓度。在一些实施例中，衬层125在顶部115t处、在中间部分115m处以及在底部115b处的氮浓度可以基本为4：1：2，但所要保护的范围并不限于此。
参考图8。在图7的干退火工艺之后，将图7的可流动介电层120'转换为SiO2，并且执行平坦化工艺350以去除沟槽114外部的可流动介电层120'以形成隔离结构120。在一些实施例中，平坦化工艺是化学机械抛光(CMP)工艺。在一些实施例中，平坦化工艺去除沟槽114外部的可流动介电层120'。在一些实施例中，平坦化工艺还去除掩模层210和保护层220(见图7)。在一些实施例中，平坦化工艺去除掩模层210，然而通过蚀刻工艺去除保护层220。
在去除沟槽114外部多余的可流动介电层120'以及去除掩模层210和保护层220之后，形成沟槽结构。在一些实施例中，可以在半导体鳍部118上或上面形成栅极介电层和栅电极(未示出)以形成FinFET。
在图8中，沟槽结构包括衬底110、隔离结构120和衬层125。衬底110具有沟槽114。在沟槽114中沉积隔离结构120。衬层125设置在衬底110和隔离结构120之间。衬层125包括氮，并且衬层125在空间上具有不同的氮浓度。换句话说，衬层125的氮浓度非均匀分布。在一些实施例中，半导体器件的沟槽结构是浅沟槽绝缘(STI)结构，但所要保护的范围并不限于此。
更加具体地，衬层125设置为邻近衬底110和隔离结构120。衬层125还覆盖至少一个半导体鳍部118。例如，在图8中，衬层125覆盖半导体鳍部118。衬层125可以是其水平部分和垂直部分具有彼此接近的厚度的共形层。衬层125起到若干作用，包括减小衬底110中的应力、使沟槽114角部的圆化程度最小以及在去除多余的可流动介电层120'的平坦化过程期间提供防止空缺形成的一些保护。在一些实施例中，衬层125是氮氧化硅，并且隔离结构120是二氧化硅(SiO2)。
根据前述实施例，沟槽填充有可流动介电层。可流动介电层可以在沉积期间“流动”以填充沟槽中的空隙。该技术可以用于填充具有高或低的高宽比的沟槽。此外，由于衬层和隔离结构都在同一制造工艺期间形成，所以可以省略附加的预形成的衬层。因此，可以减少制造时间和成本。与隔离结构一起形成的衬层具有在空间上不同的氮浓度。换句话说，衬层的氮浓度非均匀分布。
尽管参考STI结构描述了以上实施例，但是本领域的普通技术人员将理解，本发明可以应用于各种其他的结构，其中，期望以高质量电介质填充沟槽或间隙，尤其是具有高高宽比的沟槽或间隙。
根据一些实施例，半导体器件的沟槽结构包括衬底、隔离结构和衬层。衬底中具有沟槽。隔离结构设置在沟槽中。衬层设置在衬底和隔离结构之间。衬层包括氮，并且衬层具有在空间上不同的氮浓度。
根据一些实施例，用于形成半导体器件的沟槽结构的方法包括在衬底的沟槽中形成可流动介电层。固化可流动介电层。退火固化的可流动介电层以形成绝缘结构和衬层。绝缘结构形成在沟槽中，衬层形成在绝缘结构与衬底之间，衬层包括氮，并且衬层具有在空间上不同的氮浓度。
根据一些实施例，用于形成半导体器件的沟槽结构的方法包括蚀刻衬底以形成沟槽。利用可流动介电层填充沟槽。对可流动介电层执行氧化处理。对氧化的可流动介电层执行至少一种退火处理以形成绝缘结构和衬层。绝缘结构形成在沟槽中，衬层形成在绝缘结构与衬底之间，衬层包括氮，并且衬层的氮浓度非均匀分布。
上面论述了若干实施例的部件，使得本领域普通技术人员可以更好地理解本发明的各个方面。本领域普通技术人员应该理解，可以很容易地使用本发明作为基础来设计或更改其他用于达到与这里所介绍实施例相同的目的和/或实现相同优点的处理和结构。本领域普通技术人员也应该意识到，这种等效构造并不背离本发明的精神和范围，并且在不背离本发明的精神和范围的情况下，可以进行多种变化、替换以及改变。

Claims (10)

1.一种半导体器件的沟槽结构，包括：
衬底，所述衬底中具有沟槽；
隔离结构，设置在所述沟槽中；以及
衬层，设置在所述衬底与所述隔离结构之间，其中，所述衬层包括氮，并且所述衬层在空间上具有不同的氮浓度。
2.根据权利要求1所述的沟槽结构，其中，所述沟槽具有底面和至少一个侧壁，并且所述衬层覆盖所述底面和所述侧壁。
3.根据权利要求2所述的沟槽结构，其中，所述沟槽还具有顶部和底部，所述底部比所述顶部更靠近所述底面，并且所述衬层在所述顶部处的氮浓度高于所述衬层在所述底部处的氮浓度。
4.根据权利要求3所述的沟槽结构，其中，所述沟槽还具有设置在所述顶部和所述底部之间的中间部分，并且所述衬层在所述顶部处的氮浓度高于所述衬层在所述中间部分处的氮浓度。
5.根据权利要求3所述的沟槽结构，其中，所述沟槽还具有设置在所述顶部和所述底部之间的中间部分，并且所述衬层在所述底部处的氮浓度高于所述衬层在所述中间部分处的氮浓度。
6.一种用于形成半导体器件的沟槽结构的方法，包括：
在衬底的沟槽中形成可流动介电层；
固化所述可流动介电层；以及
对所述固化的可流动介电层进行退火以形成绝缘结构和衬层，其中，所述绝缘结构形成在所述沟槽中，所述衬层形成在所述绝缘结构与所述衬底之间，所述衬层包括氮，并且所述衬层在空间上具有不同的氮浓度。
7.根据权利要求6所述的方法，其中，所述衬层由氮氧化硅制成。
8.根据权利要求6所述的方法，还包括：
在所述衬底中形成多个半导体鳍部，其中，所述沟槽形成在所述多个半导体鳍部中的邻近的两个半导体鳍部之间。
9.一种用于形成半导体器件的沟槽结构的方法，包括：
蚀刻衬底以形成沟槽；
利用可流动介电层填充所述沟槽；
对所述可流动介电层执行氧化处理；以及
对所述氧化的可流动介电层执行至少一种退火处理以形成绝缘结构和衬层，其中，所述绝缘结构形成在所述沟槽中，所述衬层形成在所述绝缘结构与所述衬底之间，所述衬层包括氮，并且所述衬层的氮浓度非均匀分布。
10.根据权利要求9所述的方法，其中，在形成所述沟槽期间形成多个半导体鳍部，并且所述沟槽设置在所述多个半导体鳍部中的两个半导体鳍部之间，所述方法还包括：
在所述多个半导体鳍部中的至少一个上形成掩模层，并且所述掩模层包括氮。
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