TWI573198B - 在三度空間集積製程中轉移材料層之方法及其相關結構與元件 - Google Patents

在三度空間集積製程中轉移材料層之方法及其相關結構與元件 Download PDF

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Publication number
TWI573198B
TWI573198B TW101127515A TW101127515A TWI573198B TW I573198 B TWI573198 B TW I573198B TW 101127515 A TW101127515 A TW 101127515A TW 101127515 A TW101127515 A TW 101127515A TW I573198 B TWI573198 B TW I573198B
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TW
Taiwan
Prior art keywords
donor structure
ions
donor
regions
implanting
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TW101127515A
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English (en)
Chinese (zh)
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TW201330117A (zh
Inventor
瑪麗姆 沙達卡
約努 茨拉杜
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索泰克公司
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Priority claimed from US13/246,580 external-priority patent/US8673733B2/en
Priority claimed from FR1159358A external-priority patent/FR2981501B1/fr
Application filed by 索泰克公司 filed Critical 索泰克公司
Publication of TW201330117A publication Critical patent/TW201330117A/zh
Application granted granted Critical
Publication of TWI573198B publication Critical patent/TWI573198B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
TW101127515A 2011-09-27 2012-07-30 在三度空間集積製程中轉移材料層之方法及其相關結構與元件 TWI573198B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/246,580 US8673733B2 (en) 2011-09-27 2011-09-27 Methods of transferring layers of material in 3D integration processes and related structures and devices
FR1159358A FR2981501B1 (fr) 2011-10-17 2011-10-17 Procédé de transfert de couches matériau dans des processus d’intégration 3d et structures et dispositifs associes

Publications (2)

Publication Number Publication Date
TW201330117A TW201330117A (zh) 2013-07-16
TWI573198B true TWI573198B (zh) 2017-03-01

Family

ID=46889374

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101127515A TWI573198B (zh) 2011-09-27 2012-07-30 在三度空間集積製程中轉移材料層之方法及其相關結構與元件

Country Status (6)

Country Link
JP (1) JP6141853B2 (de)
KR (1) KR101955375B1 (de)
CN (1) CN103828036B (de)
DE (1) DE112012004024T5 (de)
TW (1) TWI573198B (de)
WO (1) WO2013045985A1 (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8984463B2 (en) 2012-11-28 2015-03-17 Qualcomm Incorporated Data transfer across power domains
US9064077B2 (en) 2012-11-28 2015-06-23 Qualcomm Incorporated 3D floorplanning using 2D and 3D blocks
US20140225218A1 (en) * 2013-02-12 2014-08-14 Qualcomm Incorporated Ion reduced, ion cut-formed three-dimensional (3d) integrated circuits (ic) (3dics), and related methods and systems
US9536840B2 (en) 2013-02-12 2017-01-03 Qualcomm Incorporated Three-dimensional (3-D) integrated circuits (3DICS) with graphene shield, and related components and methods
US9041448B2 (en) 2013-03-05 2015-05-26 Qualcomm Incorporated Flip-flops in a monolithic three-dimensional (3D) integrated circuit (IC) (3DIC) and related methods
US9177890B2 (en) 2013-03-07 2015-11-03 Qualcomm Incorporated Monolithic three dimensional integration of semiconductor integrated circuits
US9171608B2 (en) 2013-03-15 2015-10-27 Qualcomm Incorporated Three-dimensional (3D) memory cell separation among 3D integrated circuit (IC) tiers, and related 3D integrated circuits (3DICS), 3DIC processor cores, and methods
FR3034569B1 (fr) * 2015-04-02 2021-10-22 Soitec Silicon On Insulator Electrolyte solide avance et sa methode de fabrication
FR3041364B1 (fr) * 2015-09-18 2017-10-06 Soitec Silicon On Insulator Procede de transfert de paves monocristallins
FR3073083B1 (fr) * 2017-10-31 2019-10-11 Soitec Procede de fabrication d'un film sur un feuillet flexible
FR3079659B1 (fr) * 2018-03-29 2020-03-13 Soitec Procede de fabrication d'un substrat donneur pour la realisation d'une structure integree en trois dimensions et procede de fabrication d'une telle structure integree

Citations (5)

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Publication number Priority date Publication date Assignee Title
US6020252A (en) * 1996-05-15 2000-02-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US20050221583A1 (en) * 2001-10-11 2005-10-06 Bernard Aspar Method for making thin layers containing microcomponents
WO2006039684A1 (en) * 2004-10-01 2006-04-13 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes
US20070037363A1 (en) * 2002-11-07 2007-02-15 Bernard Aspar Method for forming a brittle zone in a substrate by co-implantation
US20080286941A1 (en) * 1998-06-22 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device

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FR2681472B1 (fr) 1991-09-18 1993-10-29 Commissariat Energie Atomique Procede de fabrication de films minces de materiau semiconducteur.
FR2747506B1 (fr) * 1996-04-11 1998-05-15 Commissariat Energie Atomique Procede d'obtention d'un film mince de materiau semiconducteur comprenant notamment des composants electroniques
JPH10135147A (ja) * 1996-11-01 1998-05-22 Nippon Telegr & Teleph Corp <Ntt> 結晶薄膜の製造方法及び太陽電池の製造方法
FR2755537B1 (fr) 1996-11-05 1999-03-05 Commissariat Energie Atomique Procede de fabrication d'un film mince sur un support et structure ainsi obtenue
FR2758907B1 (fr) * 1997-01-27 1999-05-07 Commissariat Energie Atomique Procede d'obtention d'un film mince, notamment semiconducteur, comportant une zone protegee des ions, et impliquant une etape d'implantation ionique
FR2767416B1 (fr) 1997-08-12 1999-10-01 Commissariat Energie Atomique Procede de fabrication d'un film mince de materiau solide
JPH1174208A (ja) * 1997-08-27 1999-03-16 Denso Corp 半導体基板の製造方法
FR2773261B1 (fr) 1997-12-30 2000-01-28 Commissariat Energie Atomique Procede pour le transfert d'un film mince comportant une etape de creation d'inclusions
FR2774510B1 (fr) 1998-02-02 2001-10-26 Soitec Silicon On Insulator Procede de traitement de substrats, notamment semi-conducteurs
FR2795865B1 (fr) 1999-06-30 2001-08-17 Commissariat Energie Atomique Procede de realisation d'un film mince utilisant une mise sous pression
FR2818010B1 (fr) 2000-12-08 2003-09-05 Commissariat Energie Atomique Procede de realisation d'une couche mince impliquant l'introduction d'especes gazeuses
JP4814498B2 (ja) * 2004-06-18 2011-11-16 シャープ株式会社 半導体基板の製造方法
EP1911085B1 (de) * 2005-07-08 2011-10-12 S.O.I.Tec Silicon on Insulator Technologies Verfahren zur herstellung eines films
FR2935537B1 (fr) 2008-08-28 2010-10-22 Soitec Silicon On Insulator Procede d'initiation d'adhesion moleculaire
US7816225B2 (en) * 2008-10-30 2010-10-19 Corning Incorporated Methods and apparatus for producing semiconductor on insulator structures using directed exfoliation

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020252A (en) * 1996-05-15 2000-02-01 Commissariat A L'energie Atomique Method of producing a thin layer of semiconductor material
US20080286941A1 (en) * 1998-06-22 2008-11-20 Semiconductor Energy Laboratory Co., Ltd. Method of manufacturing a semiconductor device
US20050221583A1 (en) * 2001-10-11 2005-10-06 Bernard Aspar Method for making thin layers containing microcomponents
US20070037363A1 (en) * 2002-11-07 2007-02-15 Bernard Aspar Method for forming a brittle zone in a substrate by co-implantation
WO2006039684A1 (en) * 2004-10-01 2006-04-13 Massachusetts Institute Of Technology Strained gettering layers for semiconductor processes

Also Published As

Publication number Publication date
CN103828036A (zh) 2014-05-28
DE112012004024T5 (de) 2014-07-24
KR101955375B1 (ko) 2019-03-07
JP2014531768A (ja) 2014-11-27
CN103828036B (zh) 2017-02-15
JP6141853B2 (ja) 2017-06-07
TW201330117A (zh) 2013-07-16
WO2013045985A1 (en) 2013-04-04
KR20140065435A (ko) 2014-05-29

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