TWI565000B - 在相同晶粒上形成Ｇｅ／ＳｉＧｅ通道及ＩＩＩ－Ｖ族通道電晶體的技術 - Google Patents

在相同晶粒上形成Ｇｅ／ＳｉＧｅ通道及ＩＩＩ－Ｖ族通道電晶體的技術 Download PDF

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TWI565000B
TWI565000B TW104115776A TW104115776A TWI565000B TW I565000 B TWI565000 B TW I565000B TW 104115776 A TW104115776 A TW 104115776A TW 104115776 A TW104115776 A TW 104115776A TW I565000 B TWI565000 B TW I565000B
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integrated circuit
substrate
fins
transistor
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TW104115776A
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TW201611190A (zh
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葛蘭 葛雷斯
安拿 莫希
卡希克 強普納森
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英特爾股份有限公司
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    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
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Description

在相同晶粒上形成Ge/SiGe通道及III-V族通道電晶體的技術
本發明係有關於在相同晶粒上形成Ge/SiGe通道及III-V族通道電晶體的技術。
提升基板上之包括形成在半導體基板之電晶體、二極體、電阻、電容及其它被動和主動電子裝置之電路裝置的特性和產量係典型地在設計、製造和操作那些裝置期間主要考慮因素。例如，在設計和製造或形成金屬-氧化物-半導體(MOS)電晶體半導體裝置期間，例如那些使用在互補式金屬氧化物半導體(CMOS)裝置中，其通常需要增加在n型MOS裝置(n-MOS)通道中電子(載子)的移動以及增加在p型MOS裝置(p-MOS)通道中帶正電之電洞(載子)的移動。
200‧‧‧基板
210‧‧‧偽基板
212、212’、222‧‧‧鰭片
220‧‧‧其它的Ge/SiGe或III-V族材料
230‧‧‧淺溝槽絕緣
240、258‧‧‧硬遮罩
250‧‧‧溝槽
252‧‧‧閘極
254‧‧‧閘極電極
256‧‧‧間隔物
260‧‧‧接觸
312、322‧‧‧通道區
412、422‧‧‧奈米線
1000‧‧‧運算裝置
1002‧‧‧母板
1004‧‧‧處理器
1006‧‧‧通訊晶片
第1圖根據本發明一個或多個實施例示出一種形成積體電路的方法。
第2A-2H圖根據各種實施例示出當施行第1圖的方法時形成的範例結構。
第3A圖根據一實施例示出一種包括兩個具有鰭片配置之電晶體的積體電路，第一電晶體包含Ge/SiGe或III-V族材料且第二電晶體包含另一種Ge/SiGe或III-V族材料。
第3B圖根據一實施例示出一種包括兩個具有鰭片配置之電晶體的積體電路，第一電晶體包含Ge/SiGe或III-V族材料且第二電晶體包括包含Ge/SiGe或III-V族材料的源極/汲極區及包含另一種Ge/SiGe或III-V族材料的通道區。
第4A圖根據一實施例示出一種相似於第3A圖所示出的積體電路，除了該電晶體具有奈米線配置。
第4B圖根據一實施例示出一種相似於第3B圖所示出的積體電路，除了該電晶體具有奈米線配置。
第5A-5B圖根據一些實施例示出相似於一些分別在第3A-3B圖所示出的積體電路，除了該電晶體的一者具有鰭片的配置且另一者具有奈米線配置。
第6圖根據一範例實施例示出一種使用本文所揭露技術所形成之積體電路結構或裝置實現的運算系統。
【發明內容及實施方式】
用於在相同晶粒形成Ge/SiGe通道及III-V族通道電晶體之技術被揭露。該技術包括在矽或絕緣體基板上沉積Ge/SiGe或III-V族材料之偽基板(pseudo-substrate)。偽基板可接著被圖形化成鰭片且該鰭片的子集(subset)可由其它的Ge/SiGe或III-V族材料取代。Ge/SiGe鰭片可被使用於p-MOS而III-V族材料可被使用於n-MOS，以及兩組鰭片可被使用於CMOS裝置。在某些情況下，僅有通道區之鰭片子集在例如取代閘極製程期間被取代。在某些情況下，一些或全部的鰭片可被形成為或取代為一個或多個奈米線或奈米帶(nanoribbons)。參考本發明後眾多的配置和變化將顯而易見。
總體概述
在一些應用中期望形成具有鍺(Ge)或矽化鍺(SiGe)通道的電晶體(例如，用於p-MOS裝置)及具有III-V族材料通道之電晶體(例如，用於n-MOS裝置)。例如CMOS裝置之包括Ge/SiGe通道及III-V族通道電晶體裝置兩者之結構和裝置的形成包含可以影響例如性能和產量之非平凡(non-trivial)挑戰。儘管矽(Si)是一種相對常見的、廉價且充足晶元材料，它不可能充分地支持Ge/SiGe通道及III-V族通道電晶體裝置直接地建立在其上。例如，電性載子移動率(electrical carrier mobility)、介面陷阱密度(interface trap density)及用 於使摻雜劑遷移/分離成錯位之電位降低的問題(並可能因此導致總額短路)可能被產生，因為當直接沉積Ge/SiGe及III-V族材料在矽基板上時引起顯著的缺陷密度。
因此，根據本發明一個或多個實施例，用於在相同晶粒上形成Ge/SiGe通道及III-V族通道電晶體之技術被揭露。在一些實施例中，該技術包括在矽基板上之Ge/SiGe或III-V族偽基板的初始毯式沈積(blanket deposition)，接著形成其它的Ge/SiGe或III-V族材料在偽基板中。例如，如果Ge或SiGe被毯式沉積在矽基板上(例如，用以形成p-MOS)，接著Ge/SiGe偽基板可被使用作為用於沉積III-V族材料之基板(例如，用以形成n-MOS)。在另一範例中，如果III-V族材料被毯式沉積在矽基板上(例如，用以形成n-MOS)，III-V族層可接著被使用作為用於沉積Ge/SiGe材料的偽基板(例如，用以形成p-MOS)。藉由以毯式形式在矽基板上執行初始沉積Ge/SiGe或III-V族材料，可以達到更高品質的沉積(例如當與該材料非毯式沉積比較，諸如僅製造該材料之鰭片結構或通道區在矽基板上)。相比於在例如圖案化的矽晶元上執行相同製程，毯式沉積在偽基板上執行蝕刻及熱處理時也提供更佳的撓性。此外，相比於在矽上沉積Ge/SiGe或III-V族材料，其可以是有利於沉積Ge/SiGe在III-V族材料上及沉積III-V族材料在Ge/SiGe上。
在其它實施例中，Ge/SiGe或III-V族材料之 初始毯式沉積可在絕緣體基板上而不是矽基板上被執行，用以形成例如絕緣層上鍺(Ge-on-insulator，GOI)、絕緣層上矽化鍺(SiGe-on-insulator，SGOI)或絕緣層上III-V族材料(例如，GaAsOI)的結構。在此種實施例中，其它的Ge/SiGe或III-V族材料可接著被沉積在所形成的結構上用以例如整合p-MOS及n-MOS裝置在相同晶粒上。當參考本發明而顯而易見的是，本文所揭露之技術可被使用以形成平面的、鰭片的和/或奈米線電晶體配置。在一些實施例中，不同電晶體配置的組合可使用本文所述之技術被使用在相同晶粒或相同積體電路上。例如，在一實施例中，CMOS裝置可被形成包括Ge/SiGe通道p-MOS裝置及III-V族通道n-MOS裝置，其中p-MOS或n-MOS中的一者可具有鰭片配置而另一者具有奈米線配置，其將在本文更詳細地討論。如本文所使用之毯式沉積包括材料(例如，偽基板材料)的沉積或成長，其中該沉積/成長的材料覆蓋其中多個電晶體將使用本文所述之技術形成在基板區域的實質部分。在一些情形下，毯式沉積可覆蓋整個晶元或晶粒或其它合適尺寸的基板，而在其他情形下，毯式沉積可僅覆蓋其中將形成電晶體之晶元/晶粒/基板的區域。
在一些實施例中，Ge/SiGe材料(無論毯式沉積在矽或絕緣體基板上或毯式沉積在III-V族偽基板上)可包含Ge和/或Si1-xGex(例如，其中x>0.8或0.4>x>0.2)。在一些實施例中，III-V族層(無論毯式沉積在矽 或絕緣體基板上，或沉積在Ge/SiGe偽基板上)可包含單一III-V族材料或III-V族材料堆疊。例如，在一實施例中，III-V族層包含砷化鎵(GaAs)或磷化銦(InP)的單一層或例如InP/InGaAs/InAs之III-V族材料的多層堆疊。許多其它Ge/SiGe及III-V族材料配置參考本發明後將顯而易見。如各種本文所討論，Ge/SiGe及III-V族材料可應變和/或包括根據終端使用或目標應用而摻雜。在一些實施例中，III-V族材料(無論單一層或多層堆疊)例如可包括p型摻雜在底部附近及n型摻雜在頂部附近，用以建立內建二極體，其停止或阻礙洩漏電流流至III-V族材料沉積於其上的基板層。
在一些實施例中，在Ge/SiGe或III-V族偽基板形成之後(例如，經由毯式沉積在矽或絕緣層上)，鰭片被形成在基板內以及淺溝槽絕緣(shallow trench isolation)被執行。希望被取代之鰭片子集可接著被蝕刻掉且藉由沉積其它Ge/SiGe或III-V族材料而被取代。在一些實施例中，該取代可在子集中被執行於每一鰭片之實質部分或整體。然而，在其它實施例中，僅有子集的通道區域可在例如取代金屬閘極(replacement metal gate，RMG)製程期間被取代。在一些這種實施例中，鰭片子集的源極和汲極區(其有通道區域取代)可被維持如原本Ge/SiGe或III-V族基板材料。
經分析(例如，使用掃描式/穿透式電子顯微鏡(SEM/TEM)和/或組合物的映射)，根據一個或多個 實施例之結構或裝置配置將有效地顯示包括含有Ge/SiGe通道裝置(例如，p-MOS裝置)及III-V族通道裝置(例如，n-MOS裝置)之矽或絕緣體基板的晶粒，其中材料中的一者被沉積在其它之上(例如，Ge/SiGe沉積在III-V族材料偽基板上或III-V族材料沉積在Ge/SiGe偽基板上)。在一些情形下，該裝置可為包含Ge/SiGe通道裝置(例如，p-MOS裝置)及III-V族通道裝置(例如，n-MOS裝置)之CMOS裝置。在一些實施例中，特性優勢可從Ge/SiGe或III-V族偽基板在矽或絕緣體基板上的毯式沉積實現，例如當相比於選擇性地沉積Ge/SiGe或III-V族材料(例如，用以僅形成此種材料之鰭片)。特性優勢也可從在III-V族偽基板上沉積Ge/SiGe或在Ge/SiGe偽基板上沉積III-V族材料實現(例如，當取代偽基板鰭片之子集時)，當相比於沉積Ge/SiGe或III-V族材料在矽基板上。此種特性優勢可包括改善電性載子移動率、改善介面陷阱密度以及用於使摻雜劑遷移/分離成錯位之電位減少或去除(並可能因此導致總額短路)。參考本發明後眾多的配置和變化將顯而易見。
架構和方法
第1圖根據本發明一個或多個實施例示出一種形成積體電路的方法100。第2A-2H圖根據各種實施例示出當施行第1圖的方法100時形成的範例結構。儘管第2A-2H圖之結構主要是敘述本發明上下文之形成鰭片的電 晶體配置(例如，三閘極(tri-gate)或鰭片場效電晶體(finFET))，但本發明不如此限制。例如該技術可被使用以形成平面、雙閘極、鰭片和/或奈米線(或環繞閘極(gate-all-around)或奈米帶)電晶體配置或其它任何合適的配置，當參考本發明後將顯而易見。第3A-B、4A-B及5A-B圖示出了根據本發明一些實施例之包括使用本發明所述之技術形成的各種電晶體配置的積體電路。
從第1圖可以看出，根據一實施例，方法100包括在矽或絕緣體基板上執行102 Ge/SiGe或III-V族偽基板210之毯式沉積以形成第2A圖所示之結果範例結構。基板200可包括矽大塊基板、絕緣層上矽(Si on insulator，SOI)結構或一些其中頂層為矽且可被作為其上可沉積偽基板210之其它適合的多層結構。基板200也可以為絕緣層，諸如氧化物材料或介電材料或其它電性絕緣材料，在其上形成偽基板210。在其中基板200為絕緣層的實施例中，在絕緣層200上之偽基板210的沉積可形成例如絕緣層上鍺(Ge-on-insulator，GOI)、絕緣層上矽化鍺(SiGe-on-insulator，SGOI)或絕緣層上III-V族材料(例如，GaAsOI)的結構。毯式沉積102可包括化學氣相沉積(chemical vapor deposition，CVD)、原子層沉積(atomic layer deposition，ALD)、液相磊晶(liquid phase epitaxy，LPE)、物理氣相沉積(physical vapor deposition，PVD)、分子束磊晶(molecular beam epitaxy，MBE)或任何其它允許偽基板210形成在基板 200上之適合的製程。在一些情形下，化學和/或熱處理可於異位(ex-situ)或原位(in-situ)被執行以準備用於偽基板210之毯式磊晶沉積102的基板200表面。毯式沉積102可包括偽基板210材料之恆定沉積，或其可包括漸變或多層沉積(例如，用以減少偽基板210之線差排密度(threading dislocation density))。毯式沉積102可包括週期性或沉積後退火以及可包括沉積後研磨以回復偽基板210的表面光滑度。
偽基板210可包含如前所述之Ge/SiGe或至少一III-V族材料。在一些其中偽基板210包含Ge/SiGe材料之實施例中，偽基板210可包含Ge和/或Si1-xGex(例如，其中x>0.8或0.4>x>0.2)。例如，在一些實施例中，偽基板210可包含Ge或SiGe單一層或一包括Ge和/或Si1-xGex之漸變或多層堆疊(例如，包括具有不同百分比的Ge之SiGe層的多層堆疊)。在一些其中偽基板210包含III-V族材料之實施例中，偽基板210包含單一III-V族材料或III-V族材料堆疊。例如，在一些實施例中，偽基板210可包含砷化鎵(GaAs)、磷化銦(InP)、砷化銦(InAs)、砷化銦鎵(InGaAs)、砷化鋁(AlAs)或砷化銦鋁(InAlAs)或任何其它合適的III-V族材料的單一層。在其它實施例中，偽基板210可包含III-V族材料的多層堆疊，例如InP/InGaAs/InAs、GaAs/InP/InAs、GaAs/InGaAs/InAs、GaAs/InAlAs/InAs、InP/InGaAs/InP、GaAs/InAs、GaAs/InGaAs或InP/InGaAs 或任何其它合適的包含兩個或多個III-V材料之多層堆疊。在此種其中偽基板210係III-V族多層堆疊的實施例中，高能隙III-V族材料可被使用於靠近該堆疊的底層(例如，幫忙減少至接地的洩漏電流)，例如GaAs、InP、InAlAs或AlAs。此外，III-V族多層堆疊可以採用低能隙III-V族材料於靠近該堆疊的頂層(例如，用以幫助使接觸到該堆疊)，例如InAs或InGaAs。
如各種本文所討論之Ge/SiGe和III-V族材料可被應變和/或根據終端使用或目標應用而摻雜。部分的偽基板210摻雜也可以發生在方法100中的其它階段，當參考本發明而顯而易見。在一些實施例中，III-V族材料(無論單一層或多層堆疊)可包括例如在靠近底部的p型摻雜以及靠近頂部之n型摻雜，用以建立內建二極體，其停止或阻礙洩漏電流流至基板200。
根據一實施例，方法100繼續圖案化在偽基板210圖案化104中的鰭片212以及執行淺溝槽絕緣(STI)，用以形成顯示於第2B圖之結果範例結構。圖案化或形成104鰭片212可包括任何數量的遮罩或蝕刻製程，和/或其它合適的技術。例如，在一範例實施例中，STI溝槽蝕刻製程被執行以形成鰭片212。在一範例實施例中，STI溝槽蝕刻製程被執行之後，溝槽被填充STI氧化物230且該結構被研磨平整以形成第2B圖所示之結構。需注意在此範例實施例中，鰭片212被形成使得偽基板材料210仍然在STI材料230之下。此外需注意到即使 在範例實施例中僅有四個鰭片，根據終端使用或目標應用，任何數量之任一不同或一致的形狀和尺寸的鰭片212可形成在偽基板210中。
根據一實施例，方法100繼續在旨在被保留/保持的鰭片212上圖案化106硬遮罩240，用以形成第2C圖所示之結果範例結構。圖案化104可包括任何數量之遮罩/蝕刻製程，和/或其它合適的技術。硬遮罩240可包含例如氮化鈦之任何合適的材料。注意在此範例實施例中，可以看出每一其它鰭片212具有硬遮罩240圖案化在上，因為那些鰭片在此範例情形下旨在被保留/保持。然而，圖案化106可根據終端使用或目標應用而被執行使得硬遮罩240在不同組的鰭片上。也需注意到如本文所討論之旨在被取代之鰭片在一些範例實施例中被指出為212’。
根據一實施例，方法100繼續蝕刻108旨在被取代之鰭片212’以建立如第2D圖所示之範例結構之溝槽250。蝕刻108可使用任何適合的蝕刻技術執行，諸如各種乾式和/或濕式蝕刻製程。在一些實施例中，蝕刻108可在原位/沒有空斷(air break)執行，而在其它實施例中，蝕刻108可在異位執行。
根據一實施例，方法100繼續在溝槽250中沉積110其它的Ge/SiGe或III-V族材料220，用以形成第2E圖所示之結果範例結構。置換材料220之沉積110可包括任何本文所述之沉積製程(例如，CVD、ALD、LPE、PVD、MBE)，或任何其它適合的沉積製程。如在 第2E圖可看出，在此實施例中沉積110係選擇性沉積，使得置換材料220僅保留在溝槽250中(且沒有保留在STI材料230或硬遮罩材料240上)。沉積110可包括置換材料220之恆定沉積，或其可包括漸變或多層沉積。在此範例實施例中，取代沉積材料220係取決於偽基板210的材料。例如，如果偽基板210包含Ge/SiGe材料，接著置換材料220包含III-V族材料。在另一範例中，如果偽基板210包含III-V族材料，接著置換材料220包含Ge/SiGe材料。本文所討論之相對用於偽基板210之Ge/SiGe和III-V族材料同樣適用於置換材料220。例如，置換材料220可包含如本文各種敘述之單一Ge/SiGe或III-V族材料或多層堆疊。此外，置換材料220可被應變和/或根據終端使用或目標應用而摻雜。
根據一實施例，方法100繼續去除112硬遮罩240及平坦化/研磨置換材料220，用以形成第2F圖所示之結果範例結構。硬遮罩240可使用任何適合的技術去除，且在一些情形下，當平坦化該結構時硬遮罩240可被去除。研磨製程可例如被執行以回復表面平整；然而，這樣的製程不需要被執行。如第2F圖可看出，置換材料220可被形成進入在每一鰭片222任何一側之具有STI材料230之鰭片222中。因此，該結構具有交替的Ge/SiGe材料和III-V族材料之鰭片，因為無論鰭片212或222是Ge/SiGe材料而另一鰭片212或222則是III-V族材料。
根據一實施例，方法100繼續凹陷114 STI材 料230以允許鰭片212和222滲出至STI平面之上，而形成第2G圖所示之結果範例結構。凹陷114 STI材料230可使用任何合適的技術執行且其可能有例於鰭片及奈米線配置，當參考本發明將顯而易見。然而，在其中平面電晶體配置使用方法100形成的實施例中，凹陷製程114可不必被執行，因此凹陷製程114是可選擇的。在替代實施例中，第2G圖所示之結構可以是其中僅有在閘極之下的偽基板鰭片212之通道區或主動部分被取代之取代閘極部分的內部圖。其中僅有通道區被取代之此種結果結構之範例顯示於第3B、4B及5B圖將在本發明更詳細地討論。例如，顯示於第3B、4B及5B圖之此種結構可以與其中整個偽基板其鰭片被取代之第3A、4A及5A圖比較。需注意到在其中整個鰭片被取代之實施例中，取代可以被執行在任何執行閘極處理之後。還應注意到在其中僅偽基板之主動部分/通道區被取代之實施例中，當偽閘極已被去除以露出偽基板鰭片之通道區時，取代可執行於閘極處理期間。
方法100繼續完成116一個或多個電晶體的形成。根據一實施例，如第2H圖所示，各種不同的製程可以被執行以完成116一個或多個電晶體，且此種製程可包括在鰭片212及222上形成閘極252或閘極堆疊。閘極252的形成可包括偽閘極氧化物沉積、偽閘極電極(例如，多晶矽(poly-Si))沉積及圖案化硬遮罩(hard mask)沉積。額外的處理可包括圖案化偽閘極及沉積/蝕刻間隔 物材料。此種製程之後，該方法可繼續絕緣體沉積、平坦化及接著偽閘極電極和閘極氧化物去除以露出電晶體的通道區，例如為了取代金屬閘極製程被完成。接著打開通道區，偽閘極氧化物及電極可分別被取代為例如高k介電質及取代金屬閘極。源極/汲極接觸溝槽處理迴圈可被執行，其可包括例如源極/汲極接觸或接觸層的沉積。方法100可包括各種合適的額外或替代製程，當參考本發明將顯而易見。
第3A圖根據一實施例示出一種包括兩個具有鰭片配置之電晶體的積體電路，第一電晶體包含Ge/SiGe或III-V族材料且第二電晶體包含另一種Ge/SiGe或III-V族材料。可以看出，積體電路包括基板200、偽基板210、鰭片212和222以及分離鰭片之STI 230，所有的這些已經參照前面的第2A-H圖被敘述。積體電路也包括閘極電極254及閘極介電質(為了便於說明而未顯示)直接形成在閘極電極254下。閘極介電質及閘極電極可使用任何合適的技術及從任何合適的材料而形成。例如，閘極堆疊可如前面敘述在取代閘極製程期間已經被形成，且此種製程可包括任何合適的沉積技術(例如，CVD、PVD等等)。此外，閘極電極可包含例如諸如多晶矽之廣範圍的材料，或諸如鋁(Al)、鎢(W)、鈦(Ti)或銅(Cu)之各種合適的金屬或金屬合金。可以看出，間隔物256及硬遮罩258被形成環繞閘極堆疊。鰭片212和222之源極/汲極可包括在源極/汲極溝槽蝕刻被執行以露出那些區域 之後形成的接觸260。接觸260可使用例如矽化(silicidation)製程形成(一般而言，沉積接觸金屬及後續退火)。
如在第3A圖可看出，鰭片212和222分別的通道區312和322在形狀及材料中匹配它們對應的鰭片。例如，如本發明各種敘述之如果偽基板210包含Ge/SiGe，然後從偽基板210形成的鰭片212也包含Ge/SiGe且鰭片212之通道區312也包含Ge/SiGe。在此種範例中，形成在偽基板210上之鰭片222包含III-V族材料且鰭片222之通道區322也包含III-V族材料。此外，在此種範例中，Ge/SiGe通道區312可以為p型摻雜(例如，用以形成p-MOS電晶體)及III-V族通道區322可以為n型摻雜(例如，用以形成n-MOS電晶體)。在另一範例中，如本發明各種敘述之如果偽基板210包含III-V族，然後從偽基板210形成的鰭片212也包含III-V族材料且鰭片212之通道區312也包含III-V族材料。在此種範例中，形成在偽基板210上之鰭片222包含Ge/SiGe且鰭片222之通道區322也包含Ge/SiGe。此外，在此種範例中，III-V族通道區312可以為n型摻雜(例如，用以形成n-MOS電晶體)及Ge/SiGe通道區322可以為p型摻雜(例如，用以形成p-MOS電晶體)。如本發明各種敘述，摻雜可使用任何合適的技術和摻雜劑執行，例如依據將被摻雜的材料、所期望n型或p型的摻雜結果和/或目標應用。例如，用於Ge/SiGe之p型摻雜劑 包括硼(B)、鋁(Al)、鎵(Ga)和/或銦(In)，僅列舉幾個範例。此外，用於III-V族材料之n型摻雜劑可包括碳(C)、矽(Si)、鍺(Ge)、錫(Sn)、硒(Se)和/或碲(Te)，僅列舉幾個範例。當參考本發明時眾多不同的摻雜方案將顯而易見。
第3B圖根據一實施例示出一種包括兩個具有鰭片配置之電晶體的積體電路，第一電晶體包含Ge/SiGe或III-V族材料且第二電晶體包括包含Ge/SiGe或III-V族材料的源極/汲極區及包含另一種Ge/SiGe或III-V族材料的通道區。在此範例實施例中，偽基板材料210之取代執行於取代金屬閘極製程期間，使得僅有鰭片212’之通道區被取代。這可能藉由維持第2B圖之鰭片212之完整、執行STI 240之凹陷(例如，如參考第2G圖)以及當通道區被露出時接著僅取代偽基板之子集之主動部分或通道區(例如，在取代金屬閘極處理期間)而實現。在此種情形下，僅鰭片212之通道區之子集可被取代以形成第3B圖所示之包括取代通道區322之鰭片212’。此外，在此種範例情形下及前面所敘述中，第2G圖可表示在僅偽基板鰭片之子集之通道區被取代之後閘極電極溝槽內部之露出的通道區。需注意到在第3B圖所示之範例實施例中，電晶體之源極/汲極區包含相同材料(Ge/SiGe或III-V族材料之一者)而通道區包含不同材料(其中一者包含Ge/SiGe或III-V族材料以及另一者包含另一個Ge/SiGe或III-V族材料)。
第4A圖根據一實施例示出一種相似於第3A圖所示出的積體電路，除了該電晶體具有奈米線配置。奈米線電晶體(有時指的是環繞閘極或奈米帶)係配置相似於鰭片基電晶體，但是取代其中閘極在三側上之鰭片通道區(因此，有三個有效閘極)，一個或多個奈米線被使用且閘極材料通常環繞奈米線的所有側。取決於特定設計，一些奈米線電晶體具有例如四個有效閘極。如第4A圖可看出，每個具有奈米線通道架構412和422之電晶體有兩個奈米線，儘管在其它實施例中可具有任何數目的奈米線。例如，奈米線412和422當通道區在偽閘極被去除後之取代金屬閘極製程期間露出時已經形成。在此種範例中，Ge/SiGe和/或III-V族材料鰭片可以為多層結構以幫助促進從鰭片結構轉變為奈米線結構。在一範例情形下，III-V族多層堆疊可被形成，諸如GaAs/InGaAs或InP/InGaAs，其中GaAs或InP層被蝕刻掉以形成InGaAs奈米線。然而，當參考本發明將顯而易見的是眾多不同的材料和技術可用於形成Ge/SiGe或III-V族材料奈米線通道架構。
第4B圖根據一實施例示出一種相似於第3B圖所示出的積體電路，除了該電晶體具有奈米線配置。需注意到的是在此範例實施例中，電晶體之源極/汲極區包含相同材料(Ge/SiGe或III-V族材料之一者)而通道區包含不同材料(其中一者包含Ge/SiGe或III-V族材料以及另一者包含另一個Ge/SiGe或III-V族材料)。
第5A-5B圖根據一些實施例示出相似於一些分別在第3A-3B圖所示出的積體電路，除了該電晶體的一者具有鰭片的配置而另一者具有奈米線配置。在第5A-5B圖中的實施例中示出了不同電晶體配置可被形成在相同積體電路上。在此種範例實施例中，積體電路包括與偽基板材料210包含相同材料之鰭片通道區312以及與偽基板210包含不同材料之奈米線通道區422。這些實施例提供兩種不同的配置；然而，任何數目的配置，包括平面、雙閘極、鰭片和或奈米線電晶體配置皆可被形成。在任何第3A-B、4A-B及5A-B圖所示之實施例中的兩個電晶體可形成CMOS裝置。
範例系統
第6圖根據一範例實施例示出一種使用本文所揭露技術所形成之積體電路結構或裝置實現的運算裝置1000。可以看出，運算裝置1000容置於母板1002。母板1002可包括多個組件，包含但不限制於處理器1004及至少一通訊晶片1006，每一通訊晶片可以物理地及電性地與母板1002耦合，或以其他方式整合在其中。如將理解的，母板1002可以是例如任何的印刷電路板(printed circuit board)，無論是主板、安裝在主板上的子板或運算裝置1000之唯一板等等。
根據其應用，運算系統1000可包括其它有或沒有物理性地及電性地與母板1002耦合的組件。這些其 它組件包括，但不限制於，揮發性記憶體(例如：DRAM)、非揮發性記憶體(即，ROM)、圖形處理器(graphics processor)、數位訊號處理器(digital signal processor)、密碼處理器(crypto processor)、晶片組(chipset)、天線(antenna)、顯示器、觸控螢幕顯示器、觸控螢幕控制器(touchscreen controller)、電池、音頻編解碼器(audio codec)、視頻編解碼器(video codec)、功率放大器(power amplifier)(未示出)、全球定位系統(global positioning system，GPS)裝置、羅盤(campass)、蓋格計數器(Geiger counter)、加速度計(accelerometer)、陀螺儀(gyroscope)、揚聲器(speaker)、相機(camera)以及大容量存儲裝置(mass storage device)(例如：硬碟機(hard disk drive)、光碟(compact disk，CD)、數位影音光碟(digital versatile disk，DVD)等等)。任何包括在運算系統1000中之組件可包括一個或多個使用根據本發明一範例實施例形成之積體電路結構或裝置。在一些實施例中，多種功能可被整合至一個或多個晶片(例如，注意到通訊晶片1006可以是部分的或以其它方式整合到處理器1004中)。
通訊晶片1006實現用於傳送資料到運算系統1000和從運算系統1000傳送資料之無線通訊。用語「無線」及其衍生可用於描述電路、裝置、系統、方法、技術、通訊通道等等，其可以通訊資料通過使用調製電磁波 於非固體介質。該用語不是暗示相關裝置不包含有線，儘管一些實施方式可能沒有包含有線。通訊晶片1006可以實現任何數目的無線標準或協議，包括但不限制於，Wi-Fi(IEEE802.11族)、WiMAX(例如IEEE802.16族)、IEEE 802.20、長期演進技術(LTE)、Ev-DO、HSPA+、HSDPA+、HSUPA+、EDGE、GSM、GPRS、CDMA、TDMA、DECT、藍芽、彼等之衍生物、以及指定為3G、4G、5G等的任何其他無線協定。運算系統1000可包含多個通訊晶片1006。例如，第一通訊晶片1006可專用於距離較短的無線通訊，例如Wi-Fi與藍芽，以及第二通訊晶片1006可專用於距離較長的無線通訊，例如GPS、EDGE、GPRS、CDMA、WiMAX、LTE、Ev-DO及其他。
運算系統1000之處理器1004可包括封裝處理器1004內之積體電路。在一些實施例中，處理器之積體電路晶片包括實施一個或多個使用如所揭露之技術形成的積體電路結構或裝置之板上電路，如本文各種敘述。用語「處理器」可指處理來自暫存器及/或記憶體之電子資料以將該等電子資料轉換成可儲存於暫存器及/或記憶體之其他電子資料的任何裝置或裝置之一部份。
通訊晶片1006也可以包括封裝通訊晶片1006內之積體電路。根據一些此種範例實施例，通訊晶片之積體電路晶片包括一個或多個使用所揭露技術形成的積體電路結構或裝置。如根據本發明可以理解，注意到多標準無線功能可直接整合至處理器1004中(例如，其中任何晶 片1006之功能被整合至處理器1004中，而不是具有分開的通訊晶片)。更需注意到處理器1004可以為具有此種無線能力之晶片組。簡言之，任何數量之處理器1004和/或通訊晶片1006可被使用。同樣地，任一晶片或晶片組可具有多種功能整合在其中。
在各種實施中，運算裝置1000可以為膝上型電腦(laptop computer)、簡易筆記型電腦(netbook computer)、筆記型電腦(notebook computer)、極薄筆記型電腦(ultrabook computer)、智慧型手機(smartphone)、平板電腦(tablet)、個人數位助理(personal digital assistant，PDA)、超級行動個人電腦(ultra mobile PC)、行動電話(mobile phone)、桌上型電腦(desktop computer)、伺服器(server)、印表機(printer)、掃描器(scanner)、螢幕(monitor)、機頂盒(set-top box)、娛樂控制單元(entertainment control unit)、數位相機(digital camera)、隨身音樂撥放器(portable music player)、數位錄影機(digital video recorder)或採用一個或多個使用所揭露技術形成的積體電路結構或裝置，如本文各種敘述。
進一步範例實施例
下面的範例涉及到進一步的實施例，從中數個的排列和配置將是顯而易見的。
範例1係一種積體電路，其包含：矽(Si) 或絕緣體基板；形成在該基板上之偽基板，且其包含以下其中一者：鍺(Ge)和/或矽化鍺(SiGe)；或至少一III-V族材料；包括通道區之第一電晶體，該第一電晶體通道區從該偽基板之一部分形成且包含偽基板材料；以及包括通道區之第二電晶體，該第二電晶體通道區形成在該偽基板上且包含以下其中另一者：鍺和/或矽化鍺；或至少一III-V族材料。
範例2包括申請專利範圍第1項之發明標的(subject matter)，其中該偽基板係毯式沉積在該基板上。
範例3包括任何申請專利範圍第1-2項之發明標的，其中該Ge和/或SiGe通道區係p型摻雜及該III-V族通道區係n型摻雜。
範例4包括任何申請專利範圍第1-3項之發明標的，其中具有Ge和/或SiGe通道區之該電晶體由Si1-xGex所組成，其中x>0.8或0.4>x>0.2。
範例5包括任何申請專利範圍第1-4項之發明標的，其中該第二電晶體包括形成在該基板上之源極/汲極區且包含該第二電晶體通道區材料。
範例6包括任何申請專利範圍第1-4項之發明標的，其中該第二電晶體包括從該偽基板之一部分形成的源極/汲極區且包含該偽基板材料。
範例7包括任何申請專利範圍第1-6項之發明標的，其中該至少一III-V族材料包含至少兩III-V族 材料的堆疊。
範例8包括申請專利範圍第7項之發明標的，其中在該堆疊中之底部材料係砷化鎵(GaAs)、磷化銦(InP)、砷化鋁(AlAs)及砷化銦鋁(InAlAs)中的一者。
範例9包括任何申請專利範圍第7-8項之發明標的，其中在該堆疊中之頂部材料係砷化銦鎵(InGaAs)和砷化銦(InAs)中的一者。
範例10包括任何申請專利範圍第1-9項之發明標的，其中該至少一III-V族材料在靠近底部係p型摻雜及靠近頂部係n型摻雜。
範例11包括任何申請專利範圍第1-10項之發明標的，其中該第一及第二電晶體之至少一者具有鰭片配置。
範例12包括任何申請專利範圍第1-11項之發明標的，其中該第一及第二電晶體之至少一者具有奈米線或奈米帶配置。
範例13係一種互補式金屬氧化物半導體(CMOS)裝置包含任何申請專利範圍第1-12項之發明標的。
範例14係一種運算裝置包含申請專利範圍第1-12項任一項之發明標的。
範例15係一種積體電路，其包含：矽(Si)或絕緣體基板；形成在該基板上之偽基板，且其包含以下 其中一者：鍺(Ge)和/或矽化鍺(SiGe)；或至少一III-V族材料；從該偽基板形成之第一鰭片；以及在該偽基板上形成之第二鰭片，其包含以下其中另一者：鍺和/或矽化鍺；或至少一III-V族材料。
範例16包括任何申請專利範圍第15項之發明標的，更包含：形成在該第一鰭片上之第一電晶體；及形成在第二鰭片上之第二電晶體。
範例17包括任何申請專利範圍第15項之發明標的，更包含：包括從該第一鰭片形成之通道區的第一電晶體；及包括從該第二鰭片形成之通道區的第二電晶體。
範例18包括任何申請專利範圍第16-17項之發明標的，其中該第一電晶體係p-MOS電晶體而該第二電晶體係n-MOS電晶體。
範例19包括任何申請專利範圍第16-18項之發明標的，其中該第一和第二鰭片之一者的至少一部分被形成為一個或多個奈米線或奈米帶。
範例20包括任何申請專利範圍第15-19項之發明標的，其中該偽基板係毯式沉積在該基板上。
範例21包括任何申請專利範圍第15-20項之發明標的，其中包含Ge和/或SiGe之該鰭片由Si1-xGex組成，其中x>0.8或0.4>x>0.2。
範例22包括任何申請專利範圍第15-21項之發明標的，其中該至少一III-V族材料包含至少兩III-V 族材料的堆疊。
範例23包括任何申請專利範圍第22項之發明標的，其中在該堆疊中之底部材料係砷化鎵(GaAs)、磷化銦(InP)、砷化鋁(AlAs)及砷化銦鋁(InAlAs)中的一者。
範例24包括任何申請專利範圍第22-23項之發明標的，其中在該堆疊中之頂部材料係砷化銦鎵(InGaAs)和砷化銦(InAs)中的一者。
範例25包括任何申請專利範圍第15-24項之發明標的，其中該至少一III-V族材料在靠近底部係p型摻雜及靠近頂部係n型摻雜。
範例26係一種形成積體電路的方法，該方法包含：毯式沉積偽基板在矽(Si)或絕緣體基板上，該偽基板包含以下其中一者：鍺(Ge)和/或矽化鍺(SiGe)；或至少一III-V族材料；圖案化該偽基板為複數個鰭片；以及取代該複數個鰭片之子集中之每一鰭片的至少一部分為置換材料，該置換材料包含以下其中另一者：鍺和/或矽化鍺；或至少一III-V族材料。
範例27包括任何申請專利範圍第26項之發明標的，更包含：在由偽基板材料形成之該鰭片上形成第一組的一個或多個電晶體；在被取代之該鰭片的該子集形成第二組的一個或多個電晶體。
範例28包括任何申請專利範圍第26-27項之發明標的，其中圖案化該偽基板為複數個鰭片包含：蝕刻 淺溝槽絕緣(STI)溝槽；填充該STI溝槽為STI氧化物；及執行平坦化和/或研磨製程。
範例29包括任何申請專利範圍第26-28項之發明標的，其中取代該複數個鰭片之該子集之至少一部分包含：在該子集之所有鰭片外側上圖案化硬遮罩；蝕刻該子集；及沉積該置換材料。
範例30包括任何申請專利範圍第29項之發明標的，其中取代該複數個鰭片之該子集更包含：去除該硬遮罩；及執行平坦化和/或研磨製程。
範例31包括任何申請專利範圍第26-30項之發明標的，其中該毯式沉積包含漸變或多層沉積。
範例32包括任何申請專利範圍第26-31項之發明標的，其中只有該複數個鰭片之該子集中之每一鰭片的至少一部分被取代，該部分包含用於隨後形成的電晶體之通道區。
範例33包括任何申請專利範圍第26-32項之發明標的，更包含形成每一鰭片之至少一部分成為一個或多個奈米線。
範例34包括任何申請專利範圍第26-32項之發明標的，更包含取代每一鰭片之至少一部分為一個或多個奈米線。
範例35包括任何申請專利範圍第26-32項之發明標的，更包含：在鰭片之該子集的一者或該子集外側之該鰭片上形成一個或多個鰭片電晶體；及在鰭片之該子 集的另一者或該子集外側之該鰭片形成一個或多個奈米線電晶體。
範例36包括任何申請專利範圍第26-35項之發明標的，更包含：在鰭片之該子集的一者或該子集外側之該鰭片上形成一個或多個p-MOS電晶體；及在鰭片之該子集的另一者或該子集外側之該鰭片形成一個或多個n-MOS電晶體。
範例實施例的前述說明已經針對例示及說明之目的加以呈現。未意圖為窮舉性或限制本揭示於所揭示的精確形式。許多修改及變化按照本揭示為可能的。意圖的是，本揭示的範圍未受限於此詳細說明，但反而由其所附的申請專利範圍所限制。請求對此申請案的優先權之未來提出的申請案可能以不同方式請求所揭示之標的且一般可包括任意組的一或更多限制，如各種揭示或者此處所展示。
200‧‧‧矽或絕緣體基板
210‧‧‧Ge/SiGe或III-V族偽基板
212、222‧‧‧鰭片
230‧‧‧淺溝槽絕緣
250‧‧‧溝槽

Claims (25)

  1. 一種積體電路，包含：矽(Si)或絕緣體基板；形成在該基板上之偽基板，且其包含以下其中一者：鍺(Ge)和/或矽化鍺(SiGe)；或至少一III-V族材料；包括通道區之第一電晶體，該第一電晶體通道區從該偽基板之一部分形成且包含偽基板材料；以及包括通道區之第二電晶體，該第二電晶體通道區形成在該偽基板上且包含以下其中另一者：鍺和/或矽化鍺；或至少一III-V族材料。
  2. 如申請專利範圍第1項所述之積體電路，其中該偽基板係毯式沉積在該基板上。
  3. 如申請專利範圍第1項所述之積體電路，其中該Ge和/或SiGe通道區係p型摻雜及該III-V族通道區係n型摻雜。
  4. 如申請專利範圍第1項所述之積體電路，其中具有Ge和/或SiGe通道區之該電晶體由Si1-xGex所組成，其中x>0.8或0.4>x>0.2。
  5. 如申請專利範圍第1項所述之積體電路，其中該第二電晶體包括形成在該基板上之源極/汲極區且包含該第二電晶體通道區材料。
  6. 如申請專利範圍第1項所述之積體電路，其中該 第二電晶體包括從該偽基板之一部分形成的源極/汲極區且包含該偽基板材料。
  7. 如申請專利範圍第1項所述之積體電路，其中該至少一III-V族材料包含至少兩III-V族材料的堆疊。
  8. 如申請專利範圍第7項所述之積體電路，其中在該堆疊中之底部材料係砷化鎵(GaAs)、磷化銦(InP)、砷化鋁(AlAs)及砷化銦鋁(InAlAs)中的一者。
  9. 如申請專利範圍第7項所述之積體電路，其中在該堆疊中之頂部材料係砷化銦鎵(InGaAs)和砷化銦(InAs)中的一者。
  10. 如申請專利範圍第1項所述之積體電路，其中該至少一III-V族材料在靠近底部係p型摻雜及靠近頂部係n型摻雜。
  11. 如申請專利範圍第1項所述之積體電路，其中該第一及第二電晶體之至少一者具有鰭片配置。
  12. 如申請專利範圍第1項所述之積體電路，其中該第一及第二電晶體之至少一者具有奈米線或奈米帶配置。
  13. 一種互補式金屬氧化物半導體(CMOS)裝置包含申請專利範圍第1項至第12項中任一項之該積體電路。
  14. 一種運算系統包含申請專利範圍第1項至第12項中任一項之該積體電路。
  15. 一種積體電路，包含： 矽(Si)或絕緣體基板；形成在該基板上之偽基板，且其包含以下其中一者：鍺(Ge)和/或矽化鍺(SiGe)；或至少一III-V族材料；從該偽基板形成之第一鰭片；以及在該偽基板上形成之第二鰭片，其包含以下其中另一者：鍺和/或矽化鍺；或至少一III-V族材料。
  16. 如申請專利範圍第15項所述之積體電路，更包含：形成在該第一鰭片上之第一電晶體；及形成在第二鰭片上之第二電晶體。
  17. 如申請專利範圍第15項所述之積體電路，更包含：包括從該第一鰭片形成之通道區的第一電晶體；及包括從該第二鰭片形成之通道區的第二電晶體。
  18. 如申請專利範圍第16-17項中任一項所述之積體電路，其中該第一電晶體係p-MOS電晶體而該第二電晶體係n-MOS電晶體。
  19. 如申請專利範圍第16-17項中任一項所述之積體電路，其中該第一和第二鰭片之一者的至少一部分被形成為一個或多個奈米線或奈米帶。
  20. 一種形成積體電路的方法，該方法包含： 毯式沉積偽基板在矽(Si)或絕緣體基板上，該偽基板包含以下其中一者：鍺(Ge)和/或矽化鍺(SiGe)；或至少一III-V族材料；圖案化該偽基板為複數個鰭片；以及取代該複數個鰭片之子集中之每一鰭片的至少一部分為置換材料，該置換材料包含以下其中另一者：鍺和/或矽化鍺；或至少一III-V族材料。
  21. 如申請專利範圍第20項所述之方法，更包含：在由偽基板材料形成之該些鰭片上形成第一組的一個或多個電晶體；在被取代之該些鰭片的該子集上形成第二組的一個或多個電晶體。
  22. 如申請專利範圍第20項所述之方法，其中只有該複數個鰭片之該子集中之每一鰭片的一部分被取代，該些部分由用於隨後形成的電晶體之通道區所組成。
  23. 如申請專利範圍第20-22項中任一項所述之方法，更包含形成每一鰭片之至少一部分成為一個或多個奈米線。
  24. 如申請專利範圍第20-22項中任一項所述之方法，更包含取代每一鰭片之至少一部分為一個或多個奈米線。
  25. 如申請專利範圍第20-22項中任一項所述之方 法，更包含：在該些鰭片之該子集的一者上或該子集外側之該鰭片上形成一個或多個鰭片電晶體；及在該些鰭片之該子集的另一者上或該子集外側之該鰭片上形成一個或多個奈米線電晶體。
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