TWI544590B - 半導體裝置封裝體及其製造方法 - Google Patents

半導體裝置封裝體及其製造方法 Download PDF

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Publication number
TWI544590B
TWI544590B TW100144032A TW100144032A TWI544590B TW I544590 B TWI544590 B TW I544590B TW 100144032 A TW100144032 A TW 100144032A TW 100144032 A TW100144032 A TW 100144032A TW I544590 B TWI544590 B TW I544590B
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Taiwan
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semiconductor device
passivation layer
dielectric
device package
layer
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TW100144032A
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English (en)
Chinese (zh)
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TW201246475A (en
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理查 亞佛瑞德 畢普瑞
保羅 艾倫 麥克考奈利
艾朗 維盧派克夏 格達
湯瑪斯 伯特 格茲卡
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奇異電器公司
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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    • H01L23/00—Details of semiconductor or other solid state devices
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    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3157—Partial encapsulation or coating
    • H01L23/3171—Partial encapsulation or coating the coating being directly applied to the semiconductor body, e.g. passivation layer
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
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    • H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Light Receiving Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
TW100144032A 2010-12-08 2011-11-30 半導體裝置封裝體及其製造方法 TWI544590B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/962,761 US8310040B2 (en) 2010-12-08 2010-12-08 Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof

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Publication Number Publication Date
TW201246475A TW201246475A (en) 2012-11-16
TWI544590B true TWI544590B (zh) 2016-08-01

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US (2) US8310040B2 (enExample)
EP (1) EP2463901B1 (enExample)
JP (1) JP5926547B2 (enExample)
KR (1) KR101944477B1 (enExample)
CN (1) CN102543946B (enExample)
PH (1) PH12011000403A1 (enExample)
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CN115939222B (zh) * 2022-11-24 2025-10-17 湖南三安半导体有限责任公司 半导体器件及其制备方法
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US8310040B2 (en) 2012-11-13
PH12011000403A1 (en) 2014-07-23
KR20120089993A (ko) 2012-08-16
EP2463901B1 (en) 2018-06-13
SG182076A1 (en) 2012-07-30
EP2463901A2 (en) 2012-06-13
JP5926547B2 (ja) 2016-05-25
KR101944477B1 (ko) 2019-01-31
JP2012124486A (ja) 2012-06-28
EP2463901A3 (en) 2012-08-29
CN102543946B (zh) 2016-12-07
TW201246475A (en) 2012-11-16
CN102543946A (zh) 2012-07-04
US20120146234A1 (en) 2012-06-14
US8586421B2 (en) 2013-11-19
US20120329207A1 (en) 2012-12-27

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