TWI544590B - 半導體裝置封裝體及其製造方法 - Google Patents

半導體裝置封裝體及其製造方法 Download PDF

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Publication number
TWI544590B
TWI544590B TW100144032A TW100144032A TWI544590B TW I544590 B TWI544590 B TW I544590B TW 100144032 A TW100144032 A TW 100144032A TW 100144032 A TW100144032 A TW 100144032A TW I544590 B TWI544590 B TW I544590B
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TW
Taiwan
Prior art keywords
semiconductor device
passivation layer
dielectric
device package
layer
Prior art date
Application number
TW100144032A
Other languages
English (en)
Chinese (zh)
Other versions
TW201246475A (en
Inventor
理查 亞佛瑞德 畢普瑞
保羅 艾倫 麥克考奈利
艾朗 維盧派克夏 格達
湯瑪斯 伯特 格茲卡
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奇異電器公司
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Publication date
Application filed by 奇異電器公司 filed Critical 奇異電器公司
Publication of TW201246475A publication Critical patent/TW201246475A/zh
Application granted granted Critical
Publication of TWI544590B publication Critical patent/TWI544590B/zh

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Classifications

    • H10W74/137
    • H10W72/00
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117Shapes of semiconductor bodies
    • H10W70/09
    • H10W70/60
    • H10W74/00
    • H10W74/01
    • H10W74/144
    • H10W74/147
    • H10W70/093
    • H10W72/07131
    • H10W72/073
    • H10W90/00

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Light Receiving Elements (AREA)
TW100144032A 2010-12-08 2011-11-30 半導體裝置封裝體及其製造方法 TWI544590B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/962,761 US8310040B2 (en) 2010-12-08 2010-12-08 Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof

Publications (2)

Publication Number Publication Date
TW201246475A TW201246475A (en) 2012-11-16
TWI544590B true TWI544590B (zh) 2016-08-01

Family

ID=45002829

Family Applications (1)

Application Number Title Priority Date Filing Date
TW100144032A TWI544590B (zh) 2010-12-08 2011-11-30 半導體裝置封裝體及其製造方法

Country Status (8)

Country Link
US (2) US8310040B2 (enExample)
EP (1) EP2463901B1 (enExample)
JP (1) JP5926547B2 (enExample)
KR (1) KR101944477B1 (enExample)
CN (1) CN102543946B (enExample)
PH (1) PH12011000403A1 (enExample)
SG (1) SG182076A1 (enExample)
TW (1) TWI544590B (enExample)

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* Cited by examiner, † Cited by third party
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US8431438B2 (en) 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US9209151B2 (en) 2013-09-26 2015-12-08 General Electric Company Embedded semiconductor device package and method of manufacturing thereof
US9806051B2 (en) 2014-03-04 2017-10-31 General Electric Company Ultra-thin embedded semiconductor device package and method of manufacturing thereof
KR101978027B1 (ko) * 2014-05-15 2019-05-13 인텔 코포레이션 집적 회로 조립체용 성형 복합 인클로저
JP6573876B2 (ja) * 2014-05-29 2019-09-11 アーゼッド・エレクトロニック・マテリアルズ(ルクセンブルグ)ソシエテ・ア・レスポンサビリテ・リミテ 空隙形成用組成物、その組成物を用いて形成された空隙を具備した半導体装置、およびその組成物を用いた半導体装置の製造方法
EP3065164A1 (en) * 2015-03-04 2016-09-07 ABB Technology AG Power semiconductor arrangement and method of generating a power semiconductor arrangement
WO2020014499A1 (en) * 2018-07-13 2020-01-16 Array Photonics, Inc. Dual-depth via device and process for large back contact solar cells
DE102020135088A1 (de) * 2020-03-27 2021-09-30 Samsung Electronics Co., Ltd. Halbleitervorrichtung
CN113517205A (zh) * 2020-04-27 2021-10-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11699663B2 (en) 2020-04-27 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme design for wafer singulation
CN115939222B (zh) * 2022-11-24 2025-10-17 湖南三安半导体有限责任公司 半导体器件及其制备方法
CN116936592A (zh) * 2023-07-24 2023-10-24 华天科技(昆山)电子有限公司 一种高可靠性的cis芯片封装结构及方法

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US4198444A (en) * 1975-08-04 1980-04-15 General Electric Company Method for providing substantially hermetic sealing means for electronic components
US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
US5161093A (en) 1990-07-02 1992-11-03 General Electric Company Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive
JP3453390B2 (ja) * 1996-10-08 2003-10-06 日立化成工業株式会社 半導体装置、半導体チップ搭載用基板及びその製造法
US6376908B1 (en) * 1997-12-10 2002-04-23 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package and process for the production thereof
US6239980B1 (en) 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
JP3602000B2 (ja) * 1999-04-26 2004-12-15 沖電気工業株式会社 半導体装置および半導体モジュール
US6232151B1 (en) 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
JP4454814B2 (ja) * 2000-08-29 2010-04-21 Necエレクトロニクス株式会社 樹脂封止型半導体装置及びその製造方法
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US7262444B2 (en) 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure
JP5033682B2 (ja) * 2008-03-12 2012-09-26 株式会社テラミクロス 半導体素子およびその製造方法並びに半導体装置およびその製造方法
WO2009156970A1 (en) * 2008-06-26 2009-12-30 Nxp B.V. Packaged semiconductor product and method for manufacture thereof
TW201101547A (en) * 2009-06-23 2011-01-01 Univ Kun Shan Packaging structure of light emitting diode

Also Published As

Publication number Publication date
EP2463901A2 (en) 2012-06-13
EP2463901A3 (en) 2012-08-29
US8310040B2 (en) 2012-11-13
SG182076A1 (en) 2012-07-30
EP2463901B1 (en) 2018-06-13
TW201246475A (en) 2012-11-16
PH12011000403A1 (en) 2014-07-23
US8586421B2 (en) 2013-11-19
US20120329207A1 (en) 2012-12-27
US20120146234A1 (en) 2012-06-14
CN102543946A (zh) 2012-07-04
JP2012124486A (ja) 2012-06-28
JP5926547B2 (ja) 2016-05-25
CN102543946B (zh) 2016-12-07
KR20120089993A (ko) 2012-08-16
KR101944477B1 (ko) 2019-01-31

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