SG182076A1 - Semiconductor device package and method of manufacturing thereof - Google Patents

Semiconductor device package and method of manufacturing thereof Download PDF

Info

Publication number
SG182076A1
SG182076A1 SG2011090644A SG2011090644A SG182076A1 SG 182076 A1 SG182076 A1 SG 182076A1 SG 2011090644 A SG2011090644 A SG 2011090644A SG 2011090644 A SG2011090644 A SG 2011090644A SG 182076 A1 SG182076 A1 SG 182076A1
Authority
SG
Singapore
Prior art keywords
semiconductor device
passivation layer
device package
dielectric
connection pads
Prior art date
Application number
SG2011090644A
Other languages
English (en)
Inventor
Richard Alfred Beaupre
Paul Alan Mcconnelee
Arun Virupaksha Gowda
Thomas Bert Gorczyca
Original Assignee
Gen Electric
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Gen Electric filed Critical Gen Electric
Publication of SG182076A1 publication Critical patent/SG182076A1/en

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/137—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being directly on the semiconductor body
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/117—Shapes of semiconductor bodies
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/08—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs
    • H10W70/09—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers by depositing layers on the chip or wafer, e.g. "chip-first" RDLs extending onto an encapsulation that laterally surrounds the chip or wafer, e.g. fan-out wafer level package [FOWLP] RDLs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/144—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations comprising foils
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/0711—Apparatus therefor
    • H10W72/07131—Means for applying material, e.g. for deposition or forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Light Receiving Elements (AREA)
  • Semiconductor Integrated Circuits (AREA)
SG2011090644A 2010-12-08 2011-12-07 Semiconductor device package and method of manufacturing thereof SG182076A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US12/962,761 US8310040B2 (en) 2010-12-08 2010-12-08 Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof

Publications (1)

Publication Number Publication Date
SG182076A1 true SG182076A1 (en) 2012-07-30

Family

ID=45002829

Family Applications (1)

Application Number Title Priority Date Filing Date
SG2011090644A SG182076A1 (en) 2010-12-08 2011-12-07 Semiconductor device package and method of manufacturing thereof

Country Status (8)

Country Link
US (2) US8310040B2 (enExample)
EP (1) EP2463901B1 (enExample)
JP (1) JP5926547B2 (enExample)
KR (1) KR101944477B1 (enExample)
CN (1) CN102543946B (enExample)
PH (1) PH12011000403A1 (enExample)
SG (1) SG182076A1 (enExample)
TW (1) TWI544590B (enExample)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8431438B2 (en) * 2010-04-06 2013-04-30 Intel Corporation Forming in-situ micro-feature structures with coreless packages
US9209151B2 (en) 2013-09-26 2015-12-08 General Electric Company Embedded semiconductor device package and method of manufacturing thereof
US9806051B2 (en) 2014-03-04 2017-10-31 General Electric Company Ultra-thin embedded semiconductor device package and method of manufacturing thereof
KR101978027B1 (ko) * 2014-05-15 2019-05-13 인텔 코포레이션 집적 회로 조립체용 성형 복합 인클로저
CN106471057A (zh) * 2014-05-29 2017-03-01 Az电子材料（卢森堡）有限公司 空隙形成用组合物、具备使用该组合物而形成的空隙的半导体装置、以及使用了该组合物的半导体装置的制造方法
EP3065164A1 (en) * 2015-03-04 2016-09-07 ABB Technology AG Power semiconductor arrangement and method of generating a power semiconductor arrangement
CN112740425A (zh) * 2018-07-13 2021-04-30 阵列光子学公司 用于大型背接触太阳能电池的双深度通孔器件和工艺
DE102020135088A1 (de) * 2020-03-27 2021-09-30 Samsung Electronics Co., Ltd. Halbleitervorrichtung
CN113517205A (zh) * 2020-04-27 2021-10-19 台湾积体电路制造股份有限公司 半导体器件及其形成方法
US11699663B2 (en) 2020-04-27 2023-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Passivation scheme design for wafer singulation
CN115939222B (zh) * 2022-11-24 2025-10-17 湖南三安半导体有限责任公司 半导体器件及其制备方法
CN116936592A (zh) * 2023-07-24 2023-10-24 华天科技（昆山）电子有限公司 一种高可靠性的cis芯片封装结构及方法

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4198444A (en) * 1975-08-04 1980-04-15 General Electric Company Method for providing substantially hermetic sealing means for electronic components
US4249299A (en) * 1979-03-05 1981-02-10 Hughes Aircraft Company Edge-around leads for backside connections to silicon circuit die
US5161093A (en) 1990-07-02 1992-11-03 General Electric Company Multiple lamination high density interconnect process and structure employing a variable crosslinking adhesive
DE69738783D1 (de) * 1996-10-08 2008-07-31 Hitachi Chemical Co Ltd Halbleiteranordnung, halbleiterchipträgersubstrat, herstellungsverfahren für anordnung und substrat, klebstoff und doppelseitiges haftklebeband
US6376908B1 (en) * 1997-12-10 2002-04-23 Mitsubishi Gas Chemical Company, Inc. Semiconductor plastic package and process for the production thereof
US6239980B1 (en) 1998-08-31 2001-05-29 General Electric Company Multimodule interconnect structure and process
US6306680B1 (en) 1999-02-22 2001-10-23 General Electric Company Power overlay chip scale packages for discrete power devices
JP3602000B2 (ja) * 1999-04-26 2004-12-15 沖電気工業株式会社 半導体装置および半導体モジュール
US6232151B1 (en) 1999-11-01 2001-05-15 General Electric Company Power electronic module packaging
JP4454814B2 (ja) * 2000-08-29 2010-04-21 Ｎｅｃエレクトロニクス株式会社 樹脂封止型半導体装置及びその製造方法
US7633765B1 (en) * 2004-03-23 2009-12-15 Amkor Technology, Inc. Semiconductor package including a top-surface metal layer for implementing circuit features
US7262444B2 (en) 2005-08-17 2007-08-28 General Electric Company Power semiconductor packaging method and structure
JP5033682B2 (ja) * 2008-03-12 2012-09-26 株式会社テラミクロス 半導体素子およびその製造方法並びに半導体装置およびその製造方法
EP2291858B1 (en) * 2008-06-26 2012-03-28 Nxp B.V. Packaged semiconductor product and method for manufacture thereof
TW201101547A (en) * 2009-06-23 2011-01-01 Univ Kun Shan Packaging structure of light emitting diode

Also Published As

Publication number Publication date
JP2012124486A (ja) 2012-06-28
TWI544590B (zh) 2016-08-01
TW201246475A (en) 2012-11-16
US20120329207A1 (en) 2012-12-27
EP2463901A3 (en) 2012-08-29
US8310040B2 (en) 2012-11-13
CN102543946B (zh) 2016-12-07
KR20120089993A (ko) 2012-08-16
US8586421B2 (en) 2013-11-19
KR101944477B1 (ko) 2019-01-31
PH12011000403A1 (en) 2014-07-23
EP2463901A2 (en) 2012-06-13
US20120146234A1 (en) 2012-06-14
CN102543946A (zh) 2012-07-04
EP2463901B1 (en) 2018-06-13
JP5926547B2 (ja) 2016-05-25

Similar Documents

Publication Publication Date Title
US8310040B2 (en) Semiconductor device package having high breakdown voltage and low parasitic inductance and method of manufacturing thereof
US10497648B2 (en) Embedded electronics package with multi-thickness interconnect structure and method of making same
US8466007B2 (en) Power semiconductor module and fabrication method
EP2469591B1 (en) Semiconductor device package and method for fabricating the same
US12218098B2 (en) Chip assembling on adhesion layer or dielectric layer, extending beyond chip, on substrate
US10312194B2 (en) Stacked electronics package and method of manufacturing thereof
US10804115B2 (en) Electronics package with integrated interconnect structure and method of manufacturing thereof
US10770444B2 (en) Electronics package having a multi-thickness conductor layer and method of manufacturing thereof
US10700035B2 (en) Stacked electronics package and method of manufacturing thereof
EP2302676A1 (en) High power semiconductor device
US20130214435A1 (en) Epoxy encapsulating and lamination adhesive and method of making same
KR101124112B1 (ko) 전기 소자 및 상기 전기 소자를 위한 전기 접속 리드를포함하는 시스템, 및 상기 시스템을 제작하기 위한 방법
US20170278810A1 (en) Embedded die in panel method and structure