TWI543381B - 半導體裝置 - Google Patents
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Description
本發明關於一種渠溝-MOS屏障肖特基二極體(Trench-MOS-Barrier-Schottky-Diode,TMBS)，它具有在渠溝底下方浮動的(gefloatet，英：floated)p-盆地(Wanne，英：trough)，當作限幅(削波)(Klammer，英：clip)元件，此二極體特別適合用在汽車發電機系統中當作Z-功率二極體，其貫穿電壓(Durchbruchspannung，英：breakdown voltage)約20伏特。
在現代汽車中，利用電構件作越來越多的功能。因此對電功率的需求越來越高，為了涵蓋這種需求，故汽車中的發電機系統的效率須提高。迄今一般使用PN二極體當作汽車發電機系統中的Z二極體。此PN二極體的優點一方面為低的阻斷電流(反向電流)(Sperrstrom，英：reverse current)，另方面為高強固性(robustness)。其主要缺點為高的流通電壓(Flußspannung)UF。在室溫時，電流在UF=0.7伏特時才開始流通。在正常的操作條件下，例如電流密度500安培/每平方公分，UF上升到超過1伏特，這點表示發電機的效率有不可忽視的損失。
理論上，可用肖特基二極體(Schottky-Diode)當作另一選擇。肖特基二極體的流過電壓遠比PN二極體低得多，例如在高電流密度500安培/每平方公分時為0.5伏特~0.6伏特。此外，肖特基二極體當作主體載體(Majority
carrier)的構件時，在作迅速切換操作時很有利。但迄今仍未有使用肖特基二極體在汽車發電機系統中者。其原因係可歸究於肖特基二極體的一些主要缺點：
1)相較於PN二極體來，阻斷電流較高
2)阻斷電流受阻斷電壓的影響很大，及
3)強固性(Robustheit，英：robustness)差，特別是在高溫時。
已有人主張將肖特基二極體改善，其一例子為TMBS(Trench-MOS-Barrier-Schottky-Diode)，見T.酒井氏，等人“Experimental Investigation of dependence of electrical characteristics on device parameters in Trench MOS Barrier Schettky Diodes”,Proceedings of 1998 International Symposium on Power Semiconductors & Ics，京都，293~296頁)及DE 69428996 A1.
如圖1所示，該TMBS由以下之物構成：--一個n+-基材(1)；--一個n-磊晶層(2)(Epischicht，英：epi-layer)；--至少二個渠溝(6)〔它們藉著在n磊晶層(2)中蝕刻而造成〕；--在晶片前側上的金屬層(4)，當作陽極電極；--在晶片後側上的金屬層(5)，當作陽極電極；以及--在渠溝(6)與金屬層(4)之間的氧化物層(7)。
從電學觀點，該TMBS係一種MOS構造〔它具有一金屬層(4)、氧化物層(7)及一n-磊晶層〕與一肖特基二極體〔它具有金屬層(4)(當作陽極)與n-磊晶層(2)(當作陰極)之
間的肖特基屏障〕的組合。電流沿流通方向流過渠溝之間的台面範圍(Mesa-Bereich，英：Mesa-zone)。渠溝(6)本身不能讓電流流過。因此，電流沿流通方向流過的有效面積，在TMBS的場合比起傳統扁平(Planar)肖特基二極體更小。
TMBS的優點在於可減少阻斷電流(Sperrström)。在MOS構造以及肖特基二極體的場合，沿阻斷方向都會形成空間電荷區域，隨著電壓升高，空間電荷區域擴展，且當電壓小於TMBS的貫穿電壓時，互相在相鄰的渠溝(6)之間的範圍中央相碰在一起，如此，該與高阻斷電流有關的肖特基效應受遮蔽，且阻斷電流減少。這種遮蔽效應與以下構造參數(渠溝深度Dt、渠溝間距離Wm、渠溝寬度Wt)以及與氧化物層厚度To很有關係，見圖1。
先前技術製造TMBS係如下：
--藉著n-磊晶層(2)蝕刻做出渠溝(6)
--生長氧化層(7)
--將渠溝用多晶矽構成之導電的摻雜層充填。
另種變更方式，渠溝可用金屬充填。
只要渠溝的深度Dt遠大於渠溝間的距離Wm，則在渠溝(6)之間的中間範圍中的空間電荷區域的擴展為宛如一次空間者(quasi-one dimensional)。
但TMBS的一缺點為MOS構造弱。當貫穿時，在氧化層(7)內以及在n-磊晶層(2)中的氧化層附近產生很高的電場，其結果會使得「熱」的電荷載體從n-磊晶層(2)注入(Injektion)氧化層(7)中而使MOS構造崩解
(degradieren)，且在特定操作條件下甚至會破壞。TMBS的另一缺點為具有圓形或軟性的「阻斷特性線」。換言之，早在原來的貫穿之前，換言之，當電壓等於貫穿電壓的70~80%時，「阻斷電流」已明顯上升且遠大於在較小電壓時的阻斷電流。這種偏大的阻斷電流在肖特基二極體提前貫穿(Vordurchbruch，英：prematured breakdown)時，特別是在高溫時，會造成很大的功率損失，且由於正的(positiv)電熱回耦作用，造成熱的不穩定(thermal runaway)以及使構件故障。
本發明的目的在提供具有高強固性及較小流通電壓的肖特基二極體，它們適用於在汽車發電機系統中當作Z功率二極體用。在此，藉著將PN保護二極體與肖特基二極體作整合串聯，可使肖特基二極體即使在電壓穿透時也能可靠地操作，此操作模式係在汽車發電機中使用時對負載傾卸(Load dump)的保護為必要者。
本發明的肖特基二極體係一種TMBS，它具有在渠溝底下方的浮動的盆地，該PN二極體(它由該浮動的p盆地與n-磊晶層構成)決定本發明的TMBS的貫穿電壓，且當作限幅(削波)元件(Klammerelement，英：clipping element)。在此，p-盆地的設計方式選設成使該PN二極體的貫穿電壓BV-pn小於該肖特基二極體的貫穿電壓BV-肖特基及該MOS構造的貫穿電壓BV-mos，且本發明的TMBS有一種角落式的阻斷特性曲線。當貫穿時，氧化層中的電場強度遠比在傳統TMBS的場合小。
本發明的優點為：相較於傳統TMBS，由於整合之PN二極體的限幅功能，因此其強固性和穩定性高，且因此適合用於汽車發電機系統中當作Z二極體，這是因為在氧化物上存在的電場強度較小之故。本發明的裝置可利用一種變更的渠溝功率MOSFET標準程序表示。
如圖2所示，本發明的TMBS(它具有下渠溝底下方的浮動p盆地)由一n+基材、一n-磊晶層(2)、至少二個渠溝(6)[它們被蝕刻到該n-磊晶層(2)中，其寬度Wt、深度Dt、而相鄰之渠溝(6)之間的距離為Wm]、以及在晶片前側上的金屬層(4)(當作陽極電極)與在晶片後側上的金屬層(5)(當作陰極電極)以及在渠溝(6)的表面上的氧化層(其厚度To)。在渠溝底下方，有用電方式浮動的p盆地(8)，其厚度Dp，該p-盆地與n-磊晶層(2)共同構成PN過渡區。
從電學觀點看，本發明之在渠溝底下方具有浮動的p盆地的TMBS係一種用一個MOS構造[它具有金屬層(4)與氧化層(7)及n-磊晶層(2)]以及一個肖特基二極體[它具有金屬層(4)(當作陽極)與n-磊晶層(2)(當作陰極)之間的肖特基屏障]和一PN二極體[它具有浮動盆地(8)(當作陽極)與n-磊晶層(2)(當作陰極)之間的PN過渡區]的組合。這些浮動的p盆地(8)設計成使本發明的TMBS的貫穿電壓由p盆地(8)與n-磊晶層(2)之間的PN過渡區的貫穿電壓決定。
在本發明之TMBS(它具有在渠溝底下方的浮動p盆地)的場合，一如傳統TMBS，電流沿流通方向只流過肖特基二極體(如果肖特基二極體的貫穿電壓遠小於PN二極體的貫穿電壓的話)。在該MOS構造、肖特基二極體及PN二極體的場合，沿阻斷方向形成空間電荷區域，這些空間電荷區域隨電壓上升而在磊晶層(2)中及p-盆地中擴展，且當電壓小於本發明的TMBS的貫穿電壓時，就在相鄰的渠溝(6)之間的範圍的中央碰在一起。如此，該與高阻斷電流有關的肖特基效應(屏障降低作用)受到遮蔽，且阻斷電流減少，這種遮蔽效應由MOS構造及p盆地決定，且與以下構造參數很有關：渠溝的深度Dt、渠溝間的距離、渠溝寬度Wt、氧化層層(To)的厚度以及p盆地的厚度Dp。在貫穿操作時，「阻斷電流」流經該浮動之p盆地，然後流經MOS構造的反相層(Inversionschicht)到肖特基接點，換言之，PN二極體與肖特基二極體係串聯者。本發明的TMBS具有和傳統TMBS相似的肖特基效應的遮蔽作用，但另外由於整合的限幅功能，更有高強固性。PN二極體的貫穿電壓BV-pn設計成使BV-pn小於肖特基二極體的貫穿電壓BV_肖特基以及MOS構造的貫穿電壓BV-MOS，且貫穿作用在p盆地與n-磊晶層(2)之間的PN過渡區以及在p盆地的底發生。因此在貫穿時，高電場強度位於p盆地的底，且在MOS構造附近的電場強度遠小於傳統TMBS的場合，這點對於要避免由於「熱」電荷或體注入氧化物層(7)中造成的構件的不穩定而言很有利。如此可避免貫穿電壓「漂移」(Drife)的情事。因此本發明之具有在渠溝底下方的浮動p盆地的TMBS很適合用於汽車發電機系統中當作Z功率二極體。
如果PN二極體的貫穿電壓BV-pn小於肖特基二極體的貫穿電壓BV-肖特基，例如BV-pn=BV-肖特基的50%，則本發明的TBMS具有角落形的「阻斷特性線」，換言之，傳統TMBS的肖特基二極體的所謂「提前貫穿」的情事不再發生。這是使構件的強固性提高。
利用階段磊晶層，可將角落形特性曲線作得甚至更容易。如圖3所示，該n磊晶層不同於圖2的變更例，不再做成具一致的摻雜濃度，而係從上往下劃分成二個不同摻雜濃度的範圍，上磊晶層(2a)可使肖特基二極體的貫穿電壓BV-肖特基較高且其摻雜量低，下n-磊晶層(2b)(p-盆地的下範圍擴散進入其中)具較高摻雜濃度。因此該浮動p盆地與下n-磊晶層之間的PN過渡區有較低的貫穿電壓且因此決定PN二極體的貫穿電壓以及本發明的TMBS的貫穿電壓。
在本發明的TMBS，在晶片的邊緣範圍還比具有附加的構造以減少邊緣場強度。舉例而言，這點可為低摻雜的p範圍、場板或和先前技術相關的類似構造，也可將這些或所有半導體層由相反的導電類型構成並將陽極與陰極端子更換。
本發明的第一種製造具有浮動p盆地的TMBS的方法包含以下步驟：
--作磊晶
--作渠溝蝕刻
--將渠溝表面氧化
--將渠溝的底上的氧化物層蝕刻
--將p-盆地擴散通過渠溝底
--將渠溝的側壁和底上的氧化物層蝕刻
--將渠溝表面氧化
--將渠溝用摻雜的多晶矽充填
--將晶片前側及後側鍍上金屬層。
本發明第二種製造具有浮動的p-盆地的TMBS的方法包含以下步驟：
--用n+基材當作起始材料
--作磊晶
--作渠溝蝕刻
--將渠溝用p摻雜的矽或多晶矽充填到一種厚度Dp為止
--如有必要，將渠溝中的p摻雜的矽或多晶矽的一部分蝕刻
--將渠溝表面氧化
--將渠溝用摻雜的多晶矽充填
--將晶片前側及後側鍍上金屬層。
(1)‧‧‧n+基材
(2)‧‧‧n-磊晶層
(4)‧‧‧晶片前側上的金屬層
(5)‧‧‧晶片後側上的金屬層
(6)‧‧‧渠溝
(7)‧‧‧氧化物層
(8)‧‧‧p-摻椎層
Dt‧‧‧渠溝深度
Mm‧‧‧渠溝間距離
Wt‧‧‧渠溝寬度
To‧‧‧氧化物層厚度
圖1係一TMBS(渠溝MOS屏障二極體)；圖2係一本發明的TMBS(渠溝MOS屏障二極體)，具有渠溝底下方的浮動p盆地；圖3係一本發明的TMBS(渠溝MOS屏障二極體)，具有渠溝底下方的浮動p盆地，以及階段磊晶層。
(1)．．．n+基材
(2)．．．n-磊晶層
(4)．．．晶片前側上的金屬層
(5)．．．晶片後側上的金屬層
(6)．．．渠溝
(7)．．．氧化物層
(8)．．．p-摻椎層
Dt．．．渠溝深度
Mm．．．渠溝間距離
Wt．．．渠溝寬度
To．．．氧化物層厚度
Claims (15)
- 一種半導體裝置，具有一渠構MOS屏障肖特基二極體(TMBS)，其由一n-磊晶層(2)及一金屬層構成，該n-磊晶層(2)和該金屬層構成一肖特基二極體，其中在該n-磊晶層中至少有二個蝕刻的渠溝(6)，呈二度空間呈示方式位在一n+-基材(1)上，該基材(1)當作陰極區域，其中在該n-磊晶層(2)中至少在渠溝(6)的底下方一位置有一電性浮動的p摻雜層(8)，其當作一pn二極體的陽極區域且其中在該金屬層(4)與渠溝(6)的表面間有一氧化物層(7)，其特徵在：該n-摻雜磊晶層由二個不同摻雜的n-層組成，其包含一上磊晶層(2)及一下磊晶部分層(2b)，該上磊晶層係一低摻雜之n-層，該下部分磊晶層(2b)接到該上磊晶層(2)且摻雜濃度較該上磊晶層(2)更高，且該p-摻雜層(8)的下區域擴散到該下磊晶部分層(2b)中，其中在該電性浮動的p-摻雜層(8)和該下磊晶部分層(2b)之間的pn過渡區的貫穿電壓比該肖特基二極體的貫穿電壓(BV-肖特基)和該渠溝MOS屏障肖特基二極體(TMBS)的MOS構造的貫穿電壓(BV-MOS)更低，且決定該pn-二極體的貫穿電壓以及該渠溝MOS屏障肖特基二極體(TMBS)的貫穿電壓。
- 如申請專利範圍第1項之半導體裝置，其中：該PN二極體的貫穿電壓(BV-pn)在該肖特基二極體的貫穿電壓(BV-肖特基)的50%範圍。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該p盆地(8)與n-磊晶層(2)(2b)設計成使該TMBS的貫穿電壓由該PN二極體決定，且貫穿用在p盆地(8)的底發生。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該半導體裝置在貫穿時可用高電流操作。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該半導體裝置的貫穿電壓在20伏特~40伏特範圍。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該半導體裝置可用在汽車發電機中當作整流二極體及/或負載傾卸保護二極體。
- 如申請專利範圍第1或第2項之半導體裝置，其中：在晶片的後側上有一金屬層(5)當作陰極電極，而晶片的前側上有一金屬層(4)當作陽極電極，該金屬層(4)具有接到n-磊晶層(2)的肖特基接點。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該渠溝(6)具長方形或U形或可預設形狀的造形。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該渠溝(6)排列成條帶狀或島狀，其中這些島設計成圓形、六角形或可適當地預設的形狀。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該晶片(4)前側上的金屬層(5)將渠溝(6)充填。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該浮動的p盆地(8)係藉著通過渠溝底的p-擴散作用與藉著將渠溝的下範圍用p摻雜的矽或多晶矽充填而造成。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該渠溝(6)係藉著蝕刻到n-磊晶層中而形成。
- 如申請專利範圍第1或第2項之半導體裝置，其中：該半導體層由相反之導通類形構成，且陽極端子與陰 極端子互換。
- 一種用於製造上述申請專利範圍的任一項的一種半導體裝置的方法，其特徵在：至少作以下步驟：--用作n+基材當作起始材料--作磊晶--作出渠溝蝕刻--將渠溝表面氧化--將渠溝的結合部上的氧化物層蝕刻--將p-盆地擴散通過渠溝底--將渠溝的側壁和底上的氧化物層蝕刻--將渠溝表面氧化--將渠溝用摻雜的多晶矽充填--將晶片前側及後側鍍上金屬層。
- 一種用於製造申請專利範圍第1~13項任一項的一種半導體裝置的方法，其特徵在，至少作以下的步驟：--用n+基材當作起始材料--作磊晶層--作渠溝蝕刻--將渠溝用p摻雜的矽或多晶矽充填到一種厚度Dp為止--如有必要，將渠溝中的p摻雜的矽或多晶矽的一部分蝕刻--將渠溝表面氧化--將渠溝用摻雜的多晶矽充填--將晶片前側及後側鍍上金屬層。
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| DE102009028248A DE102009028248A1 (de) | 2009-08-05 | 2009-08-05 | Halbleiteranordnung |
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| DE102011087591A1 (de) * | 2011-12-01 | 2013-06-06 | Robert Bosch Gmbh | Hochspannungs-Trench-Junction-Barrier-Schottkydiode |
| CN103378131A (zh) * | 2012-04-29 | 2013-10-30 | 朱江 | 一种电荷补偿肖特基半导体装置及其制造方法 |
| US9018698B2 (en) * | 2012-11-16 | 2015-04-28 | Vishay General Semiconductor Llc | Trench-based device with improved trench protection |
| US8981528B2 (en) | 2012-11-16 | 2015-03-17 | Vishay General Semiconductor Llc | GaN-based Schottky diode having partially recessed anode |
| US8981381B2 (en) | 2012-11-16 | 2015-03-17 | Vishay General Semiconductor Llc | GaN-based Schottky diode having dual metal, partially recessed electrode |
| JP2014120685A (ja) * | 2012-12-18 | 2014-06-30 | Toshiba Corp | 半導体装置 |
| CN109192786A (zh) * | 2018-08-22 | 2019-01-11 | 江苏中科君芯科技有限公司 | 一种具有浮空p岛的沟槽型二极管及其制备方法 |
| CN111816693A (zh) * | 2019-04-10 | 2020-10-23 | 台湾茂矽电子股份有限公司 | 二极管结构及其制造方法 |
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| US5365102A (en) | 1993-07-06 | 1994-11-15 | North Carolina State University | Schottky barrier rectifier with MOS trench |
| US6078090A (en) | 1997-04-02 | 2000-06-20 | Siliconix Incorporated | Trench-gated Schottky diode with integral clamping diode |
| US6252258B1 (en) | 1999-08-10 | 2001-06-26 | Rockwell Science Center Llc | High power rectifier |
| US7186609B2 (en) * | 1999-12-30 | 2007-03-06 | Siliconix Incorporated | Method of fabricating trench junction barrier rectifier |
| US6392273B1 (en) * | 2000-01-14 | 2002-05-21 | Rockwell Science Center, Llc | Trench insulated-gate bipolar transistor with improved safe-operating-area |
| US6707127B1 (en) * | 2000-08-31 | 2004-03-16 | General Semiconductor, Inc. | Trench schottky rectifier |
| DE102004053760A1 (de) * | 2004-11-08 | 2006-05-11 | Robert Bosch Gmbh | Halbleitereinrichtung und Verfahren für deren Herstellung |
| JP5351519B2 (ja) * | 2005-12-27 | 2013-11-27 | パワー・インテグレーションズ・インコーポレーテッド | 高速回復整流器構造体の装置および方法 |
| DE102007029121B3 (de) * | 2007-06-25 | 2008-11-20 | Infineon Technologies Austria Ag | Verfahren zur Herstellung eines Halbleiterbauelements, sowie Halbleiterbauelement |
| TWI366235B (en) | 2007-11-14 | 2012-06-11 | Chip Integration Tech Co Ltd | High switching speed two mask schottky diode with high field breakdown |
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| US9263599B2 (en) | 2016-02-16 |
| TW201108421A (en) | 2011-03-01 |
| DE102009028248A1 (de) | 2011-02-10 |
| WO2011015394A1 (de) | 2011-02-10 |
| EP2462620B1 (de) | 2017-05-17 |
| US20120181652A1 (en) | 2012-07-19 |
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