TWI529874B - 封裝結構及其形成方法 - Google Patents

封裝結構及其形成方法 Download PDF

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TWI529874B
TWI529874B TW103115923A TW103115923A TWI529874B TW I529874 B TWI529874 B TW I529874B TW 103115923 A TW103115923 A TW 103115923A TW 103115923 A TW103115923 A TW 103115923A TW I529874 B TWI529874 B TW I529874B
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conductive pattern
dielectric layer
die
encapsulant
sealant
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TW201523806A (zh
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許峰誠
盧思維
林俊成
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台灣積體電路製造股份有限公司
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Description

封裝結構及其形成方法
本發明係關於一種封裝技術，且特別是關於一種扇出(fan-out)之封裝結構及其形成方法。
半導體裝置應用於各種電子用品，例如個人電腦、行動電話、數位相機及其它電子設備。半導體裝置通常藉由在半導體基板上依序沈積絕緣或介電層、導電層及半導體層之材料，並使用微影法來圖案化上述多種材料層，以形成半導體基板上之電路構件及元件。通常會於單一半導體晶圓上製作數十種甚至數百種積體電路，並藉由沿著一切割道切割上述積體電路來單粒化個別晶粒。隨後分別將上述各個晶粒封裝於例如多晶片模組內或其它類型之封裝結構內。
半導體工業藉由持續降低最小特徵尺寸來持續提昇各種電子構件(例如，電晶體、二極體、電阻、電容等)的集積密度(integration density)，其允許將更多構件整合進一給定的區域內。這些較小的電子構件(例如積體電路晶粒)在一些用途中可能會需要比過去的封膠體耗用更小區域之較小的封膠體。
本發明一實施例提供一種封裝結構，包括一晶粒，其包括位於一主動層側上之一電性焊墊，一封膠體，其側 向圍繞晶粒且延伸於晶粒之主動層側正上方，以及一第一導電圖案，位於封膠體上，第一導電圖案包括一第一開口內之一第一介層連接窗，其貫穿封膠體而到達電性焊墊，第一介層連接窗接觸電性焊墊。
本發明另一實施例提供一種封裝結構，包括一晶粒，於一側邊具有一電性焊墊，一封膠體，圍繞晶粒且位於晶粒之側上，封膠體在平行晶粒之側的一方向上，由自晶粒側向位移之一第一區域連續延伸至位於晶粒之側正上方的一第二區域，一第一導電圖案，位於封膠體上，第一導電圖案包括一第一開口內之一第一介層連接窗，其貫穿封膠體而到達電性焊墊，一第一介電層，位於封膠體及第一導電圖案上，以及一第二導電圖案，位於第一介電層上，第二導電圖案包括一第二開口內之一第二介層連接窗，其貫穿第一介電層而到達第一導電圖案。
本發明又一實施例提供一種封裝結構之形成方法，包括形成一封膠體，側向封膠一晶粒且位於晶粒之一主動表面上，主動表面包括一電性焊墊，形成一第一開口，貫穿封膠體而到達電性焊墊，以及於封膠體上形成一第一導電圖案，第一導電圖案包括位於第一開口內到達電性焊墊之一第一介層連接窗。
30‧‧‧晶粒
32‧‧‧頂部金屬化層
34‧‧‧焊墊
36‧‧‧鈍化保護層
38‧‧‧承載基底
40、80‧‧‧介電封膠體
42、48、54、64、68、82‧‧‧開口
44、70、84‧‧‧第一導電圖案
46‧‧‧第二介電層
50‧‧‧第二導電圖案
52‧‧‧第三介電層
56‧‧‧接合墊
58‧‧‧外部電性連接體
60‧‧‧暫時性支柱
62‧‧‧封膠體
66‧‧‧第一介電層
第1~7圖為依據本發明一實施例所繪示之一製程中的各種中間結構。
第8~15圖為依據本發明其它數個實施例所繪示之不同製程中的各種中間結構。
第16~21圖為依據本發明其它數個實施例所繪示之不同製程中的各種中間結構。
以下說明本發明實施例之製作與使用。然而，可輕易了解本發明實施例提供許多合適的發明概念而可實施於廣泛的各種特定背景。所揭示的特定實施例僅僅用於說明以特定方法製作及使用本發明，並非用以侷限本發明的範圍。
以下參照特定前後文說明本發明實施例，即扇出(fan-out)封裝結構及其形成方法，但這些實施例亦可應用於其它封裝結構。此處討論之實施例係用以提供本發明之申請專利標的之製作與使用，且發明所屬技術領域中具有通常知識者能夠了解可在不脫離本發明之精神和範圍作出更動及潤飾。以下圖式及討論內容係說明經簡化的結構以使特徵顯著，並忽略對發明所屬技術領域中具有通常知識者顯而易見之不必要的細節。圖式及說明中使用相同的標號來表示相同或相似的部件。雖然方法實施例係以特定實施順序討論，但亦可依任何合理順序來實施其它方法實施例。
第1~7圖為依據本發明一實施例所繪示之一製程中的各種中間結構。第1圖顯示了藉由一介電封膠體40進行封膠之一晶粒30。晶粒30包括位於晶粒30之主動層側上的一頂部金屬化層32、一焊墊34(例如一電性連接焊墊)以及一鈍化保護層36。晶粒30可為例如一邏輯積體電路、一記憶體晶粒、一 類比晶粒或其它任何晶粒。晶粒30可包括一半導體基底，例如一塊材半導體基底、絕緣體上半導體基底(semiconductor-on-insulator substrate)等等。其上藉由半導體製程而形成有主動裝置(例如，電晶體)及/或被動裝置(例如，電容、電感)等等。金屬化層(包括頂部金屬化層32)可位於半導體基底上，並可包括內連接體構以使裝置彼此電性耦接及/或耦接至焊墊34。焊墊34透過鈍化保護層36內的各個開口而露出。
在一範例中，晶粒30可形成為一晶圓的一部份。藉由例如切割或鋸斷來將晶圓單粒化(singulated)以形成個別晶粒30。使用例如一揀取及放置(pick-and-place tool)工具將晶粒30放置於承載基底38上，其可為玻璃基底、矽基底、氧化鋁基底等等，並藉由一晶粒貼附膜將晶粒30貼附至承載基底38，例如任何適當接著劑、環氧樹脂、紫外線(UV)膠(當其暴露於紫外線下時會失去其接著性)等等。焊墊34及鈍化保護層36則設置於承載基底38之相對側。
在第1圖中，形成介電封膠體40用以側向封膠晶粒30且位於鈍化保護層36及焊墊34上。如圖所示，介電封膠體40由側向設置於晶粒30之一區域連續延伸至設置於晶粒30正上方之一區域。例如，在鄰近晶粒30之一側邊，不存在與另一不同介電材料的垂直界面(其中，「垂直」係如圖所示，為垂直於晶粒30之頂部表面的一方向)，例如其不會位於晶粒30之焊墊34正上方。介電封膠體40可包括環氧樹脂模製化合物或其它任何支持晶粒30嵌入於位在基底38上之封膠體40內的介電材料，且可使用壓縮成形製程、層積製程等等來形成。在一實施 例中，介電封膠體40為可光學圖案化的。
在第2圖中，在介電封膠體40內形成開口42，以露出焊墊34。可使用適當光學微影技術來形成開口42，以使介電封膠體40暴露於光線。在上述實施例中，介電封膠體40會在曝光之後進行顯影及/或固化。
在第3圖中，在介電封膠體40上及開口42內形成到達焊墊34之一第一導電圖案44。第一導電圖案44包括各種走線(trace)及/或介層連接窗(via)，例如位於開口42內之介層連接窗。在一實施例中，第一導電圖案44包括一金屬，例如銅、鈦等等，或前述之組合，其藉由一鍍覆製程來形成，例如無電鍍法、電鍍法等等。例如，在介電封膠體40上及開口42內沈積一晶種層。晶種層可為藉由原子層沈積法(atomic layer deposition，ALD)、濺鍍法、其它物理氣相沈積製程等沈積之銅、鈦等等，或前述之組合。藉由例如一適當光學微影技術將一光阻沈積及圖案化，並曝光此圖案，以用於第一導電圖案44。藉由無電鍍法、電鍍法等等將導電材料例如銅、鋁等等，或前述之組合，沈積於晶種層上。以例如一適當光阻掀除製程將光阻移除，並藉由例如一濕式或乾式蝕刻來移除剩餘曝光之晶種層部份。
在第4圖中，在介電封膠體40及第一導電圖案44上形成一第二介電層46。第二介電層46可包括聚苯并噁唑(polybenzoxazole，PBO)、聚亞醯胺、苯并環丁烯(benzocyclobutene，BCB)等等，或前述之組合。可藉由一旋塗製程、層積製程等等，或前述之組合來沈積第二介電層 46。使用一適當光學微影技術形成貫穿第二介電層46而到達部份的第一導電圖案44的開口48，包括例如使第二介電層46內預定形成開口48之部份曝光於光線。第二介電層46可在曝光之後進行顯影及/或固化。
在第5圖中，在第二介電層46上及開口48內形成到達第一導電圖案44之部份的第二導電圖案50。第二導電圖案50包括各種走線及/或介層連接窗。在一實施例中，藉由一鍍覆製程例如無電鍍法、電鍍法等等來形成第二導電圖案50，其包括一金屬，例如銅、鈦等等，或前述之組合，如上述參照第3圖之討論內容。
在第6圖中，在第二介電層46及第二導電圖案50上形成第三介電層52。第三介電層52可包括聚苯并噁唑、聚亞醯胺、苯并環丁烯等等，或前述之組合。可藉由一旋塗製程、層積製程等等，或前述之組合，來沈積第三介電層52。使用一適當光學微影技術形成貫穿第三介電層52而到達部份的第二導電圖案50的開口54，包括例如使第三介電層52內預定形成開口54之部份曝光於光線。第三介電層52可在曝光之後進行顯影及/或固化。
在第7圖中，形成接合墊56及外部電性連接體58。將接合墊56形成為直接耦接至上述部份的第二導電圖案50，且位在開口54內及第三介電層52之頂部表面的一部分上。在一範例中，各個接合墊56可為一凸塊底層金屬(under bump metal，UBM)並可包括一金屬，例如銅、鈦等等，或前述之組合，且藉由一鍍覆製程來形成，例如無電鍍法、電鍍法等等，如上述 參照第3圖之討論內容。在各個接合墊56上形成外部電性連接體58，例如焊球或凸塊。外部電性連接體58可包括焊料，例如無鉛焊料，並可使用一適當焊球置放(ball drop)製程來形成。隨後，可藉由例如使晶粒貼附膜露出於一溶劑或紫外線(例如當晶粒貼附膜為紫外線膠時)，由承載基底38將形成之封膠體移出。
第8~15圖為依據本發明數個實施例所繪示之不同製程中的各種中間結構。例如，可以參照第11圖所討論之步驟取代第9及10圖之步驟。在第8圖中，在晶粒30之焊墊34上形成暫時性支柱60。在一實施例中，暫時性支柱60為光阻支柱。如參照第1圖所討論之實施例，晶粒30可形成為一晶圓的部份。在單粒化之前，可在晶圓上形成一光阻材料並將其圖案化為光阻支柱。隨後單粒化此晶圓以形成個別晶粒30，並使用一晶粒貼附膜將晶粒30貼附至承載基底38。在其它實施例中，暫時性支柱60可為藉由使用光學微影及蝕刻技術在例如單粒化晶粒30之後或之前在焊墊34上沈積及圖案化之其它任何材料。
在第9圖中，形成封膠體62以封膠將晶粒30至大於暫時性支柱60高度的高度，在第10圖中，封膠體62隨後被往回研磨以露出暫時性支柱60。封膠體62可為一模製化合物等等，亦可具有介電性質。可使用一壓縮成形製程、層積製程等等來形成封膠體62，且隨後可將其固化。在第10圖中，藉由例如使用砂輪及/或化學機械研磨法來研磨封膠體62，以露出暫時性支柱60。
在第11圖中，將封膠體62形成為具有由封膠體62 露出之暫時性支柱60。可藉由使用一模板上之可壓縮及剝離薄膜的一壓縮成形製程而使暫時性支柱60由封膠體62露出。當具有可壓縮薄膜之壓縮模板與封膠體62接觸時，可使暫時性支柱60壓入此可壓縮薄膜，壓縮力可使封膠體凹陷至低於暫時性支柱60頂部的位準。用於模板上之可壓縮薄膜的例示性材料包括矽膠等等。可壓縮薄膜可為例如200μm厚。
在第10及11圖中，形成封膠體62用以為側向封膠晶粒30且位於鈍化保護層36及焊墊34上。如圖所示，封膠體62由側向設置於晶粒30的一區域連續延伸至設置於晶粒30正上方的一區域。例如，在鄰近晶粒30之一側邊，不存在與另一不同介電材料的垂直界面(其中，「垂直」係如圖所示，為在垂直於晶粒30之頂部表面的一方向上)，例如其未位於晶粒30之焊墊34正上方。在第10或11圖之後，將暫時性支柱60移除以形成到達焊墊34的開口64，如第12圖所示。在暫時性支柱60為光阻之數實施例中，可使用適當剝離製程來移除暫時性支柱60。在其它實施例中，可藉由蝕刻移除暫時性支柱60。
在第13圖中，在封膠體62上形成第一介電層66並將其圖案化，以形成通過開口64之開口68並露出焊墊34。第一介電層66可包括聚苯并噁唑、聚亞醯胺、苯并環丁烯等等，或前述之組合。可藉由一旋塗製程、層積製程等等，或前述之組合來沈積第一介電層66。使用適當之光學微影技術形成貫穿第一介電層66而到達焊墊34之開口68，包括例如使第一介電層66內預定形成開口68之部份曝光於光線。第一介電層66可在曝光之後進行顯影及/或固化。
在第14圖中，在第一介電層66及開口68內形成到達焊墊34之第一導電圖案70。第一導電圖案70包括各種走線及/或介層連接窗。在一實施例中，藉由一鍍覆製程例如無電鍍法或電鍍法等等來形成第一導電圖案70，其包括一金屬，例如銅、鈦等等，或前述之組合，如上述參照第3圖之討論內容。
在第15圖中，參照第4至7圖之討論內容來形成第二介電層46、第二導電圖案50、第三介電層52、接合墊56及外部電性連接體58。
第16~21圖為依據本發明其它數個實施例所繪示之各製程中的各種中間結構。例如，可以參照第18圖所討論之步驟取代第16及17圖之步驟。如上述第18圖所示，在晶粒30之焊墊34上形成暫時性支柱60。在一實施例中，暫時性支柱60為光阻支柱。如參照第1圖之實施例的討論內容，可將晶粒30形成為一晶圓的一部份。可在單粒化之前將光阻材料形成於晶圓上並將其圖案化為光阻支柱。隨後將晶圓單粒化以形成個別晶粒30，並使用晶粒貼附膜將晶粒30貼附於承載基底38。在其它實施例中，暫時性支柱60可為在晶粒30單粒化之前或之後藉由例如使用光學微影及蝕刻技術沉積並圖案化於焊墊34上之任何材料。
在第16圖中，形成介電封膠體80以封膠晶粒30至大於暫時性支柱60高度的高度，在第17圖中，介電封膠體80隨後被往回研磨以露出暫時性支柱60。介電封膠體80可為一聚合物，例如ABF絕緣膜(Ajinomoto Build-up Film，ABF)等等，亦可具有介電性質。可使用一壓縮成形製程來形成介電封膠體 80，例如層積製程等等，且隨後可將其固化。在第17圖中，藉由例如使用砂輪及/或化學機械研磨法研磨介電封膠體80，以露出暫時性支柱60。
在第18圖中，介電封膠體80形成為具有露出於介電封膠體80之暫時性支柱60。可藉由例如使用模板上之可壓縮及剝離薄膜的壓縮成形製程使暫時性支柱60由介電封膠體80露出。當具有可壓縮薄膜之壓縮模板與介電封膠體80接觸時，可使暫時性支柱60壓入此可壓縮薄膜，壓縮力可使封膠體凹陷至低於暫時性支柱60頂部的位準。模板上之可壓縮及剝離薄膜的例示性材料包括矽膠等等。可壓縮薄膜可為例如200μm厚。
在第17及18圖中，形成介電封膠體80用以側向封膠晶粒30且位於鈍化保護層36及焊墊34上。如圖所示，介電封膠體80由側向設置於晶粒30的一區域連續延伸至設置於晶粒30正上方之一區域。例如，在鄰近晶粒30之一側邊，不存在與另一不同介電材料的垂直界面(其中，「垂直」係如圖所示，為在垂直於晶粒30之頂部表面的一方向上)，例如其未位於晶粒30之焊墊34正上方。在第17或18圖之後，移除暫時性支柱60以形成到達焊墊34之開口82，如第19圖所示。在暫時性支柱60為光阻之數個實施例中，可使用適當剝離製程來移除暫時性支柱60。在其它實施例中，可藉由蝕刻移除暫時性支柱60。
在第20圖中，在介電封膠體80上及開口82內形成到達焊墊34之第一導電圖案84。第一導電圖案84包括各種走線及/或介層連接窗。在一實施例中，藉由一鍍覆製程例如無電鍍法或電鍍法等等來形成第一導電圖案84，其包括一金屬，例 如銅、鈦等等，或前述之組合，如上述參照第3圖之討論內容。
在第21圖中，參照第4至7圖之討論內容而形成第二介電層46、第二導電圖案50、第三介電層52、接合墊56及外部電性連接體58。
本案實施例可具有數種優點。例如，依據本案一實施例，由於例如製程步驟較少及/或較便宜，故可降低封膠體之製作成本。此外，到達焊墊(例如焊墊34)之介層連接窗圖案可具有較易控制之特徵尺寸(例如當關鍵尺寸為介於5μm至200μm之間時)、特徵尺寸均一性、側壁角度及邊緣粗糙度。
本發明一實施例為一種封裝結構，包括一晶粒，其包括位於一主動層側上之一電性焊墊，一封膠體，其側向圍繞晶粒且延伸於晶粒之主動層側正上方。一第一導電圖案位於封膠體上，且第一導電圖案包括一第一開口內之一第一介層連接窗，其貫穿封膠體而到達電性焊墊。第一介層連接窗接觸電性焊墊。
本發明另一實施例為一種封裝結構，包括一晶粒，於一側具有一電性焊墊，一封膠體，圍繞晶粒且位於晶粒之側上。封膠體在平行晶粒之側的一方向上，由自晶粒側向位移之一第一區域連續延伸至位於晶粒之側正上方的一第二區域。一第一導電圖案位於封膠體上，第一導電圖案包括一第一開口內之一第一介層連接窗，其貫穿封膠體而到達電性焊墊。一第一介電層位於封膠體及第一導電圖案上。一第二導電圖案位於第一介電層上，第二導電圖案包括一第二開口內之一第二介層連接窗，其貫穿第一介電層而到達第一導電圖案。
本發明又一實施例為一種封裝結構之形成方法，包括形成一封膠體，側向封膠一晶粒且位於晶粒之一主動表面上，主動表面包括一電性焊墊，形成一第一開口，貫穿封膠體而到達電性焊墊，以及於封膠體上形成一第一導電圖案，第一導電圖案包括位於第一開口內到達電性焊墊之一第一介層連接窗。
雖然本發明之實施例及其優點係揭露如上，然而，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可作更動、替代與潤飾。再者，本發明之保護範圍並未侷限於說明書內所述特定實施例中的製程、機器、製造、物質組成、裝置、方法及步驟，任何所屬技術領域中具有通常知識者可從本發明揭示內容中理解現行或未來所發展出的製程、機器、製造、物質組成、裝置、方法及步驟，只要可以在此處所述實施例中實施大體相同功能或獲得大體相同結果皆可使用於本發明中。因此，本發明之保護範圍包括上述製程、機器、製造、物質組成、裝置、方法及步驟。
30‧‧‧晶粒
32‧‧‧頂部金屬化層
34‧‧‧焊墊
36‧‧‧鈍化保護層
38‧‧‧承載基底
40‧‧‧介電封膠體
44‧‧‧第一導電圖案
46‧‧‧第二介電層
50‧‧‧第二導電圖案
52‧‧‧第三介電層
56‧‧‧接合墊
58‧‧‧外部電性連接體

Claims (8)

  1. 一種封裝結構，包括：一晶粒，包括位於一主動層側上之一電性焊墊；一封膠體，側向圍繞該晶粒且延伸於該晶粒之該主動層側正上方；一第一導電圖案，位於該封膠體上，該第一導電圖案包括一第一開口內之一第一介層連接窗，其貫穿該封膠體而到達該電性焊墊，該第一介層連接窗接觸該電性焊墊；以及一第一介電層，位於該封膠體上，且該第一導電圖案位於該第一介電層上，該第一介層連接窗位於該第一介電層之一第二開口內且貫穿該封膠體。
  2. 如申請專利範圍第1項所述之封裝結構，其中該封膠體為一介電封膠體，該第一導電圖案鄰接該介電封膠體。
  3. 如申請專利範圍第1項所述之封裝結構，其中該封膠體為一可光學圖案化材料、一模製化合物或一ABF絕緣膜。
  4. 如申請專利範圍第1項所述之封裝結構，更包括：一第二介電層，位於該第一導電圖案及該封膠體上；一第二導電圖案，位於該第二介電層上，該第二導電圖案包括一第二開口內之一第二介層連接窗，其貫穿該第一介電層而到達該第一導電圖案；一第三介電層，位於該第二導電圖案及該第二介電層上；一接合墊，經由該第三介電層內之一第三開口而到達該第二導電圖案；以及一外部電性連接體，位於該接合墊上。
  5. 一種封裝結構，包括：一晶粒，於一側具有一電性焊墊；一封膠體，圍繞該晶粒且位於該晶粒之該側上，該封膠體在平行該晶粒之該側的一方向上，由自該晶粒側向位移之一第一區域連續延伸至位於該晶粒之該側正上方的一第二區域；一第一導電圖案，位於該封膠體上，該第一導電圖案包括一第一開口內之一第一介層連接窗，其貫穿該封膠體而到達該電性焊墊；一第一介電層，位於該封膠體上，且該第一導電圖案位於該第一介電層上，該第一介層連接窗位於一第二開口內，其通過該第二開口內之該第一介電層；一第二介電層，位於該封膠體及該第一導電圖案上；以及一第二導電圖案，位於該第二介電層上，該第二導電圖案包括一第三開口內之一第二介層連接窗，其貫穿該第二介電層而到達該第一導電圖案。
  6. 一種封裝結構之形成方法，包括：形成一封膠體，側向封膠一晶粒且位於該晶粒之一主動表面上，該主動表面包括一電性焊墊；形成一第一開口，貫穿該封膠體而到達該電性焊墊；以及於該封膠體上形成一第一導電圖案，該第一導電圖案包括位於該第一開口內到達該電性焊墊之一第一介層連接窗。
  7. 如申請專利範圍第6項所述之封裝結構之形成方法，其中在形成該封膠體時，一暫時性支柱位於該電性焊墊上，其中 形成貫穿該封膠體之該第一開口之步驟包括：藉由移除位於該暫時性支柱上之該封膠體，以露出貫穿該封膠體之該暫時性支柱；以及移除該暫時性支柱。
  8. 如申請專利範圍第6項所述之封裝結構之形成方法，更包括於該封膠體上形成一第二介電層，該第一導電圖案位於該第二介電層上，該第一介層連接窗位於一第二開口內，其通過該第一開口內之該第二介電層。
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