TWI529618B - 用於極早分支預測之包含影子快取的單一循環多分支預測 - Google Patents

用於極早分支預測之包含影子快取的單一循環多分支預測 Download PDF

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TWI529618B
TWI529618B TW100133656A TW100133656A TWI529618B TW I529618 B TWI529618 B TW I529618B TW 100133656 A TW100133656 A TW 100133656A TW 100133656 A TW100133656 A TW 100133656A TW I529618 B TWI529618 B TW I529618B
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摩翰麥德 艾伯戴爾拉
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軟體機器公司
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    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
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    • G06F9/3802—Instruction prefetching
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    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
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    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
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    • G06—COMPUTING; CALCULATING OR COUNTING
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Description

用於極早分支預測之包含影子快取的單一循環多分支預測
本發明一般係關於數位電腦系統，尤其係關於選擇包括一指令順序之指令的系統及方法。
改善電腦架構效能是一項困難的工作，已經想到的改善方式有頻率調整(frequency scaling)、單指令多資料(Single Instruction Multiple Data，SIMD)、超長指令字集(Very Long Instruction Word，VLIW)、多緒(multi-threading)與多處理器技術。這些方式主要在於改善程式執行的處理量。許多技術都需要軟體明確並行處理，相較之下，頻率調整改善處理量與延遲，並不需要軟體明確加註並行處理。近來，頻率調整已經達到瓶頸，因此透過頻率調整來改善有困難。如此，除非有大量明確軟體並行處理，否則難以增加處理量。
關於單緒程式執行，程式執行由分支指令控制，其指示該程式控制流程。當分支指令是有條件的或分支目標不直接時，程式指令順序會隨時變動。在這種情況下，基本上要讓處理器的擷取邏輯(fetch logic)找出是否採用分支的條件分支。此致能擷取邏輯產生指令順序(sequence)以追隨分支目標(target)，或產生追隨分支指令本身的指令順序。不過這在擷取階段上存在一個問題，分支本身執行之前並不知道分支的條件的結果(outcome)。
在克服此問題的嘗試當中，先前技術設計已經實施分支預測邏輯，來預測分支的結果。在微處理器的擷取階段上，該預測的結果可讓擷取邏輯預期從哪個地方帶出下一個指令順序。不過問題仍舊存在，因為若在相同循環內要處理一個以上的條件分支，則該擷取階段的邏輯很快會變得非常複雜。原因在於此處理需要依序進行。目前的分支需要先處理，以便知道從何處帶來下一個指令順序。此態樣會導致略過順序中下一個分支。因此擷取階段內處理分支的順序本質，在微處理器的單緒執行速度上加諸效能瓶頸。
本發明的具體實施例實施一種演算法(例如方法與設備)，其致能微處理器之擷取邏輯的並行化(parallelization)以在每個單一循環中處理多個分支。該演算法也根據該單一循環內的分支預測，形成指令的最終順序。
在一個具體實施例內，將本發明實施為一種識別一預測執行路徑之指令的方法。該方法包括存取複數個指令，包括多個分支指令(branch instruction)。針對該等多個分支指令的每一分支指令，產生一個別第一遮罩(mask)，代表若採用該分支時而執行的指令。產生一個別第二遮罩，代表若不採用該分支時而執行的指令。接收一預測輸出(prediction output)，其中包括一個別分支預測(respective branch prediction)，用於該等多個分支指令的每一分支指令。針對該等多個分支指令的每一分支指令，該預測輸出用於從該個別第一和第二遮罩之間選擇一個別結果遮罩(resultant mask)。針對每一分支指令，若預測一之前的分支分開越過(branch over)一後續分支，則使得該後續分支的一結果遮罩無效。在所有結果遮罩上執行一邏輯運算，來產生一最終遮罩(final mask)。從該等複數個指令中，根據該最終遮罩，選擇要執行的指令子集。
上述為總結，因此必須簡單扼要並且省略細節；因此精通技術人士將了解，該總結僅為例示，並不成為任何限制。從下列非限制的詳細說明當中，將了解如同申請專利範圍所單獨定義的本發明之其他態樣、發明特徵以及優點。
雖然本發明已經搭配一個具體實施例來說明，但本發明並不用於限制到此處所公佈的特殊形式。相反地，吾人想要如申請專利範圍內所定義將改變、修改以及同等配置合理包含在本發明的範疇內。
在下列詳細說明當中，許多特定細節，例如特定方法順序、結構、元件以及連接都已經公布。不過吾人要了解，這些與其他特定細節並不需要用於實現本發明的具體實施例。在其它環境中，已知的結構、元件或連接都已經省略或未詳細說明，以避免模糊本說明。
說明書內參考本發明的「一個具體實施例」或「具體實施例」用於表示，與該具體實施例有關連所說明的特定功能、結構或特性包含在本發明的至少一個具體實施例內。出現在整個說明書內許多地方的「在一個具體實施例內」一詞，並不一定全都參照到同一個具體實施例，也不是與其他具體實施例互斥的個別或替代具體實施例。再者，說明可由某些具體實施例展示而其他沒有的許多特徵。同樣，說明可為某些具體實施例所需但是其他具體實施例不需的許多需求。
某些詳細說明部分都以可在電腦記憶體上執行的資料位元上操作之程序、步驟、邏輯區塊、處理以及其他符號表示之方式來呈現。這些說明與代表為精通資料處理技術的人士用來將其工作內容灌輸給其他精通此技術人士的最有效方式。此處的程序、電腦可執行步驟、邏輯區塊、處理等等一般係認為是導致所要結果的有條理的(self-consistent)步驟或指令順序。這些步驟為所需的物理量之物理操縱。通常，雖然非必要，不過這些量採用電腦可讀取儲存媒體並且可以在電腦系統內儲存、傳輸、結合、比較以及操縱的電或磁性信號形式。為了時間上方便起見，原則上因為常用，所以這些信號代表位元、數值、元件、符號、字元、詞彙、數字等等。
不過，吾人應該瞭解，所有這些與類似詞彙都與適當的物理量相關連，並且僅為適用這些量的便利符號。除非特別說明，否則從下列討論中可瞭解，整個說明書的討論運用像是「處理」、「存取」、「寫入」、「儲存」或「複製」等詞表示電腦系統或類似電子計算裝置的動作以及處理，其操縱以及轉換代表電腦系統暫存器、記憶體和其他電腦可讀取媒體內物理(電子)量的資料成為類似代表電腦系統記憶體、暫存器或其他這種資訊儲存、傳輸或顯示裝置內物理量的其他資料。
本發明的具體實施例實施一種演算法(例如方法與設備)，其致能微處理器之擷取邏輯的並行化以在每個單一循環中處理多個分支。該演算法也根據該單一循環內的分支預測，形成指令的最終順序。此工作不需要依序處理該等分支(例如不用以每循環一個分支的速率逐一分支地處理指令順序)就可執行。取而代之是本發明的具體實施例可有每循環多個分支的處理速率，如此啟用大指令擷取與分配頻寬。請注意，個別分支指令的處理在單一循環(cycle)內可能不會完成，不過，處理器硬體可在每個循環內處理多個分支，因此達成每循環多分支的處理量。如此，分支處理速率為每一循環，但是單一循環內並不需要等待時間(latency)。圖1和圖2顯示由本發明具體實施例操作的指令示範順序。接著，圖3顯示根據本發明的一個具體實施例的一處理步驟的總體流程，用於識別並取得(extract)該等指令，其包括具有多個分支之指令順序的執行路徑(execution path)。
圖1顯示由本發明一個具體實施例操作的指令示範順序。如圖1內所示，由圖1的頂端到底部，指令順序100總共包括16個指令。如圖1內所見，順序100包括四個分支指令101-104。
本發明具體實施例的一個目標為在每個單一循環內處理整個指令群組。根據不同的具體實施例，這些指令可包括原生指令(native instruction)(例如微處理器架構的原生指令，例如x86指令、MIPS指令等)。另外，這些指令可包括微程式碼(microcode)。
在一個具體實施例內，在相同單一循環內處理16個指令的整個群組。如稍早所述，指令順序內包括越多分支，則發生並需要處理的組合與可能之結果順序越多。這特性例示於底下圖2內。
圖2顯示根據本發明一個具體實施例之具有個別程式碼區段(code segment)的該順序指令100，用於所例示的每一分支。如上述，指令順序內呈現越多分支，則需要辨明的指令順序組合與可能性越多。此外，分支帶來的可能性越多，則可省略的分支越多。
這例示於圖2內，顯示若採用分支c1時，則發生第一結果順序「1」。如本說明書所提，若程式執行流程移動到一分支的目標，則採用該分支。這由每一分支指令末端上括號內的兩位數所表示，例如分支c1的目標為11，造成省略接下來6個指令，同樣的，分支c2的目標為10，造成省略接下來2個指令，以此類推。
如此，若採用分支c2時，則顯示並發生第二結果順序「2」。若採用分支c3時，則顯示並發生第三結果順序「3」。同樣的，若採用分支c4時，則顯示並發生第四結果順序「4」。
如圖2內所示，來自該等分支的結果順序彼此重疊，這例示其中指令順序內一之前的分支能夠利用跳過後續分支，使得後續分支無效的方式。如此，若採用分支c1，則省略兩個後續分支c2和c3並且使其無效，或無關於指令順序的執行路徑。同樣的，若不採用分支c1而採用分支c2，則將省略後續分支c3並使其無效。
本發明的具體實施例實施一種演算法(例如方法與設備)，其致能微處理器之擷取邏輯的並行化以在每個單一循環中處理多個分支，例如分支c1至c4。該演算法也根據該單一循環內用於c1至c4的分支預測，形成指令的最終順序。此演算法說明於底下圖3內。
圖3顯示根據本發明的一個具體實施例的一處理(process)300的步驟的總體流程，用於識別並取得該等指令，其包括具有多個分支之指令順序的執行路徑。處理300顯示例如微處理器指令擷取模組的示範操作步驟。
處理300開始於步驟301，在此一擷取模組(fetch module)存取包括多個分支指令的複數個指令。如上述，存取一指令順序(instruction sequence)，其中該指令順序包括一些分支指令(例如圖1中順序100的分支c1-c4)。
在步驟302內，針對多個分支指令的每一分支指令，產生個別第一遮罩，此第一遮罩代表若採用該特定分支時而執行的指令。
在步驟303內，針對每一分支指令，產生個別第二遮罩，此第二遮罩代表若不採用該特定分支時而執行的指令。如此在步驟303的結論上，該指令順序內的每一分支都將有兩個遮罩，一個代表若採用該分支時要執行的指令，另一個代表若不採用該分支時要執行的指令。
在步驟304內，該擷取模組接收一分支預測輸出。該分支預測輸出做出預測該指令順序的每一分支之採用或不採用狀態。
在步驟305內，使用該分支預測輸出，以針對該指令順序的每一分支指令而在該第一遮罩與該第二遮罩之間選擇。例如針對已知分支，若該分支預測輸出指示將採用該分支，則將選擇該分支的第一遮罩。若該分支預測輸出指示將不採用該分支，則將選擇該分支的第二遮罩。該分支預測輸出所選的遮罩稱為結果遮罩。
在步驟306內，針對該指令順序的每一分支指令，若預測一之前的分支分開或省略越過一後續分支，則使得該後續分支的一結果遮罩無效。如上述，指令順序內一之前的分支能夠利用略過後續分支，使得後續分支無效。
在步驟307內，在所有結果遮罩上執行一邏輯運算，來產生一最終遮罩。因此，此最終遮罩識別包括指令順序內之執行路徑的指令，其由該順序內該等多個分支的預測結果所決定。
在步驟308內，使用該最終遮罩，以從包括該指令順序的該等複數個指令當中，選擇用於執行的指令子集。如此，由該擷取模組產生一小型執行路徑指令順序(compact execution path instruction sequence)。在一個具體實施例，在每個單一循環內產生此小型執行指令順序。
圖4顯示例示根據本發明的一個具體實施例的一處理操作的流程圖400，用於識別並取得該等指令，其包括具有多個分支之指令順序的執行路徑。
如上述，本發明具體實施例的一個目標為在一個循環內處理整個指令群組。這例示於圖4，其中由一個循環內的該擷取模組處理指令順序100的全部16個指令。識別碼(identifier)401例示其中該擷取模組識別其中每一分支之方式。從指令順序100的頂端開始，標記已經識別的第一分支、標記已經識別的第二分支，以此類推，以將該順序減少到只有該等條件運算(conditional operation)(例如該等分支)。原始指令(例如分支指令以外的指令)則簡單標記為零。
圖4也例示追蹤該等分支區段的分支區段表(branch segment table)402。在該分支區段表的左手邊，每一對應的分支都具有一個區段，開頭為該順序內分支的編號，結尾為該後續分支的編號。如此如圖4內所示，分支c1具有第一區段5-7，其為不採用該分支時將執行的指令。同樣的在右手邊上，分支c1具有第二區段11-14，其為採用該分支時將執行的指令。原始指令用x標記。
如上述，針對多個分支指令的每一分支指令，產生個別第一遮罩，此第一遮罩代表若採用該特定分支時而執行的指令。同樣的，針對每一分支指令，產生個別第二遮罩，此第二遮罩代表若不採用該特定分支時而執行的指令。如此在步驟303的結論上，該指令順序內的每一分支都將有兩個遮罩，一個代表若採用該分支時要執行的指令，另一個代表若不採用該分支時要執行的指令。在一具體實施例內，這些遮罩包括位元的集合。
分支預測元件403試驗該指令區段內的分支，並且預測是否每一分支將採用「T」或不將採用「NT」。在本具體實施例內，由該擷取模組的一比較與省略邏輯元件(compare and skip logic component)404處理分支預測元件403的輸出。透過比較與省略模組404的操作，使用該分支預測輸出，在該指令順序的每一分支指令之該第一遮罩或該第二遮罩之間選擇。
圖4顯示結果遮罩410。如上述，針對已知分支，若該分支預測輸出指示將採用該分支，則將選擇該分支的第一遮罩。若該分支預測輸出指示將不採用該分支，則將選擇該分支的第二遮罩。該分支預測輸出所選的該遮罩顯示為結果遮罩410。
之前的分支可使結果遮罩無效。這顯示於圖4內，其中結果遮罩410的頂端顯示其個別狀態，有效並採用為「VT」或無效為「NV」。如上述，針對該指令順序的每一分支指令，若預測一之前的分支分開或省略越過一後續分支，則使得該後續分支的一結果遮罩無效。同樣的，指令順序內一之前的分支能夠利用略過後續分支，使得後續分支無效。如此，即使該分支預測輸出可預測採用「T」的一結果遮罩，不過一之前的分支還是可使該結果遮罩無效。這顯示於圖4內，其中即使預測採用分支c3，但是比較與省略邏輯404還是使c3的結果遮罩無效。在圖4具體實施例內，遮罩無效導致該遮罩的所有順序位置(例如1至16)都填入1。
圖4也顯示最終遮罩420的該輸出指令順序。如上述，該擷取模組在所有結果遮罩上執行一邏輯運算(例如一邏輯AND運算)，來產生一最終遮罩。因此，此最終遮罩識別包括指令順序內之執行路徑的指令，其由該順序內該等多個分支的預測結果所決定。在一個具體實施例內，該邏輯運算只在有效結果遮罩上執行。在其他具體實施例內，該邏輯運算在所有遮罩上執行，其中該無效遮罩全部填入1。使用最終遮罩420，以從包括該指令順序的該等複數個指令當中，選擇用於執行的指令子集。如此，由該擷取模組產生一小型執行路徑指令順序。在一個具體實施例，在每個單一循環內產生此小型執行指令順序。
請注意，本發明具體實施例的演算法根據也在該單一循環內的分支預測，形成指令的最終順序。此工作不需要依序處理該等分支就可執行(例如不用以每循環一個分支的速率逐一處理指令順序)。
在一個具體實施例內，利用將識別該分支在該指令順序內之位置的位元關聯於每一分支，來幫助該演算法。運用這些位元，每一分支都關聯於2區段(例如分支區段表402)。如上述，該第一區段為為該指令的順序，接著分支到下一個分支。該第二區段為為該指令的順序，從該分支的目標開始直到下一個分支。與該分支目標一起的該分支識別位元(例如由與目前分支位置的偏差所表示)用於建立這些區段。同時，所有分支都在該分支預測表內平行受到查找，以便找出其預測；這些分支預測類似於一般單一分支預測。
另請注意，在一個具體實施例內，每一分支位置都同時與之前的分支目標比較，以找出此分支是在該之前分支的領域之內或之外。然後，利用跳超過(jump beyond)該分支位置的先前有效分支之目標，決定是否省略該分支。此資訊由該分支預測的平行查找(parallel look up)賦予資格，以找出省略過哪個分支，如此其順序格式不包含在該指令的最終順序內。藉由使用該分支預測來產生這些分支的結果遮罩，選擇對每一分支有效的預測區段(例如並未因為之前的有效分支省略它而被省略)，而由組裝指令相關區段以形成該最終指令順序，如圖4所示。
圖5顯示根據本發明一個具體實施例的一遠分支快取(far branch cache)501以及一遠跳躍目標指令快取(far jump target instruction cache)502。圖5也顯示一遠分支預測器(far branch predicto)503。
圖5具體實施例顯示整體微處理器管線(microprocessor pipeline)的最佳化，其中2條以上的快取線(cache line)呈現給該擷取模組(例如該指令順序消除模糊邏輯(instruction sequence disambiguation logic))。在圖5的具體實施例內，首先從多條快取線集中該等指令。該擷取從指向指令順序的開始快取線開始，圖5內顯示為快取線X。該開始快取線與下一個後續快取線，就是快取線X+1(或以上)，都從快取結構501當中擷取。若該指令順序具有一遠跳躍超出下一個快取線，則遠跳躍目標指令快取結構502用於將一遠目標快取線(far target cache line)(例如快取線Y)取代該下一個快取線(例如快取線X+1)。若來自遠分支預測器(far branch predictor)503的預測指出將採用該遠目標快取線，則選擇該遠目標快取線指令順序。否則，該擷取模組忽略該遠目標快取線Y。
在其他具體實施例內，並非將整個快取線都儲存在該快取結構內，部分快取線可連結(concatenate)在一起並且儲存在該快取結構內。在一個具體實施例內，部分快取線在分支邊界上連結在一起，以形成全新快取線，可用來改善有效指令順序的密度。為了啟用此功能，分支預測資訊與該等快取線儲存在一起，以陳述部分該等快取線如何連結在一起，如此當實際分支結果已知時可確認那些預測。另外可修改或新增遠分支，以跳躍至考量新連結快取線部分的新目標，藉此改善傳入指令的前端處理量(front end throughput)。
在一個具體實施例內，這可靠2個階段完成。第一階段從快取結構中擷取多條快取線。然後將選取的快取線呈現給指令順序組裝器(instruction sequence assembler)，其根據動態分支預測(dynamic branch prediction)釐清(disambiguate)分支並且組裝最終指令順序。指令順序緩衝結構(instruction sequence buffer structure)位於指令順序消除模糊邏輯的輸出上。該指令順序緩衝功能為到下一個管線階段的緩衝，並且也選擇性儲存特定指令順序供未來使用。該指令順序緩衝器可儲存經常預測順序(當分支造成該順序的預測相當準確時)或經常失預測順序(當分支造成該順序的的預測時常失準時)的最終組裝區段。
此指令順序緩衝器將改善頻寬並減少前端的指令擷取模組延遲，因為這些順序都儲存在該緩衝器內，不需要使用分支預測表與遮罩進行前述的指令順序處理。
圖6顯示根據本發明一個具體實施例的示範的微處理器管線600的圖式。微處理器管線600包含一擷取模組601，實施用於識別並擷取包括執行之指令的處理功能，如上述。在圖6的具體實施例內，該擷取模組接著一解碼模組(decode module)602、一分配模組(allocation module)603、一派遣模組(dispatch module)604、一執行模組(execution module)605以及一除役模組(retirement module)606。請注意，微處理器管線600只是實施上述本發明具體實施例功能性的一個管線範例，精通技術人士應該了解，可實施包含上述解碼模組功能性的其他微處理器管線。
在上面的說明中，為了解釋而參考特定具體實施例做說明。不過，上面例示的討論並非用於專屬或限制本發明於所說明的形式中。許多修改與變化都可以上述為依據。具體實施例經過選擇與說明來最佳闡述本發明原理及其實際應用，並且讓其他精通此技術的人士最有效利用本發明及多種具體實施例，這些具體實施例可經多種修正以適合所考慮的特定用途。
100．．．指令順序
101-104．．．分支指令
300．．．處理
400．．．流程圖
401．．．識別碼
402．．．分支區段表
403．．．分支預測元件
404．．．比較與省略邏輯元件
404．．．比較與省略模組
410．．．結果遮罩
420．．．最終遮罩
501．．．遠分支快取
502．．．遠跳躍目標指令快取
503．．．遠分支預測器
600．．．微處理器管線
601．．．擷取模組
602．．．解碼模組
603．．．分配模組
604．．．派遣模組
605．．．執行模組
606．．．除役模組
在附圖圖號中本發明藉由範例進行說明並且不受其限制，以及其中相同的參考編號指示相同的元件。
圖1顯示由本發明一個具體實施例示範的操作的指令順序。
圖2顯示根據本發明一個具體實施例之具有個別程式碼區段的該順序指令，用於所例示的每一分支。
圖3顯示根據本發明的一個具體實施例的一處理的步驟的總體流程，用於識別並取得該等指令，其包括具有多個分支之指令順序的執行路徑。
圖4顯示例示根據本發明的一個具體實施例的一處理操作的流程圖，用於識別並取得該等指令，其包括具有多個分支之指令順序的執行路徑。
圖5顯示根據本發明一個具體實施例的一遠分支快取以及一遠跳躍目標指令快取。
圖6顯示根據本發明一個具體實施例的示範的微處理器管線的圖式。
300．．．處理

Claims (26)

  1. 一種識別指令的方法，該方法包括：存取複數個指令，這些指令包括多個分支指令；針對該等多個分支指令的每一分支指令，產生一個別第一遮罩，代表採用該分支時而執行的指令，以及一個別第二遮罩，代表不採用該分支時而執行的指令；接收一預測輸出，其包括一個別分支預測，用於該等多個分支指令的每一分支指令；針對該等多個分支指令的每一分支指令，該預測輸出用於從該個別第一和第二遮罩之間選擇一個別結果遮罩；針對每一分支指令，若預測一之前的分支分開越過一後續分支，則使得該後續分支的一結果遮罩無效；在所有結果遮罩上執行一邏輯運算，來產生一最終遮罩；以及從該等複數個指令中，根據該最終遮罩，選擇要執行的一指令子集。
  2. 如申請專利範圍第1項之方法，其中選擇該指令子集是在存取該等複數個指令的一時脈循環(clock cycle)內執行。
  3. 如申請專利範圍第1項之方法，另包括供應該指令子集至執行單元來執行。
  4. 如申請專利範圍第1項之方法，其中接收該預測輸出包括接收來自一分支預測單元(branch prediction unit)的該預測輸出。
  5. 如申請專利範圍第1項之方法，其中減少該指令子集的分支指令以進行條件運算。
  6. 如申請專利範圍第1項之方法，其中該邏輯運算為一AND運算。
  7. 如申請專利範圍第6項之方法，其中所有個別第二遮罩包含所有集合位元。
  8. 一種識別指令的系統，該系統包括：一擷取模組，其存取複數個指令，該等指令包括多個分支指令；針對該等多個分支指令的每一分支指令，該擷取模組產生一個別第一遮罩，代表採用該分支時執行的指令，以及一個別第二遮罩，代表不採用該分支時執行的指令；該擷取模組接收一預測輸出，其包括一個別分支預測，用於該等多個分支指令的每一分支指令；針對該等多個分支指令的每一分支指令，該擷取模組使用該預測輸出，從該個別第一和第二遮罩之間選擇一個別結果遮罩；針對每一分支指令，若預測一之前的分支分開越過一後續分支，則該擷取模組使得該後續分支的一結果遮罩無效；由該擷取模組在所有結果遮罩上執行一邏輯運算，來產生一最終遮罩；以及從該等複數個指令中，該擷取模組根據該最終遮罩，選擇要執行的一指令子集。
  9. 如申請專利範圍第8項之系統，其中選擇該指令子集是在存取該等複數個指令的一時脈循環內執行。
  10. 如申請專利範圍第8項之系統，另包括供應該指令子集至執行單元來執行。
  11. 如申請專利範圍第8項之系統，其中該接收該預測輸出包括接收來自一分支預測單元的該預測輸出。
  12. 如申請專利範圍第8項之系統，其中減少該指令子集的分支指令以進行條件運算。
  13. 如申請專利範圍第8項之系統，其中該邏輯運算為一AND運算。
  14. 如申請專利範圍第13項之系統，其中所有個別第二遮罩包含所有集合位元。
  15. 一種實施識別指令方法的微處理器，該微處理器包括：一微處理器管線；一擷取模組，其包含於該微處理器管線內，其中該擷取模組：存取複數個指令，該等指令包括多個分支指令；針對該等多個分支指令的每一分支指令，產生一個別第一遮罩，代表採用該分支時執行的指令，以及一個別第二遮罩，代表不採用該分支時執行的指令；接收一預測輸出，其中包括一個別分支預測，用於該等多個分支指令的每一分支指令；針對該等多個分支指令的每一分支指令，使用該預測輸出而從該個別第一和第二遮罩之間選擇一個別結果遮罩；針對每一分支指令，若預測一之前的分支分開越過一後續分支，則使得該後續分支的一結果遮罩無效；在所有結果遮罩上執行一邏輯運算，來產生一最終遮罩；以及從該等複數個指令中，根據該最終遮罩，選擇要執行的一指令子集。
  16. 如申請專利範圍第15項之微處理器，其中選擇該指令子集是在該存取該等複數個指令的一時脈循環內執行。
  17. 如申請專利範圍第15項之微處理器，另包括供應該指令子集至執行單元來執行。
  18. 如申請專利範圍第15項之微處理器，其中該接收該預測輸出包括接收來自一分支預測單元的該預測輸出。
  19. 如申請專利範圍第15項之微處理器，其中減少該指令子集的分支指令以進行條件運算。
  20. 如申請專利範圍第15項之微處理器，其中該邏輯運算為一AND運算。
  21. 如申請專利範圍第20項之微處理器，其中所有個別第二遮罩包含所有集合位元。
  22. 一種提供複數個快取線給一擷取模組之方法，該方法包括：從複數個快取線收集指令，其中該等複數個快取線之一者包括一指令順序的一開始快取線、該等複數個快取線之一者包括一後續快取線接著該開始快取線，並且該等複數個快取線之一者包括一遠目標快取線；在接收該執行順序的執行流(execution flow)將從該開始快取線前往該後續快取線的一預測後，忽略該遠目標快取線，讓執行流包括該後續快取線；以及在接收該執行順序的執行流將從該開始快取線前往該遠目標快取線的一預測，忽略該後續快取線，讓執行流包括該遠目標快取線。
  23. 如申請專利範圍第22項之方法，其中從一第一指令快取存取該開始快取線與該後續快取線，並且其中從一第二指令快取存取該遠目標快取線。
  24. 如申請專利範圍第22項之方法，其中該開始快取線、該後續快取線以及該遠目標快取線都呈現至一指令順序組裝器，其使用動態分支預測釐清該指令順序的該等分支。
  25. 如申請專利範圍第24項之方法，其中使用一遠分支預測器，產生一分支預測來控制執行流是前往該後續快取線或該遠目標快取線。
  26. 如申請專利範圍第22項之方法，其中部分快取線連結在一起並儲存在該快取結構內，並且其中該部分快取線連結在分支邊界上，來形成一全新快取線。
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