TWI524528B - ＦｉｎＦＥＴ元件與其形成方法 - Google Patents

ＦｉｎＦＥＴ元件與其形成方法 Download PDF

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TWI524528B
TWI524528B TW102140982A TW102140982A TWI524528B TW I524528 B TWI524528 B TW I524528B TW 102140982 A TW102140982 A TW 102140982A TW 102140982 A TW102140982 A TW 102140982A TW I524528 B TWI524528 B TW I524528B
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Taiwan
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gate
channel region
forming
dielectric layer
region
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TW102140982A
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TW201421693A (zh
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黃玉蓮
蔡明桓
萬幸仁
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台灣積體電路製造股份有限公司
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    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Thin Film Transistor (AREA)

Description

FinFET元件與其形成方法
本發明係關於半導體元件，更特別關於鰭狀場效電晶體(FinFET)與其形成方法。
依據Moore定律縮小半導體元件尺寸，其成本與複雜度引發新方法以改良半導體元件特性。為了依Moore定律持續縮小下一代的微處理器設計，可採用新的閘極材料如高介電常數之閘極介電層與金屬閘極以降低元件漏電流，採用有效閘極區域大於同樣尺寸之平面元件的FinFET元件、或者採用應力誘發通道以增加電荷載子遷移率。
本發明一實施例提供一種FinFET元件的形成方法，包括：形成半導體帶於半導體基板上，其中半導體帶位於介電層中；形成閘極於半導體帶與介電層上；形成第一凹陷與第二凹陷於半導體帶中，其中第一凹陷與第二凹陷位於閘極之相反兩側上；形成源極區於第一凹陷中，並形成汲極區於第二凹陷中；以及使介電層凹陷化，其中半導體帶之第一部份延伸超過介電層的上表面，且第一部份形成半導體鰭狀物。
本發明一實施例提供一種FinFET元件的形成方法，包括：形成半導體帶於半導體基板上，其中半導體帶位於 介電層中；形成第一虛置閘極於半導體帶與介電層上；形成多個第一閘極間隔物於第一虛置閘極的相反兩側上；蝕刻形成多個凹陷於半導體帶中；磊晶成長第一源極區於凹陷之一者中，與第一汲極區於凹陷之另一者中；移除第一虛置閘極以露出半導體帶中的第一通道區；移除半導體帶中的第一通道區；形成第一取代通道區於半導體帶中；蝕刻介電層，其中第一取代通道區延伸超過介電層之上表面，且其中部份半導體帶延伸超過介電層之上表面以形成半導體鰭狀物；以及形成第一主動閘極於第一取代通道區上。
本發明一實施例提供一種FinFET元件，包括：介電層位於半導體基板上；半導體鰭狀物自半導體基板向上延伸，其中半導體鰭狀物位於介電層中；第一源極區與第一汲極區位於半導體鰭狀物中，其中第一源極區與第一汲極區包括第一磊晶材料，其中第一源極區與第一汲極區之側壁與半導體基板之上表面實質上正交；第一通道區位於半導體鰭狀物中，其中第一通道區於水平方向位於第一源極區與第一汲極區中；以及第一閘極結構位於半導體鰭狀物上，其中第一閘極結構位於第一通道區上。
A-A、B-B、C-C‧‧‧切線
20‧‧‧半導體基板
22‧‧‧介電層
24‧‧‧半導體帶
26、44、86‧‧‧閘極介電層
28‧‧‧汲極區
29‧‧‧鰭狀物
30‧‧‧源極區
31‧‧‧間隔物襯墊
32、46、88‧‧‧閘極
34‧‧‧閘極間隔物
36‧‧‧凹陷
37‧‧‧虛置閘極介電層
38‧‧‧虛置閘極
40‧‧‧ILD
42、48A、48B、68、70、72、83‧‧‧開口
50、74、84‧‧‧取代通道區
60、76‧‧‧ESL
62、78‧‧‧硬遮罩層
64、80‧‧‧BARC層
66、82‧‧‧光阻
100、150、200‧‧‧FinFET元件
300‧‧‧NMOS FinFET
400‧‧‧PMOS FinFET
第1圖係本發明一實施例中，FinFET元件之透視圖；第2A-5A、2B-5B圖係本發明一實施例中，鰭狀物後製的FinFET元件之製程剖視圖；第6A-10A、6B-10B、6C-10C圖係本發明另一實施例中， 鰭狀物後製與閘極後製的的FinFET元件之製程剖視圖；第11A-16A、11B-16B、11C-16C圖係本發明另一實施例中，鰭狀物後製、閘極後製、與通道取代的FinFET元件之製程剖視圖；以及第17至31圖係本發明另一實施例中，PMOS與NMOS、鰭狀物後製、閘極後製、與通道取代的FinFET元件之製程剖視圖。
下述實施例之附圖將配合標號說明，而圖式中儘可能以相同標號標示類似部份。在圖式中，可能會誇大形狀與厚度以方便清楚說明。下述說明將特別描述本發明中的方法與裝置之單元。可以理解的是，未特別顯示或描述的單元屬本技術領域中具有通常知識者所熟知的範圍。在本發明之教示下，本技術領域中具有通常知識者自可輕易地完成多種變化與改良。
在說明書中，「一實施例」指的是至少一實施例所包含的特定結構或特徵。如此一來，在不同段落中提到的「一實施例」不必然為相同實施例。此外，特定結構與特性可以任何適當的方式結合於一或多個實施例中。可以理解的是，下述圖式僅用以舉例而未以比例繪製。
實施例係用以說明特定內容如鰭狀物後製的FinFET元件。然而其他實施例可應用於平面元件，如同應用於鰭狀物元件。
第1圖係FinFET元件100之透視圖。FinFET元件100包含多個半導體帶24與介電層22於半導體基板20上，且介電層 22圍繞半導體帶24。每一半導體帶24可具有超出介電層22上表面的鰭狀物29。每一鰭狀物29可具有汲極區28、源極區30、與兩者之間的通道區(未圖示)。閘極32可位於鰭狀物29之通道區(未圖示)上。雖然第1圖中的FinFET元件100具有四個鰭狀物29與單一閘極32，但其他實施例之鰭狀物29的數目可少於或多於四個，而閘極32的數目可多於一個。
第2A至5B圖係本發明一實施例中，鰭狀物後製的FinFET 100之製程剖視圖。凡是A系列的圖(比如第2A圖)均為沿著A-A切線的剖視圖，而B系列的圖(比如第2B圖)均為沿著B-B切線的剖視圖。
半導體基板20可為掺雜或未掺雜之基體矽，或絕緣層上矽(SOI)基板之主動層。一般而言，SOI基板包含半導體材料層如矽、鍺、矽鍺合金、SOI、絕緣層上矽鍺合金(SGOI)、或上述之組合。其他適用的基板還包括多層基板、組成漸變基板、或混合定向基板。
半導體基板20可包含主動元件(未圖示於第2B圖)。本技術領域中具有通常知識者應可了解，多種元件包含電晶體、電容、電阻、類似物、或上述之組合可用以滿足FinFET元件100其設計之結構與功能需求。上述元件的形成方法可為任何合適方法。鰭狀物29可電性耦合至主動元件與被動元件。雖然圖式中只有部份的半導體基板20，但足以完整說明實施例。
在一實施例中，半導體帶24之形成方法可為圖案化半導體基板20。圖案化製程可包含沉積遮罩材料(未圖示)如 光阻或氧化矽於半導體基板20上。接著圖案化遮罩材料，再依遮罩材料之圖案蝕刻半導體基板20。最終結構包含多個半導體帶24形成於半導體基板20上。每一半導體帶24之側壁實質上正交於半導體基板20的上表面。在某些實施例中，半導體基板20被蝕刻特定深度，即半導體帶24之高度介於約10nm至約500nm之間。半導體帶24之寬度介於約5nm至50nm之間。半導體帶24之長度介於約0.01μm至10μm之間。在另一實施例中，半導體帶24可自半導體基板20之上表面磊晶成長，以形成於半導體基板20上的圖案化層(如介電層22)中的溝槽與開口中。由於此製程已熟知於本技術領域中具有通常知識者，在此不贅述。
半導體帶24可為半導體材料如矽、鍺、矽鍺合金、或類似物。在一實施例中，半導體帶24為矽。接著可經由佈植製程，可將p型或n型雜質掺入半導體帶24中。
介電層22可毯覆性地沉積於FinFET元件100上。介電層22可由一或多種合適的介電材料組成，比如氧化矽、氮化矽、低介電常數之介電材料如掺雜碳之氧化物、超低介電常數之介電材料如孔洞狀掺雜碳之氧化矽、高分子如聚亞醯胺、上述之組合、或類似物。介電常數22之沉積製程可為化學氣相沉積(CVD)、旋塗玻璃製程、或其他合適製程。
在沉積介電層22後平坦化介電層22，使介電層22的上表面與半導體帶24上之硬遮罩層(未圖示於第2A與2B圖)的上表面等高。硬遮罩層可由含磷酸或類似物之蝕刻製程移除。介電層22之平坦化可由多種方式完成。在一實施例中，平坦化製程為化學機械研磨(CMP)，使介電層與磨料反應後將其 磨除。此製程可持續到露出半導體帶24的頂部。在另一實施例中，可採用稀釋氫氟酸(DHF)或氣態氫氟酸(VHF)處理介電層22一段適當時間，以薄化介電層22。
在平坦化介電層22後，可形成閘極32於半導體帶24與介電層22上。閘極32包含閘極介電層26與閘極間隔物34。閘極介電層26之形成方法可為熱氧化法、CVD、濺鍍、或任何其他用以形成閘極介電層的已知方法。在其他實施例中，閘極介電層26包含高介電常數(大於3.9)之介電材料，比如氮化矽、氮氧化矽、金屬氧化物如氧化鉿(HfO2)、氧化鉿鋯(HfZrOx)、氧化鉿矽(HfSiOx)、氧化鉿鈦(HfTiOx)、氧化鉿鋁(HfAlOx)、類似物、上述之組合、或上述之多層結構。
閘極層(未圖示)可形成於閘極介電層26上。閘極層可為導電材料，並擇自下述群組：多晶矽、多晶矽鍺、金屬氮化物、金屬矽化物、金屬氧化物、與金屬。閘極層之沉積方法可為CVD、濺鍍、或其他用以沉積導電材料的已知技術。閘極層的上表面通常不平整，因此在圖案化或蝕刻閘極層前可先進行平坦化製程。離子可視情況掺雜至閘極層中，其掺雜方法可為離子佈植技術。接著可圖案化閘極層與閘極介電層以形成閘極32。閘極之圖案化製程包含沉積遮罩材料(未圖示)如光阻或氧化矽於閘極層上。接著圖案化遮罩材料，並依據遮罩材料之圖案蝕刻閘極層。
閘極間隔物34可形成於閘極32的相反兩側上。一般而言，閘極間隔物34之形成方法為毯覆性地沉積間隔物層(未圖示)於之前形成的結構上。在一實施例中，閘極間隔物34 可包含間隔物襯墊31，其組成可為氮化矽、碳化矽、矽鍺合金、氮氧化物、氧化物、上述之組合、或類似物。間隔物層可包含氮化矽、氮氧化物、碳化矽、氮氧化矽、氧化物、上述之組合、或類似物，其形成方法可為CVD、電漿增強式CVD(PECVD)、低壓CVD(LPCVD)、原子層沉積(ALD)、濺鍍、或其他本技術領域中具有通常知識者所知的方法。接著圖案化閘極間隔物層以形成閘極間隔物34，其圖案化方法可為非等向蝕刻，可自結構的水平表面移除間隔物層。
如第3A與3B圖所示，進行應力源汲極(SSD)蝕刻步驟，以蝕刻部份半導體帶24並形成凹陷36於半導體帶24中。SSD蝕刻可選擇性蝕刻半導體帶24，而不蝕刻介電層22、閘極32、與閘極間隔物34。在一實施例中，蝕刻形成之凹陷36深度介於約5nm至約25nm之間。SSD蝕刻步驟可由多種方式進行。在一實施例中，SSD蝕刻步驟可為搭配電漿源與蝕刻氣體的乾式化學蝕刻。電漿源可為誘導耦合電漿(ICP)蝕刻、變壓器耦合電漿(TCP)蝕刻、電子迴旋共振(ECR)蝕刻、反應性離子蝕刻(RIE)、或類似物。蝕刻氣體可為氟、氯、溴、上述之組合、或類似物。在另一實施例中，SSD蝕刻步驟可為濕式化學蝕刻，比如過氧化銨(APM)之混合物、氨水、氫氧化四甲基銨、上述之組合、或類似物。在又一實施例中，SSD蝕刻步驟可為乾式化學蝕刻與濕式化學蝕刻之組合。
在形成凹陷36後，可形成源極區30與汲極區28於凹陷36中，如第4A與4B圖所示。源極區30與汲極區28之形成方法可為磊晶成長矽鍺合金、矽、磷化矽、上述之組合、或類 似物於凹陷36中。矽組成的蓋層可視情況形成於源極區30與汲極區28上。磊晶成長使源極區30、汲極區28、與半導體帶24具有相同的的結晶方向。源極區30與汲極區28之成長實質上受限於介電層22。如第4B圖所示，汲極區28之側壁實質上正交於半導體基板20之上表面，而汲極區28之上表面實質上平行於半導體基板20之上表面。在一實施例中，汲極區28之上表面與介電層22之上表面實質上共平面。在另一實施例中，汲極區28之上表面可低於或高於介電層22之上表面。雖然第4B圖只有汲極區28，但閘極32其相反兩側上的汲極區28與源極區30具有類似結構，因此關於汲極區28之敘述亦可套用於源極區30。
在PMOS的實施例中，源極區30與汲極區28可為矽鍺合金(SiGex，x0.1)，且可掺雜硼。在NMOS的實施例中，源極區30與汲極區28可為矽或磷化矽，且可掺雜磷。在上述兩種實施例中，源極區30與汲極區28可包含矽蓋層於其上。
如第5A與5B圖所示，形成鰭狀物29。鰭狀物29之形成方法可為蝕刻或凹陷化圍繞半導體帶24之介電層22。部份半導體帶24係延伸超出介電層22之上表面，以形成鰭狀物29。在一實施例中，鰭狀物29的上表面延伸超出介電層22之上表面的距離為約10nm至約30nm之間。鰭狀物29之形成方法可為化學氧化物反應如CERTAS®蝕刻、SiCoNi蝕刻、DHF處理、上述之組合、或類似方法。
在形成源極區30與汲極區28後再形成鰭狀物29，源極區30與汲極區28將受限於介電層22並具有較佳之形狀控制，進而減少甚至消除源極區30與汲極區28的晶面。如此一 來，可降低後續形成的金屬層與其接觸的源極區30與汲極區28之間的電阻。此外，源極區30與汲極區28上的晶面會使金屬層經由晶面的交界漏電流。
第6A至10C圖係另一實施例中，鰭狀物後製與閘極後製之FinFET元件150的製程剖視圖。凡是A系列的圖(比如第6A圖)均為沿著第1圖中A-A切線的剖視圖，B系列的圖(比如第6B圖)均為沿著第1圖中B-B切線的剖視圖，而C系列的圖(比如第6C圖)均為沿著第1圖中C-C切線的剖視圖。下述內容中與前述實施例重疊的部份將不贅述。
第6A至6C圖中的FinFET元件150與前述第4A至4B圖中的FinFET元件100類似，差異在於FinFET元件150具有虛置閘極38與其下方的虛置閘極介電層37。如此一來，上述圖式中的製程與前述之第2A至3B圖中的製程類似，在此不贅述。虛置閘極介電層37與第2A至2B圖中的閘極介電層26之材料類似，但虛置閘極介電層亦可採用任何其他合適材料。在一實施例中，虛置閘極38之材料可與前述之閘極32之材料類似。虛置閘極38亦可為氮化鈦、氮化鉭、上述之組合、或類似物形成於虛置閘極介電層37上，再形成一多晶矽於其上。
如第7A至7C圖所示，蝕刻停止層(ESL，未圖示)與ILD(層間介電層)40形成於半導體基板20、虛置閘極38、間隔物襯墊31、閘極間隔物34、源極區30、與汲極區28上。ESL可順應性地沉積於半導體基板20上的構件上。在一實施例中，ESL為氮化矽、氧化矽、類似物、或上述之組合，其形成方法可為PECVD、LPCVD、ALD、類似方法、或上述之組合。
ILD 40可形成於ESL上。在一實施例中，ILD 40可為氧化矽、氮化矽、類似物、或上述之組合。ILD 40之形成方法可為CVD、高密度電漿(HDP)、類似方法、或上述之組合。接著可平坦化ILD 40至露出出虛置閘極38的上表面。在一實施例中，平坦化ILD 40的方法可為CMP以移除部份ILD 40。在其他實施例中，可採用其他平坦化技術如蝕刻。
如第8A至8C圖所示，移除虛置閘極38與虛置閘極介電層37，以形成開口42於源極區30與汲極區28之間的半導體帶24中的通道區上。虛置閘極38之移除方法可為選擇性蝕刻虛置閘極38之材料的乾蝕刻。舉例來說，若虛置閘極38為多晶矽，則乾蝕刻採用三氟化氮(NF3)、六氟化硫(SF6)、氯(Cl2)、溴化氫(HBr)、類似物、或上述之組合，濕蝕刻採用氨水、TMAH、類似物、或上述之組合以移除虛置閘極38。
在移除虛置閘極38後，進行蝕刻製程以凹陷化被移除之虛置閘極38(見第9C圖)下方的介電層22，即形成鰭狀物29。鰭狀物的形成步驟與第5A至5B圖形成鰭狀物之製程類似，在此不贅述。在一實施例中，位於開口42下方之介電層22凹陷(見第9C圖)，而非圍繞源極區30與汲極區28之區域中的介電層22凹陷(見第9B圖)。
如第10A至10C圖所示，形成閘極介電層44與閘極46於開口42中。閘極介電層44與閘極46之材料及形成方法，與第2A至2B圖中的閘極介電層26與閘極32類似，在此不贅述。如第10C圖所示，閘極46及閘極介電層44與鰭狀物29的三側相鄰。
第11A至16C圖係另一實施例中，鰭狀物後製、閘極後製、及通道取代之FinFET元件200之製程剖視圖。凡是A系列的圖(比如第11A圖)均為沿著第1圖中A-A切線的剖視圖，B系列的圖(比如第11B圖)均為沿著第1圖中B-B切線的剖視圖，而C系列的圖(比如第11C圖)均為沿著第1圖中C-C切線的剖視圖。下述內容中與前述實施例重疊的部份將不贅述。
第11A至11C圖中的FinFET元件200，與移除第9A至9C圖中FinFET元件150之虛置閘極與虛置閘極介電層後形成開口42的結構類似。如此一來，與前述第2A至3B圖與第6A至9C圖類似之製程將不贅述。
如第12A至12C圖所示，形成開口48A於半導體帶24中，以移除通道區。開口48A自半導體帶24之上表面往下的深度介於約5nm至約45nm之間。開口48A之形成方法可為蝕刻製程。在一實施例中，蝕刻製程可為搭配電漿源與蝕刻氣體的乾式化學蝕刻。電漿源可為ICP、TCP、ECR、RIE、或類似物。蝕刻氣體可為氟、氯、溴、上述之組合、或類似物。
如第13A至13C圖所示之實施例，進行另一蝕刻以形成V型的開口48B於開口48A下。V型開口的形成方法可為濕式化學蝕刻如氨水、TMAH、類似物、或上述之組合。開口48B之形成步驟係視情況(非必要)進行。取代通道開口可為非V型(比如只有開口48A)，亦可為V型(開口48A加開口48B)。
在形成開口48A(與視情況形成開口48B)後，可形成取代通道區50於開口48A中，如第14A至14C圖所示。取代通道區50可具有應力及/或較高的載子遷移率，進而改善FinFET 元件200的元件效能。取代通道區50可為矽鍺合金、矽、磷化矽、鍺、類似物、或上述之組合磊晶成長於開口48A中，並可視情況形成矽的蓋層於取代通道區50上。取代通道區50之成長實質上受限於介電層22與半導體帶24。如第14A至14C圖所示，取代通道區50之側壁可與半導體基板20之上表面實質上正交，且取代通道區50之上表面可與半導體基板20之上表面實質上平行。在一實施例中，取代通道區50之上表面與介電層22及半導體帶24之上表面實質上共平面。在另一實施例中，取代通道區50之上表面可低於或高於介電層22與半導體帶24之上表面。
在PMOS的實施例中，取代通道區50可為矽鍺合金(SiGex，x0.1)，並可掺雜硼。在NMOS的實施例中，取代通道區50可為矽，並可掺雜磷。在NMOS與PMOS之實施例中，取代通道區50可具有矽的蓋層形成其上。
在形成取代通道區50後，可進行蝕刻以凹陷化開口42下方的介電層22，即形成鰭狀物29如第15A至15C圖所示。上述鰭狀物的形成步驟與前述之第5A至5B圖中鰭狀物的形成步驟相同，在此不贅述。在一實施例中，位於開口下方42的介電層22凹陷(見第15C圖)，但圍繞源極區30與汲極區28之區域中的介電層22不凹陷(見第15B圖)。
如第16A至16C圖所示，形成閘極介電層44與閘極46於開口42中與取代通道區50上。閘極介電層44與閘極46之材料與形成方法與第2A至2B圖中的閘極介電層26與閘極32類似，在此不贅述。如第16C圖所示，閘極46及閘極介電層44與 鰭狀物29的三側相鄰。
在形成源極區30與汲極區28後再形成鰭狀物29，源極區30與汲極區28將受限於介電層22並具有較佳之形狀控制，進而減少甚至消除源極區30與汲極區28的晶面。如此一來，可降低後續形成的金屬層與其接觸的源極區30與汲極區28之間的電阻。此外，源極區30與汲極區28上的晶面會使金屬層經由晶面的交界漏電流。藉由將通道區置換為取代通道區50，可讓通道區具有應力及/或高載子遷移率，進而改善FinFET元件200的效能。
第17至31圖係另一實施例中，PMOS FinFET 400與NMOS FinFET 300沿著半導體帶24(即沿著第1圖之A-A切線)之製程剖視圖。PMOS FinFET 400與NMOS FinFET 300均為鰭狀物後製、閘極後製、及通道取代之元件。下述內容中與前述實施例重疊的部份將不贅述。
如第17圖所示，NMOS FinFET 300與PMOS FET 400各自包含源極區30與汲極區28。源極區30與汲極區28係形成於半導體帶24中，而ILD 40係形成於半導體帶24與虛置閘極38上。
如第18圖所示，ESL 60係形成於ILD 40與虛置閘極38上，而硬遮罩層62係形成於ESL 60上。ESL 60可為氧化物、氮化物、類似物、或上述之組合。硬遮罩層62可為氮化矽、氮氧化矽、氧化矽、類似物、或上述之組合。
如第19圖所示，BARC層(底部抗反射塗層)64係形成於硬遮罩62上。BARC層64可避免後述之光微影製程的射線 反射干擾曝光製程。這些干擾會增加光微影製程的關鍵尺寸。BARC層64之形成方法可為CVD、類似方法、或上述之組合。可沉積光阻66於BARC層64上，接著圖案化光阻66。在顯影並移除部份光阻66後，可進一步進行蝕刻BARC層64，以露出NMOS FinFET 300上的部份硬遮罩層62。如第20圖所示，光阻66之圖案將轉移至硬遮罩層62，並露出NMOS FinFET 300。
在第21圖中，移除NMOS FinFET 300的虛置閘極38與其下方的通道區。第一蝕刻可形成開口68，而第二蝕刻可形成開口70於半導體帶24中。此步驟與前述第12A至12C圖之步驟類似，在此不贅述。如第22圖所示，V型的開口72形成於開口70下。此步驟與前述第13A至13C圖之步驟類似，在此不贅述。
如第23圖所示，NMOS之V型的取代通道區74形成於開口70與72中。此步驟與前述第14A至14C圖之步驟類似，在此不贅述。如第24圖所示，移除PMOS FinFET 400上的硬遮罩層62與ESL 60。此步驟可為蝕刻製程，其蝕刻液包含磷酸、DHF、類似物，或上述之組合。
如第25圖所示，另一ESL 76與硬遮罩層78形成於ILD 40、NMOS FinFET 300、與PMOS FinFET 400上。ESL 76與硬遮罩層78可沉積於開口68中，其中ESL 76與閘極間隔物34相鄰，並位於取代通道區74之上表面上。此步驟與前述第18圖之步驟類似，在此不贅述。如第26圖所示，形成另一BARC層80後，形成並圖案化光阻層82以露出PMOS FinFET 400上的硬遮罩層78。此步驟與前述第19圖之步驟類似，在此不贅述。如 第27圖所示，圖案化硬遮罩層78與ESL 76以露出PMOS FinFET 400上的虛置閘極38。此步驟與第20圖之步驟類似，在此不贅述。
如第28圖所示，移除PMOS FinFET 400上的虛置閘極38與其下的通道區。此步驟與前述第21圖之步驟類似，在此不贅述。如第29圖所示，形成PMOS之取代通道區84於開口83中。此步驟與前述第14A至14C圖之步驟類似，在此不贅述。在一實施例中，PMOS的取代通道區84其深度小於NMOS的取代通道區74(見第29圖)。在另一實施例中，PMOS的取代通道區84之形狀，不同於NMOS的取代通道區74之形狀(見第29圖)。如前述的第14A至14C圖，NMOS的取代通道區74之材料與PMOS的取代通道區84之材料可不同或相同。在另一實施例中，可先形成NMOS FinFET 300後再形成PMOS FinFET 400，或先形成PMOS FinFET 400後再形成NMOS FinFET 300。
如第30圖所示，移除硬遮罩層78與ESL 76。此步驟與前述之第24圖的步驟類似，在此不贅述。在移除硬遮罩層78與ESL後，可讓圍繞半導體帶24之介電層(未圖示)凹陷化，以形成鰭狀物。此步驟與前述之第15A至15C圖的步驟類似，在此不贅述。如第31圖所示，形成閘極介電層86與閘極88於NMOS的取代通道區74與PMOS的取代通道區84上。此步驟與前述之第16A至16C圖的步驟類似，在此不贅述。
一實施例提供FinFET元件的形成方法，包括形成半導體帶於半導體基板上，其中半導體帶位於介電層中，形成閘極於半導體帶與介電層上；以及形成第一凹陷與第二凹陷於 半導體帶中，其中第一凹陷與第二凹陷位於閘極之相反兩側上。此方法亦包括形成源極區於第一凹陷中，並形成汲極區於第二凹陷中；以及使介電層凹陷化，其中半導體帶之第一部份延伸超過介電層的上表面，且第一部份形成半導體鰭狀物。
另一實施例提供FinFET元件的形成方法，包括形成半導體帶於半導體基板上，其中半導體帶位於介電層中，形成第一虛置閘極於半導體帶與介電層上，形成多個第一閘極間隔物於第一虛置閘極的相反兩側上，蝕刻形成多個凹陷於半導體帶中，磊晶成長第一源極區於凹陷之一者中，與第一汲極區於凹陷之另一者中。此方法更包括移除第一虛置閘極以露出半導體帶中的第一通道區，移除半導體帶中的第一通道區，形成第一取代通道區於半導體帶中，蝕刻介電層，其中第一取代通道區延伸超過介電層之上表面，且其中部份半導體帶延伸超過介電層之上表面以形成半導體鰭狀物；以及形成第一主動閘極於第一取代通道區上。
又一實施例提供FinFET元件，包括介電層位於半導體基板上，半導體鰭狀物自半導體基板向上延伸，其中半導體鰭狀物位於介電層中；以及第一源極區與第一汲極區位於半導體鰭狀物中，其中第一源極區與第一汲極區包括第一磊晶材料，其中第一源極區與第一汲極區之側壁與半導體基板之上表面實質上正交。此FinFET元件還包括第一通道區位於半導體鰭狀物中，其中第一通道區於水平方向位於第一源極區與第一汲極區中；以及第一閘極結構位於半導體鰭狀物上，其中第一閘極結構位於第一通道區上。
雖然本發明已以較佳實施例揭露如上，然其並非用以限定本發明，任何熟習此技藝者，在不脫離本發明之精神和範圍內，當可作任意之更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
24‧‧‧半導體帶
86‧‧‧閘極介電層
28‧‧‧汲極區
30‧‧‧源極區
88‧‧‧閘極
40‧‧‧ILD
74、84‧‧‧取代通道區
300‧‧‧NMOS FinFET
400‧‧‧PMOS FinFET

Claims (10)

  1. 一種FinFET元件的形成方法，包括：形成一半導體帶於一半導體基板上，其中該半導體帶位於一介電層中；形成一閘極於該半導體帶與該介電層上；形成一第一凹陷與一第二凹陷於該半導體帶中，其中該第一凹陷與該第二凹陷位於該閘極之相反兩側上；形成一源極區於該第一凹陷中，並形成一汲極區於該第二凹陷中；以及在形成該源極區與該汲極區後使該介電層凹陷化，其中該半導體帶之一第一部份延伸超過該介電層的上表面，且該第一部份形成一半導體鰭狀物。
  2. 如申請專利範圍第1項所述之FinFET元件的形成方法，更包括：在使該介電層凹陷化之步驟前，先形成多個閘極間隔物於該閘極的相反兩側上；沉積一蝕刻停止層於該半導體帶、該閘極、該源極區、該汲極區、與該介電層上；沉積一層間介電層於該蝕刻停止層上；平坦化該層間介電層與該蝕刻停止層，以露出該閘極的上表面；移除該閘極以形成一開口於該些閘極間隔物之間；進行該介電層之凹陷化步驟，其中該介電層係凹陷化至低於該些閘極間隔物之間的該開口；以及 形成一第二閘極於該些閘極間隔物之間的該開口中。
  3. 一種FinFET元件的形成方法，包括：形成一半導體帶於一半導體基板上，其中該半導體帶位於一介電層中；形成一第一虛置閘極於該半導體帶與該介電層上；形成多個第一閘極間隔物於該第一虛置閘極的相反兩側上；蝕刻形成多個凹陷於該半導體帶中；磊晶成長一第一源極區於該些凹陷之一者中，與一第一汲極區於該些凹陷之另一者中；移除該第一虛置閘極以露出該半導體帶中的一第一通道區；移除該半導體帶中的該第一通道區；形成一第一取代通道區於該半導體帶中；蝕刻該介電層，其中該第一取代通道區延伸超過該介電層之上表面，且其中部份該半導體帶延伸超過該介電層之上表面以形成一半導體鰭狀物；以及形成一第一主動閘極於該第一取代通道區上。
  4. 如申請專利範圍第3項所述之FinFET元件的形成方法，更包括：在蝕刻該介電層之步驟前，先形成一第二虛置閘極於該半導體鰭狀物上；形成多個第二閘極間隔物於該第二虛置閘極的相反兩側上； 磊晶成長一第二源極區於該些凹陷中的一者，與一第二汲極區於該些凹陷中的另一者；在形成該第一取代通道區之步驟後，移除該第二虛置閘極以露出該半導體帶中的一第二通道區；移除該半導體帶中的該第二通道區；形成一第二取代通道區於該半導體帶中；進行蝕刻該介電層之步驟，其中該第一取代通道區與該第二取代通道區延伸超過該介電層的上表面；以及形成一第二主動閘極於該第二取代通道區上。
  5. 如申請專利範圍第4項所述之FinFET元件的形成方法，其中該第一取代通道區與該第二取代通道區之材料不同。
  6. 如申請專利範圍第4項所述之FinFET元件的形成方法，其中該第一取代通道區具有一V型下表面延伸至該半導體帶中，且該第二取代通道區具有一實質上平坦的下表面與該半導體基板的上表面實質上平行。
  7. 如申請專利範圍第4項所述之FinFET元件的形成方法，其中該第一取代通道區的深度小於該第二取代通道區的深度。
  8. 如申請專利範圍第4項所述之FInFET元件的形成方法，其中該第一源極區、該第一汲極區、該第一主動閘極、與該第一取代通道區形成一NMOS FinFET元件，而該第二源極區、該第二汲極區、該第二主動閘極、與該第二取代通道區形成一PMOS FinFET元件。
  9. 一種FinFET元件，包括： 一介電層位於一半導體基板上；一半導體鰭狀物自該半導體基板向上延伸，其中該半導體鰭狀物位於該介電層中；一第一源極區與一第一汲極區位於該半導體鰭狀物中，其中該第一源極區與該第一汲極區包括一第一磊晶材料，其中該第一源極區與該第一汲極區之側壁與該半導體基板之上表面實質上正交；一第一通道區位於該半導體鰭狀物中，其中該第一通道區於水平方向位於該第一源極區與該第一汲極區中，其中該源極區與該汲極區之邊緣與該通道區之邊緣實質上一致；以及一第一閘極結構位於該半導體鰭狀物上，其中該第一閘極結構位於該第一通道區上。
  10. 如申請專利範圍第9項所述之FinFET元件，其中該第一通道區包括一第二磊晶材料，且其中與該第一通道區相鄰之該半導體鰭狀物其材料與該半導體基板的材料相同；以及更包括：一第二源極區與一第二汲極區位於該半導體鰭狀物中，其中該第二源極區與該第二汲極區包括一第三磊晶材料，該第三磊晶材料不同於該第一磊晶材料，其中該第二源極區與該第二汲極區之側壁與該半導體基板之上表面實質上正交；一第二通道區位於該半導體鰭狀物中，其中該第二通道區於水平方向位於該第二源極區與該第二汲極區之間，其中 該第二通道區包括一第四磊晶材料，且該第四磊晶材料不同於該第二磊晶材料；以及一第二閘極結構位於該半導體鰭狀物上，其中該第二閘極結構位於該第二通道區上。
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