TWI512809B - 於堆疊裝置製造中用於形成穿底晶圓貫孔的方法 - Google Patents
於堆疊裝置製造中用於形成穿底晶圓貫孔的方法 Download PDFInfo
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- TWI512809B TWI512809B TW099143295A TW99143295A TWI512809B TW I512809 B TWI512809 B TW I512809B TW 099143295 A TW099143295 A TW 099143295A TW 99143295 A TW99143295 A TW 99143295A TW I512809 B TWI512809 B TW I512809B
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Classifications
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- H01L23/12—Mountings, e.g. non-detachable insulating substrates
- H01L23/14—Mountings, e.g. non-detachable insulating substrates characterised by the material or its electrical properties
- H01L23/147—Semiconductor insulating substrates
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- C—CHEMISTRY; METALLURGY
- C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/30625—With simultaneous mechanical treatment, e.g. mechanico-chemical polishing
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/32115—Planarisation
- H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
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- H01L21/486—Via connections through the substrate with or without pins
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- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/6834—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used to protect an active side of a device or wafer
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
- H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
- H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
- H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/10251—Elemental semiconductors, i.e. Group IV
- H01L2924/10253—Silicon [Si]
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Organic Chemistry (AREA)
- Ceramic Engineering (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Description
本專利申請案請求12/14/2009申請的美國臨時專利申請案序號第61/286,099號的權益。
本發明係在穿底晶圓技術的領域中,該穿底晶圓技術用於橫越具有晶片組的晶圓將積體電路晶片複製到堆疊裝置內之前將工作底晶圓背側薄化。穿底晶圓技術的具體實例為該(等)底晶圓為矽晶圓,在該案例中將此技術稱作穿矽貫孔(TSV)技術。
本發明關於利用對於底晶圓材料(例如,矽)的移除具有高移除速率的化學機械平坦化(CMP)引起穿底晶圓技術的改良方法。
三維(3D)積體化能透過晶片,利用不同技術製造,於單一系統中的直接堆疊及交互作用降低系統形狀因子。這些互連件由金屬(例如,銅)釘形態的小又深的穿晶圓貫孔構成。貫孔一般為垂直電氣連接器,其電連接不同的大體上水平的電路層,而且在本發明的案例中,電連接互異的積體電路晶片上的電路。能達到3D堆疊體的技術之一,為上面佈置半導體電路(積體電路)的底晶圓的薄化。半導體晶圓製造典型涉及在矽晶圓表面上的數百個不連續操作,該等操作得進行數周。為了將在此長時間製程期間容易發生的晶圓斷裂及損害減至最少,該等底晶圓典型為300-至800-微米厚。該底晶圓係藉由從該晶圓的背側移除底晶圓材料(例如,在矽晶圓加工的案例中)。這有可能涉及將上面包含積體電路的晶圓前側膠黏於載體晶圓,及接著研磨,及接著該晶圓背側的CMP以達成約10至50微米的厚度,同時將該晶圓暫時膠黏於一載體。此薄化曝露出至少局部穿過(例如,完全穿過)該底晶圓延伸的導電性貫孔。
頃將該研磨步驟視為必須,因為CMP方法,尤其是對於矽,根據歷史在速率方式有極大的限制。然而,晶圓脫層及破壞,以及研磨輪的破壞,已成為矽晶圓背側研磨的不幸,但是不常見的問題。這問題特別大,因為該晶圓表示許多複雜製造及品質控制步驟的最終產物,及因此,這些晶圓的失效表示相當大的經濟損失。此外,研磨輪的破壞導致相當長的生產線停頓時間,以及導致額外的經濟損失。
所需的是能於夠高的速率下拋光底晶圓材料(例如,矽晶圓案例中的矽)以致於可省卻研磨步驟的CMP方法。即使在研磨步驟中磨平背側材料的方法中,高移除速率CMP的應用使製造廠商能指定較少樣必須從晶圓背側磨平的材料。
用於半導體基材的平坦化的化學機械平坦化(化學機械拋光,CMP)現在已廣為熟於此藝之士所知並且已經於許多專利及公開文獻刊物中描述。關於CMP的一些介紹性參考資料如下:由B. L. Mueller及J. S. Steckenrider所著的“Polishing Surfaces for Integrated Circuits”,Chemtech,1998年2月,38至46頁;H. Landish等人,Thin Solids Films,220(1992),1頁;及在Handbook of Semiconductor Manufacturing Technology,編者:Y. Nishi and R. Doering,Marcel Dekker,New York City(2000)中,由G. B. Shinn等人所著的“Chemical-Mechanical Polish”,第15章,415至460頁。
在典型的CMP方法中,使基材(例如,晶圓)與黏貼於壓盤的旋轉拋光墊接觸。在該基材的CMP加工期間將CMP漿料,典型為研磨性及化學反應性混合物,供應於該墊子。在該CMP方法中,旋轉該墊子(固定於該壓盤)及基材,同時將晶圓載體系統或拋光頭靠在該基材施壓(向下作用力)。該漿料基於該向下作用力的效應及該墊子相對於該基材的旋轉運動,藉由與被拋光的基材膜化學及機械交互作用完成該平坦化(拋光)方法。依此方式拋光直到移除該基材想要的膜為止,而且慣常的目標為能有效將該基材平坦化。典型地金屬CMP漿料含有懸浮於氧化的水性介質中的研磨性材料,例如氧化矽或氧化鋁。
矽為底的半導體裝置,例如積體電路(ICs),也名為積體電路晶片,典型包括介電層、金屬線電路、形成記憶體的電晶體開關及計算機特徵,以及電容器及其他構成完整操作電氣處理或記憶裝置的積體電路電氣裝置。在該介電層基材上形成多層電路跡線,經常由鋁或鋁合金或銅形成,的圖案。有許多類型的層可藉由CMP予以拋光,舉例來說,氮化矽、中間層介電質(ILD)例如氧化矽及低-k膜,包括摻碳氧化物;用以連接主動裝置的金屬層,例如鎢、銅、鋁,等等;阻障層材料,例如鈦、氮化鈦、鉭、氮化鉭、貴重金屬,等等。
有一個具體實施例中,本發明為一種製備用於建構包含至少二積體電路晶片的組合件之底矽晶圓的方法,該等積體電路晶片之至少其一係來自該底矽晶圓,該方法包含:
a) 提供具有前及後側的底矽晶圓,其中該前側包含佈置在其上的積體電路及其中該底矽晶圓包含至少一導電貫孔,該至少一導電貫孔包含導電金屬並且從該底矽晶圓的前側至少局部延伸穿過該底矽晶圓;
b) 將上面具有積體電路的底矽晶圓前側黏附於一載體;
c) 使該底矽晶圓背側與拋光墊及第一CMP漿料接觸,該第一CMP漿料包含:
1) 液態載劑;
2) 於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;及
3) 研磨劑;以及
d) 拋光該底矽晶圓的背側直到至少一導電貫孔曝露出來或進一步曝露出來為止,其中利用該第一CMP漿料於至少5,000埃/分的移除速率於6 psi或更低的向下作用力拋光第一底矽晶圓上的矽。
在另一具體實施例中,本發明為一種製備用於建構包含至少二積體電路晶片的組合件之底矽晶圓的方法,該等積體電路晶片之至少其一係來自該底矽晶圓,該方法包含:
a) 提供具有前及後側的底矽晶圓,其中該前側包含佈置在其上的積體電路及其中該底矽晶圓包含至少一導電貫孔,該至少一導電貫孔包含導電金屬並且從該底矽晶圓的前側至少局部延伸穿過該底矽晶圓;
b) 將上面具有積體電路的底矽晶圓前側黏附於一載體;
c) 使該底矽晶圓背側與拋光墊及第一CMP漿料接觸,該第一CMP漿料包含:
1) 液態載劑;
2) 於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;及
3) 研磨劑,其可懸浮於該漿料中,其可黏附於拋光墊,或兼備二者;以及
d) 拋光該底矽晶圓的背側直到至少一導電貫孔曝露出來或進一步曝露出來為止,其中利用該第一CMP漿料於至少5,000埃/分的速率於6 psi或更低的向下作用力拋光該底矽晶圓。
關於適用於含有銅的金屬化區的矽晶圓之TSV技術的特定領域,吾人所欲且必須具有CMP漿料,其將拋光以提供於大約相同速率的銅及矽。據稱此漿料為1:1選擇性漿料,因為這兩個移除速率大約相同。
為了在CMP加工的期間能於適度高的速率移除金屬,例如銅,一般需要有強氧化劑。對於金屬CMP有效的強氧化劑的實例包括:過氧化氫、過碘酸、高硫酸銨及高錳酸鉀。過氧化氫由於安全及環境考量而為較佳的強氧化劑,其中在利用該化合物氧化的期間產生無害的水成為副產物。儘管過氧化氫可用於CMP加工期間的金屬移除,但是如下列比較例舉例說明的,當該過氧化氫以中等及高濃度存在時,其經常都沒有用而且甚至招致在CMP加工期間朝向移除矽的反效果。舉例來說,當銅CMP中使用過氧化氫時,該過氧化氫典型以1重量百分比或更高的濃度存在。當本發明實施例中使用含有1重量百分比過氧化氫的漿料以拋光含有銅區的矽晶圓時,該過氧化氫存在導致該矽移除速率被降至對於穿底晶圓技術的薄化無效的濃度,其中需要相當大的矽移除速率。參見實施例1及2。
驚人且令人意外的是,導致本發明的研究證實含有低濃度的過氧化氫的CMP組合物仍能提供適度的銅移除速率,而且還能提供大約相同的矽移除速率,以致於這些漿料係或能調整為大約1:1銅:矽選擇性的漿料,其尤其有用於TSV技術。該Cu:Si選擇性可在2:1至0.5:1的範圍,或者1.5:1至0.67:1,也或者1.2:1至0.8:1。
此發現的另一重要方面為,如下列實施例中見到的,該銅移除速率可藉由調節氧化物的濃度予以調整,同時對於該矽移除速率僅具有小的效應。本發明的漿料的這個性質使得使用者能微調其加工,而不需要使用不同漿料配方。想要的話此漿料能產生正好1:1選擇性(當經過適當調整時),或此漿料可調整至具有比矽稍高或稍低的銅移除速率。就有可能在CMP加工期間發生的碟化及突出的事及缺陷來看後面的特徵很重要。若想要平的TSV晶圓表面,而且該漿料造成銅釘的稍微凹陷,可稍微降低過氧化氫的濃度以將該速率充分降低而使凹陷不再成為議題。反之亦然,若該釘從該TSV晶圓的表面突出,該氧化劑的濃度可稍微提高以充分提昇該銅速率而使當下該突出能被拋平。
儘管不受理論束縛,但是發明人相信利用含有高於特定濃度(例如,等於或高於0.5重量百分比)的過氧化氫的漿料拋光含矽基材導致該基材表面的矽被該漿料中的過氧化氫所產生的原子(游離)氫實質鈍化。發明人相信特定的強氧化劑,例如過氧化氫,能產生原子氫及過氧羥基。該sp2
混成矽表面具有帶自由基部位的懸鍵(dangling bond),該等懸鍵會與原子氫及其他反應性物種反應。一旦發生此反應,在周遭條件之下,其基本上不可逆,而且能將該矽表面有效鈍化。
驚人的是,發明人發現帶有低濃度過氧化氫(低於0.5重量百分比)的漿料能在CMP加工期間有效提供矽及銅二者的實質移除速率。再者,儘管不受理論束縛,但是發明人相信起始過氧化氫與矽的反應所需的(活化)能量稍微高於起始過氧化氫與銅的反應所需的能量。使用低濃度的過氧化氫將限制能反應的量,而且因為此反應具有較低能量而顯著與銅發生反應。然而,若使用較高濃度的過氧化氫,其中此在此反應期間有實質量的氧化劑存在,所以會同時與矽及銅表面發生反應,而且因此就在前段所述的表面上的矽與低濃度過氧化氫存在時所發生的情況相比更易於鈍化。
如前述說明的,本發明為一種製備用於建構含有二或更多積體電路晶片的組合件之底矽晶圓的方法,該等積體電路晶片之至少其一係來自該底矽晶圓,當該等積體電路晶片組裝起來時,該至少一積體晶片為堆疊裝置。此方法的關鍵方面必然伴隨化學機械平坦化(CMP)的運用以利用底晶圓材料(例如,矽)的高移除速率引起該等底晶圓背側的平坦化。該方法必然伴隨CMP漿料的運用,該CMP漿料包含:
1) 液態載劑;
2) 於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;
3) 研磨劑。
存在於本發明的方法所利用的組合物中的液態載劑可為於周遭條件的任何液體,該液體具有用於CMP漿料中的適合性質。適合的液態載劑為使研磨劑以外的大部分或所有組分溶解者,而且該等液態載劑供給該(等)研磨劑相對安定的分散。適合的液態載劑包括,但不限於,水及水和有機化合物的混合物,該等有機化合物可溶解或分散於水中。如前述說明的,多種不同有機溶劑均可單獨使用或與作為液態載劑的水一起使用。
在本發明中,用低濃度的過氧化氫係為含有金屬化區(例如,銅區)的底晶圓(例如,矽晶圓)的CMP加工時的氧化劑。有一具體實施例中,該過氧化氫的濃度可介於約0.02重量百分比至低於0.5重量百分比。有一具體實施例中,該過氧化氫的濃度可介於低於0.05重量百分比至約0.4重量百分比。有一具體實施例中,該過氧化氫的濃度可介於低於0.05重量百分比至約0.3重量百分比。有一具體實施例中,該過氧化氫的濃度可介於低於0.05重量百分比至約0.25重量百分比。有一具體實施例中,該過氧化氫的濃度可介於約0.15重量百分比至約0.25重量百分比,例如0.20重量百分比。有一具體實施例中,該過氧化氫的濃度可介於約0.10重量百分比至約0.20重量百分比,例如0.15重量百分比。若該過氧化氫的濃度係等於或高於0.5重量百分比,對於適度的CMP加工時間而言在矽晶圓的CMP期間該矽移除速率太低。若該過氧化氫的濃度係低於約0.02重量百分比,對於適度的CMP加工時間而言該銅或其他金屬的移除速率太低。
若適用,本發明中可同時使用標準(未經改質的)研磨劑及經表面改質的研磨劑。適合的未經改質的研磨劑包括,但不限於,氧化矽、氧化鋁、氧化鈦、氧化鋯、氧化鍺、氧化鈰及其共形成的產物及其混合物。本發明中也可使用以無機或有機金屬化合物處理未經改質的研磨劑(例如,氧化矽)所獲得之表面經改質的研磨劑。適用於改質的無機化合物包括:硼酸、鋁酸鈉及鋁酸鉀。適用於改質的有機金屬化合物包括:醋酸鋁、甲酸鋁及丙酸鋁。適合的研磨劑包括,但不限於,膠體產物、發煙產物及其混合物。表面經改質的研磨劑的一些具體實例為以硼酸改質氧化矽以得到經硼表面改質的氧化矽及以鋁酸鈉或鋁酸鉀改質氧化矽以得到經鋁酸表面改質的氧化矽。
本發明所用的較佳研磨劑材料為氧化矽及經表面改質的氧化矽。該氧化矽可為,舉例來說,矽膠、矽煙及其他氧化矽分散體;然而,較佳的氧化矽為矽膠或經表面改質的矽膠。
在大部分具體實施例中,該研磨劑係以該漿料總重量的約0.001重量%至約30重量%的濃度存在於該漿料中。有一具體實施例中,該研磨劑係以該漿料總重量的約0.5重量%至約20重量%的濃度存在於該漿料中。在另一具體實施例中,該研磨劑係以該漿料總重量的約1重量%至約10重量%的濃度存在於該漿料中,而且,在又另一具體實施例中,該研磨劑係以該漿料總重量的約1重量%至約5重量%的濃度存在於該漿料中。
有一具體實施例中,此獨創性漿料含有螯合劑。適合的螯合劑包括,但不限於,胺基酸、乙二胺四醋酸及烷胺。適合的胺基酸類包括,但不限於,胺基乙酸、丙胺酸、天門冬素、天門冬酸、半胱胺酸、胺基戊二酸、麩胺酸、脯胺酸、絲胺酸、酪胺酸、精胺酸及組胺酸。有一具體實施例中,該螯合劑為胺基酸,例如胺基乙酸。在較佳的具體實施例中,胺基乙酸為該螯合劑。適合的烷胺類包括,但不限於,乙二胺及三乙二胺。
其他可加至該CMP漿料組合物的化學藥品包括,舉例來說,水可混溶性溶劑、表面活性劑、pH調節劑、酸類、腐蝕抑制劑、含氟化合物、螯合劑、非聚合性含氮化合物及鹽類。
可加至該漿料組合物之適合的水可混溶的溶劑包括,舉例來說,醋酸乙酯、甲醇、乙醇、丙醇、異丙醇、丁醇、丙三醇、乙二醇及丙二醇及其混合物。有一具體實施例中該等水可混溶的溶劑可以約0重量%至約4重量%的濃度存在於該漿料組合物中,在另一具體實施例中約0.1重量%至約2重量%的濃度,及在又另一具體實施例中約0.5重量%至約1重量%的濃度;這些重量%值各自係以該漿料的總重量為基準。水可混溶的溶劑之較佳類型為異丙醇、丁醇及丙三醇。
可加至該漿料組合物之適合的表面活性劑化合物包括,舉例來說,熟悉此技藝者已知的眾多非離子型、陰離子型、陽離子型或兩性表面活性劑中之任何者。有一具體實施例中該等表面活性劑化合物可以約0重量%至約1重量%的濃度存在於該漿料組合物中,在另一具體實施例中約0.0005重量%至約1重量%的濃度,及在又另一具體實施例中約0.001重量%至約0.5重量%的濃度;這些重量%值各自係以該漿料的總重量為基準。表面活性劑之較佳類型為非離子型、陰離子型或其混合物而且最佳以該漿料總重量的約10 ppm至約1000 ppm的濃度存在。較佳為非離子型表面活性劑。
該pH-調節劑係用以改善該拋光組合物的安定性,改善使用時的安全性或符合多種不同規範的要求。關於能用以降低本發明的拋光組合物的pH之pH-調節劑,可運用氫氯酸、硝酸、硫酸、氯醋酸、酒石酸、丁二酸、檸檬酸、蘋果酸、丙二酸、多種不同脂肪酸類、多種不同聚羧酸類。另一方面,關於能用於提高該pH的目的之pH-調節劑,可運用氫氧化鉀、氫氧化鈉、氨、氫氧化四甲銨、氫氧化銨、六氫吡嗪、聚乙烯亞胺,等等。關於pH本發明的拋光組合物並沒有特別限制,但是其通常係調節至pH 5至12而且,在多種不同具體實施例中,將該pH調節至pH 7至12。有一具體實施例中,適合的鹼性漿料pH,舉例來說為約7至約11。在另一具體實施例中,適合的漿料pH為約8至約10。在另一具體實施例中該pH係介於10.01與10.49之間。有一具體實施例中,該pH係介於10.5與11.5之間。在另一具體實施例中,該pH係介於11.6與13之間。
其他可加至該漿料組合物的適合酸化合物(取代或除了前文提及的pH-調整酸類之外)包括,但不限於,甲酸、醋酸、丙酸、丁酸、戊酸、己酸、庚酸、辛酸、壬酸、乳酸、氫氯酸、硝酸、磷酸、硫酸、氫氟酸、蘋果酸、酒石酸、葡萄糖醛酸、檸檬酸、苯二甲酸、焦兒茶酸、焦棓酚羧酸、沒食子酸、單寧酸及其混合物。這些酸化合物可以約該漿料總重量的約0重量%至約5重量%的濃度存在於該漿料組合物中。
可加至該漿料組合物的適合腐蝕抑制劑包括,舉例來說,1,2,4-三唑、苯并三唑、6-甲苯基三唑、甲苯基三唑衍生物、1-(2,3-二羧丙基)苯并三唑及分支之經烷基酚取代的苯并三唑化合物。一些有用的商用腐蝕抑制劑包括Mafol3MOD1、Iconol TDA-9及Iconol TDA-6(全都能自新澤西州,弗洛哈姆公園的BASF有限公司取得),及Daetec MI-110(可自加州,卡瑪利洛的Daetec有限公司取得)。有一具體實施例中,該腐蝕抑制劑為酚化合物,而且在另一具體實施例中,該酚化合物為以介於0.001重量%(10 ppm)與5重量%之間的量存在的兒茶酚。有一具體實施例中該腐蝕抑制劑可以約0 ppm至約4000 ppm的濃度存在於該漿料中,在另一具體實施例中約10 ppm至約4000 ppm,在另一具體實施例中約50 ppm至約2000 ppm,及在又另一具體實施例中約50 ppm至約500 ppm,所有均以該漿料的總重量為基準。有一具體實施例中,該腐蝕抑制劑係以介於0.0005重量%(5 ppm)與0.1重量%(1000 ppm)之間的量存在。
若添加羧酸類的話,也可賦予該漿料組成物腐蝕抑制性質。
必要的話,為了進一步提高在CMP期間相對於介電質及/或底晶圓材料移除特定金屬的選擇性,可將含氟化合物加至該漿料組成物。適合的含氟化合物包括,舉例來說,氟化氫、過氟酸、鹼金屬氟化物鹽、鹼土金屬氟化物鹽、氟化銨、氟化四甲基銨、二氟化銨、二氟化乙二銨、三氟二乙三銨及其混合物。有一具體實施例中該含氟化合物可以約0重量%至約5重量%的濃度存在於該漿料組成物中,在另一具體實施例中較佳約0.65重量%至約5重量%,在又另一具體實施例中約0.5重量%至約2重量%,全都以該漿料的總重量為基準。適合的含氟化合物為氟化銨。
可加至該漿料組成物的適合非聚合物含氮化合物(胺類、氫氧化物,等等)包括,舉例來說,氫氧化銨、單乙醇胺、二乙醇胺、三乙醇胺、二乙二醇胺、N-羥乙基六氫吡嗪及其混合物。這些非聚合物含氮化合物可以約0重量%至約4重量%的濃度存在於該漿料組成物中,而且,若有的話,通常以該漿料總重量的約0.01重量%至約3重量%的量存在。較佳的非聚合物含氮化合物為單乙醇胺。
還有其他可加至該等漿料組成物的化學藥品為生物藥劑,例如殺菌劑、生物殺滅劑及殺黴菌劑,尤其是若該pH在約6至9左右。適合的殺菌劑包括,但不限於,1,2-苯并異噻唑啉-3-酮;2-(羥甲基)胺基乙醇;1,3-二羥甲基-5,5-二甲基乙內醯脲;1-羥甲基-5,5-二甲基乙內醯脲;3-碘-2-丙炔基-丁基胺基甲酸酯;戊二醛;1,2-二溴-2,4-二氰基丁烷;5-氯-2-甲基-4-異噻唑啉-3-酮;2-甲基-4-異噻唑啉-3-酮;及其混合物。較佳的殺菌劑為異噻唑啉類及苯并異噻唑啉類。有存在時,殺菌劑通常以該漿料總重量的約0.001重量%至約0.1重量%的濃度存在。
本發明中所利用的CMP方法在穿晶圓加工期間使用前述的組成物(如前文所揭示)供基底晶圓背側(例如,矽晶圓)的化學機械平坦化之用。有一具體實施例中,該底晶圓為矽晶圓。
本發明的底晶圓兼具前及後側,而且該前側具有佈置在其上的積體電路。該底晶圓包含至少一導電貫孔,該至少一導電貫孔包含導電金屬而且該至少一導電貫孔從該底晶圓的前側至少局部延伸穿過該底晶圓。該至少一導電貫孔的導電金屬一般可為任何於周遭溫度時為固體的導電金屬。導電金屬,例如汞及在周遭的溫度和壓力條件之下不是固體(例如,液體)的合金,被可用於本發明的導電貫孔之材料排除在外。導電金屬的實例為銅、鎢及鋁。有一具體實施例中,該導電金屬為銅。在另一具體實施例中,該導電金屬係選自由銅及鎢所組成的群組。
在本發明的方法中,把該(第一)底晶圓的前側黏附於一載體。該載體可為任何能在後續CMP加工(如下所述)的期間扮作該底晶圓的適合支撐件的材料。適合的載體材料包括,但不限於,鋼、玻璃及多種不同聚合物,例如聚乙烯、聚丙烯及聚(氯乙烯)。
在本發明方法之一具體實施例中,把上面具有積體電路的底晶圓前側黏附於該載體可依此技藝中已知任何方式完成。有一實例為使用適合的黏著劑把該底晶圓的前側暫時黏合於該載體,同時在該底晶圓背側上進行CMP加工及/或研磨。把該底晶圓黏附於該載體提供呈夾層構造的底晶圓/載體而且該底晶圓的背側為一外表面。
在CMP加工之前可以或可不在該底晶圓/載體上進行從第一底晶圓的背側移除相當大量材料的研磨步驟以將該底晶圓的背側平坦化。此技藝中已知的任何研磨方法均可利用。有一具體實施例中,在化學機械拋光該底晶圓的背側之前,該底晶圓的背側並未進行研磨步驟。在另一具體實施例中,在化學機械拋光該底晶圓的背側之前對該底晶圓的背側進行研磨步驟。
接下來,接著該研磨步驟之後,若是完成,根據本發明的方法,設置該底晶圓的背側/載體,以致於該底晶圓的背側經常面向下放在拋光墊上,把該拋光墊不動地貼附於CMP拋光機的旋轉式壓盤。依此方式,使待拋光及平坦化的底晶圓背側與該拋光墊接觸。用晶圓承載系統或拋光頭把該底晶圓/載體保持於定位並且在CMP加工的期間靠在該底晶圓的背側/載體應用向下壓力,同時旋轉該壓盤及該基材。在CMP加工的期間把該拋光組成物(第一CMP漿料)應用(通常連續地)在該墊子上,穿過該墊子或介於該墊子與晶圓之間以引起該底晶圓(例如,矽晶圓)背側的材料移除。根據本發明,利用該第一CMP漿料的方法將於至少5,000埃/分的速率於6 psi或更低的向下作用力拋光第一底晶圓。
有一具體實施例中,利用該第一CMP漿料的方法將於至少5,000埃/分的速率於6 psi或更低的向下作用力拋光該第一底晶圓。有一具體實施例中,利用該第一CMP漿料的方法將於至少9,000埃/分的速率於6 psi或更低的向下作用力拋光該第一底晶圓。有一具體實施例中,利用該第一CMP漿料的方法將於至少12,000埃/分的速率於6 psi或更低的向下作用力拋光該第一底晶圓。有一具體實施例中,利用該第一CMP漿料的方法將於至少16,000埃/分的速率於6 psi或更低的向下作用力拋光該第一底晶圓。高底晶圓移除速率為本發明的功效所不可或缺,因為經常能移除大量的底層材料。
接著上述的CMP加工之後將該第一底晶圓背側薄化及平坦化,接著該載體通常能被移除,而且能在曝露出用於裝配堆疊積體電路晶片的穿底晶圓貫孔時使用所得的較薄底晶圓。等在該底晶圓上進行本發明的平坦化及薄化之後,裁切或切割該晶圓以分離各自在該底晶圓的表面上複製許多次的單獨積體電路晶片。各個積體電路晶片含有使個別積體電路晶片能與其他類似積體電路晶片或來自完全不同的底晶圓及晶圓加工之具有電路的晶片互連的貫孔。這形成二或更多由一或更多底晶圓所製造的積體電路晶片之3-D堆疊體。
進一步藉由下列實施例來示範本發明。
符號及定義:
1. CMP為化學機械平坦化=化學機械拋光
2.為埃,長度的單位
3./min為以每分鐘埃表示的拋光速率
4. psi為每平方吋磅數
5. BP為以psi表示的背壓
6. PS為該拋光機具的壓盤旋轉速度,以rpm(每分鐘轉數)表示
7. SF為以ml/min表示的漿料流量
8. CS為載體速度
9. DF為以psi表示的向下作用力
10. min為分鐘
11. ml為毫升
12. mV為毫伏特
13. NA意指數據無法取得
14. Rpm為每分鐘轉數
15. 重量%為重量百分比
除了另行指明,否則所有組成分的濃度均為重量%。實施例所述的所有拋光實驗均以該拋光機的6 psi的向下作用力(DF)進行。
下述所有實驗係利用下文所列舉的設備進行。
CMP機具:由Speedfam IPEC(本公司現在已為Novellus所擁有)所製造的IPEC 472,二壓壓盤系統,僅使用帶有下列墊子的壓盤1。
墊子:來自Nita Haas的Suba 600
墊子磨合為利用試驗漿料及Si填料晶圓的一小時壓盤預熱(至某溫度)。
晶圓:來自德州,奧斯丁的SVTC的銅電鍍晶圓
銅晶圓膜堆疊體:矽基材上5000TEOS(四乙基原矽酸酯)上250鉭上80,000Cu。
來自Silicon Valley Microelectronics的裸矽晶圓
矽晶圓各自具有725微米±15微米厚度。
利用與去離子水以10:1稀釋的MazinTM SR300矽膠漿料(亞利桑那州,潭碧谷的DuPont Air Products Nanomaterials有限公司)製成的CMP漿料作為對照組。此漿料具有10.6的pH。在拋光實驗中配合Si及Cu空白晶圓使用該漿料,該漿料提供9644/min的矽移除速率及259/min的銅移除速率。儘管該矽移除速率相對較高,但是沒有任何氧化劑存在時該銅移除速率非常低。
如實施例1所述將過氧化氫加至該漿料,以致於該過氧化氫的濃度在所得的漿料中為1重量百分比。在拋光實驗中配合Si及Cu空白晶圓使用此帶有氧化劑的所得漿料,該漿料提供1468/min的矽移除速率及270/min的銅移除速率。於1重量百分比濃度的過氧化氫的添加導致該矽移除速率戲刻性地降低,但是該銅移除速率依舊是大約相同。
如實施例1所述將胺基乙酸加至該漿料,並且接著添加過氧化氫,以致於該過氧化氫的濃度在所得的漿料中為1重量百分比而且所得的漿料中的胺基乙酸濃度為0.4重量百分比。在過氧化氫添加之前,該SR300/胺基乙酸混合物的pH為9.85。在拋光實驗中配合Si及Cu空白晶圓使用此所得的漿料,其含有該SR300產物、過氧化氫及胺基乙酸,該漿料提供2259/min的矽移除速率及3653/min的銅移除速率。儘管胺基乙酸的添加導致該銅移除速率的實質提高,但是該矽移除速率由於過氧化氫以1重量百分比濃度存在仍舊非常低,該濃度(1重量%)經常用於銅CMP中。
以實施例1至3的相同方式進行這些實施例。如表3所示,如接下來描述的方式測試該等CMP漿料。實施例4的CMP漿料與實施例1同為10:1 SR300對照組漿料。實施例5至8的漿料各自含有10:1 SR300及0.4重量百分比胺基乙酸,而且對於實施例5、6、7及8該過氧化氫濃度分別變化於1重量%至3重量%至5重量%至7重量%。如表3所示,將該過氧化氫的濃度提高至高於1重量百分比不會導致高相當多的銅移除速率,但是卻會導致降低的矽移除速率。
這些實施例舉例說明類似於實施例5至8的組合物,但是具有較低濃度的過氧化氫驚人地同持提供矽及銅的高移除速率。在實施例9中,該過氧化氫濃度為0.25重量百分比而且,在實施例10,該過氧化氫濃度為0.5重量百分比。參見表2。
這些實施例用不同的低濃度過氧化氫,但是其他方面則以實施例3相同的方式進行。如表3所示,接下來描述所測試的CMP漿料。實施例11至15的漿料各自含有10:1 SR300及0.4重量百分比胺基乙酸,而且對於實施例11、12、13、14及15,該過氧化氫濃度變化於0.25重量%至0.2重量%至0.15重量%至0.1重量%至0.05重量%。(對於這些漿料在過氧化氫添加之前該SR300及胺基乙酸漿料的pH為9.85。)如表3所示,該過氧化氫的濃度隨著過氧化氫濃度降低從0.25重量%降至0.05重量%導致提高相當多的矽移除速率及較高但是衰退的銅移除速率。
如歸納於表3中的結果所示,含有大約0.15重量百分比的過氧化氫的漿料不僅提供與對照組樣品大約相同的矽移除速率,而且還提供更高許多的銅移除速率。再者,該Cu:Si選擇性可藉由調節該過氧化氫的濃度調整而且可達成1:1 Cu:Si選擇性漿料。配合低於0.5重量百分比的過氧化氫濃度使用這些漿料提供使該矽拋光速率保持於接近該對照組樣品(實施例1漿料)的拋光速率,同時也大大地推升該銅移除速率。
利用下列指示濃度的組分製成的預添加過氧化物底漿料(底漿料A):
依上文所列舉的順序將該等組分加至去離子水以提供此底漿料A,其具有9.94的pH。SytonHT-50及HS-40矽膠漿料為DuPont Air Products Nanomaterials有限公司(亞利桑那州,潭碧谷)可自商業上取得的產品。
於實施例16將過氧化氫以0.1重量%濃度加至此底漿料,於實施例17中0.15重量%濃度,及於實施例18中0.2重量%,以提供這些帶有過氧化氫的使用點漿料。CMP試驗時使用這些漿料拋光Si及Cu空白晶圓以測量矽及銅移除速率。表4總結所獲得的結果。如表4中的結果所示,這些漿料對於矽及銅二者均具有非常高移除速率的可調整1:1 Cu:Si選擇性漿料。於這些低濃度的過氧化氫下,該銅移除速率可藉由稍微調節該氧化劑的濃度而調整,同時對於該矽移除速率僅具有小的效應。調整時,必要的話,此漿料能產生精確的1:1 Cu:Si選擇性漿料。
Claims (23)
- 一種製備用於建構包含至少二積體電路晶片的組合件之底矽晶圓的方法,該等積體電路晶片之至少其一係來自該底矽晶圓,該方法包含:a)提供具有前及後側的底矽晶圓,其中該前側包含佈置在其上的積體電路及其中該底矽晶圓包含至少一導電貫孔,該至少一導電貫孔包含導電金屬至少局部延伸穿過該底矽晶圓;b)將上面具有積體電路的底矽晶圓前側黏附於一載體;c)使該底矽晶圓背側與拋光墊及第一化學機械平坦化漿料接觸,該第一化學機械平坦化漿料包含:1)液態載劑;2)於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;及3)研磨劑;以及d)拋光該底矽晶圓的背側直到至少一導電貫孔曝露出來或進一步曝露出來為止,其中利用該第一CMP漿料於至少5,000埃/分的移除速率於6psi或更低的向下作用力拋光第一底矽晶圓上的矽。
- 如申請專利範圍第1項之方法,其中該第一CMP漿料另外包含4)至少一金屬螯合劑及其中利用該第一CMP漿料於至少5,000埃/分的移除速率於6psi或更低的向下作用力拋光該第一底矽晶圓上的導電金屬。
- 如申請專利範圍第1項之方法,其中該導電金屬係選自由銅及鎢所構成的群組。
- 如申請專利範圍第3項之方法,其中該導電金屬為銅。
- 如申請專利範圍第4項之方法,其中該第一化學機械平坦化漿料產生之Cu:Si選擇性介於2:1至0.5:1。
- 如申請專利範圍第5項之方法,其中該第一化學機械平坦化漿料產生之Cu:Si選擇性介於1.5:1至0.67:1。
- 如申請專利範圍第5項之方法,其中該第一化學機械平坦化漿料產生之Cu:Si選擇性介於1.2:1至0.8:1。
- 如申請專利範圍第1項之方法,其中該液態載劑包含水。
- 如申請專利範圍第1項之方法,其中該該底矽晶圓的背側並未在化學機械拋光該底矽晶圓的背側之前進行研磨步驟。
- 如申請專利範圍第1項之方法,其中該底矽晶圓的背側係於化學機械拋光該底矽晶圓的背側之前進行研磨步驟。
- 如申請專利範圍第1項之方法,其中該過氧化氫濃度係於0.1至0.25重量百分比的範圍中。
- 如申請專利範圍第1項之方法,其中該過氧化氫濃度係於0.15至0.2重量百分比的範圍中。
- 一種製備用於建構包含至少二積體電路晶片的組合件之底矽晶圓的方法,該等積體電路晶片之至少其一係來自該底矽晶圓,該方法包含:a)提供具有前及後側的底矽晶圓,其中該前側包含佈置在其上的積體電路及其中該底矽晶圓包含至少一導電貫孔,該至少一導電貫孔包含導電金屬並且從該底矽晶圓的前側至少局部延伸穿過該底矽晶圓;b)將上面具有積體電路的底矽晶圓前側黏附於一載體;c)使該底矽晶圓背側與拋光墊及第一化學機械平坦化漿料接觸,該第一化學機械平坦化漿料包含:1)液態載劑;2)於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;及3)研磨劑,其可懸浮於該漿料中,其可黏附於拋光墊,或兼備二者;4)至少一金屬螯合劑;以及d)拋光該底矽晶圓的背側直到至少一導電貫孔曝露出來或進一步曝露出來為止,其中利用該第一化學 機械平坦化漿料於至少5,000埃/分的速率於6psi或更低的向下作用力拋光該底矽晶圓。
- 一種化學機械平坦化組合物,用於至少包含一金屬之底矽晶圓,其由:a)研磨劑;b)於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;以及c)水,所組成。
- 一種化學機械平坦化組合物,用於至少包含一金屬之底矽晶圓,其由:a)研磨劑;b)於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;c)水;及d)螯合劑所組成。
- 如申請專利範圍第14項之化學機械平坦化組合物,其中該過氧化氫濃度係於0.1至0.25重量百分比的範圍中。
- 如申請專利範圍第14項之化學機械平坦化組合物,其中該過氧化氫濃度係於0.15至0.2重量百分比的範圍中。
- 如申請專利範圍第2項之方法,其中該至少一金屬螯合劑由胺基酸、乙二胺四醋酸及烷胺所組成之群組中選出。
- 如申請專利範圍第2項之方法,其中該至少一金屬螯合劑為胺基酸,其由胺基乙酸、丙胺酸、天門冬素、天門冬酸、半胱胺酸、胺基戊二酸、麩胺酸、脯胺酸、絲胺酸、酪胺酸、精胺酸及組胺酸所組成之群組中選出。
- 如申請專利範圍第19項之方法,其中該至少一金屬螯合劑為胺基乙酸。
- 如申請專利範圍第13項之方法,其中該至少一金屬螯合劑由胺基酸、乙二胺四醋酸及烷胺所組成之群組中選出。
- 如申請專利範圍第18項之方法,其中該至少一金屬螯合劑為胺基乙酸。
- 一種使用化學機械平坦化組合物拋光矽及至少一金屬的用途,該化學機械平坦化組合物包含:a)研磨劑;b)於0.02重量百分比至低於0.50重量百分比的濃度的過氧化氫;以及c)水。
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