TWI500150B - 具有豎直電荷補償結構和次級表面連接層的半導體裝置以及方法 - Google Patents
具有豎直電荷補償結構和次級表面連接層的半導體裝置以及方法 Download PDFInfo
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- TWI500150B TWI500150B TW098121053A TW98121053A TWI500150B TW I500150 B TWI500150 B TW I500150B TW 098121053 A TW098121053 A TW 098121053A TW 98121053 A TW98121053 A TW 98121053A TW I500150 B TWI500150 B TW I500150B
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- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
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- H01L21/34—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies not provided for in groups H01L21/0405, H01L21/0445, H01L21/06, H01L21/16 and H01L21/18 with or without impurities, e.g. doping materials
- H01L21/46—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/428
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- H01L21/4763—Deposition of non-insulating, e.g. conductive -, resistive -, layers on insulating layers; After-treatment of these layers
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
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- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
- H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
- H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
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- H01L29/0642—Isolation within the component, i.e. internal isolation
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Description
本文件大體而言係關於半導體裝置,且更具體言之係關於功率半導體裝置,及其製造方法。
金氧半導體場效電晶體(MOSFET)係常見類型之功率切換裝置。MOSFET裝置包含一源極區、一汲極區、在源極區與汲極區之間延伸的一通道區,及一鄰近該通道區提供的閘極結構。該閘極結構包含一傳導性閘電極層,該閘電極層經安置為鄰近於該通道區,但藉由薄介電層與該通道區分離。
當MOSFET裝置處於接通狀態時,將電壓施加至該閘極結構以在源極區與汲極區之間形成一傳導通道區,此允許電流流過該裝置。在斷開狀態下,施加至閘極結構之任何電壓足夠低,使得不會形成傳導通道,且由此不會出現電流。在處於斷開狀態之同時,該裝置必須在源極區與汲極區之間支援高電壓。
擊穿電壓(BVdss)及接通狀態電阻(Rdson)係針對高電壓功率切換裝置之兩個重要裝置參數。對於具體應用而言,需要最小擊穿電壓,且實務上,設計者通常可滿足BVdss規範。然而,此經常以Rdson為代價。此效能折衷係對於高電壓功率切換裝置之製造商及使用者的主要設計挑戰。
近來,流行獲得超接合裝置以改良在Rdson與BVdss之間的折衷。在習知n通道超接合裝置中,多個重摻雜n型及p型擴散區替代一個輕摻雜n型磊晶區。在接通狀態下,電流流過重摻雜n型區,此降低Rdson。在斷開或阻塞狀態下,重摻雜n型及p型區彼此耗盡或補償以提供高BVdss。儘管自裝置效能之觀點而言超接合裝置的前景繼續被看好,但在極其穩固之裝置結構及製造方法方面仍存在挑戰。
因此,需要提供較低Rdson、較高BVdss及更穩固之效能的高電壓功率切換裝置結構及製造方法。
圖1展示根據本發明之一實施例之絕緣閘場效電晶體(IGFET)、MOSFET、超接合裝置、超接合結構、電荷補償的,或切換裝置或單元10的部分橫截面圖。藉由實例,裝置10在許多此等裝置當中:與邏輯及/或其他組件整合至半導體晶片中作為功率積體電路的部分。或者,裝置10在許多此等裝置當中:經整合在一起以形成一離散電晶體裝置。
裝置10包含半導體材料11之一區,其包括(例如)具有在大約0.001至約0.01歐姆-cm之範圍中之電阻率的n型矽基板12,且可摻雜有砷或磷。在所示實施例中,基板12為裝置10提供一汲極區,其鄰近於導電層13。半導體層14在基板12中或上形成且為n型或p型且摻雜足夠輕以便不會影響下文所描述之渠溝補償區中的電荷平衡。在一實施例中,使用習知磊晶生長技術來形成層14。在一適用於600伏特裝置之實施例中,層14為摻雜n型或p型的,摻雜物濃度為約1.0×1013
原子/cm3
至約5.0×1014
原子/cm3
,且具有大約為約40微米至約60微米的厚度。注意,儘管半導體層14在圖式中展示為比基板12厚,但實際上基板12更厚。為易於理解,在圖式中以此方式來展示其。
在一實施例中,層14之一部分在裝置10之活性區部分中為摻雜p型的,而層14的另一部分在該裝置之邊緣終止部分中為摻雜n型的。層14之厚度視裝置10之所要BVdss額定值而增大或減小。在一替代實施例中,半導體層14包括分級摻雜物分布,半導體層14具有較高之接近於基板12的摻雜物濃度,且針對其厚度朝向主表面18之平衡逐漸地或突然地轉變至較低濃度。
其他材料可用於半導體材料11或其部分的主體,該等材料包含矽鍺、矽鍺碳、摻雜碳之矽、III-V材料或其類似者。另外,熟習此項技術者將理解,絕緣閘雙級電晶體(IGBT)裝置係藉由(例如)將基板12之傳導性類型改變為p型(亦即,與半導體層14相反)以本結構達成。
裝置10進一步包含間隔開之填充渠溝,補償渠溝、半導體材料填充之渠溝、電荷補償渠溝區、深渠溝電荷補償區、電荷補償填充渠溝、補償渠溝、區域化之豎直電荷補償結構、或區域化之電荷補償區22。如本文所使用,電荷補償大體意謂相反傳導性類型之層的總電荷實質上或大體上平衡或相等。電荷補償填充渠溝22包含半導體材料220之複數個層或多個層,包含相反傳導性類型(亦即,n型及p型中之至少各一個)之至少兩個層,其可由(多個)固有的、緩衝或輕摻雜半導體層分離。如圖1中所示,材料220包含n型半導體材料層221,該材料層沿渠溝之側壁表面毗連半導體層14。
根據一較佳實施例,層221具有與源極區33相同之傳導性類型,且在裝置10處於接通狀態時形成自通道至汲極的主豎直低電阻電流路徑。補償p型半導體材料層222經形成為上覆於層221。藉由實例,n型層221及p型層222具有大約為約1.0×1015
原子/cm3
至約1.0×1017
原子/cm3
的摻雜物濃度,且各自具有約0.1微米至約0.4微米的厚度。當裝置10處於斷開狀態時,p型層222及n型層221彼此補償以提供增加的BVdss特性。儘管圖1之裝置中並未展示緩衝層,但應理解,其可存在於較早製造步驟中。在一較佳實施例中,半導體材料220之多個層包括一單晶半導體材料。下文結合圖4及圖5描述關於電荷補償渠溝22及半導體材料220之多個層的額外細節。
在一較佳實施例中,裝置10包含一介電層28,其形成為上覆於半導體材料220的多個層。在一實施例中,介電層28為具有約0.2微米之厚度的經沈積氧化矽層。在所示實施例中,以處於中央定位部分處的空隙或密封核心29組態或形成電荷補償渠溝22,且以插塞結構91封端(cap)。在一較佳實施例中,插塞91包括一單晶半導體材料,其沿半導體材料220之多個層的上部磊晶生長以封鎖電荷補償渠溝22。在一實施例中,該單晶半導體材料隨後經平坦化,使得插塞91之上表面接近於主表面18。在一替代實施例中,電荷補償渠溝22係無孔的,且用材料填充,該等材料諸如介電質、多晶半導體材料、單晶半導體材料或其組合。
儘管未圖示,但應理解,在裝置10之形成期間,來自高摻雜基板12之n型摻雜物擴散至電荷補償渠溝22的下部中,使得渠溝22在基板12內的彼等部分成為更重摻雜之n型。
裝置10亦包含井、基底、形成於半導體層14中於電荷補償渠溝22之間且接近於、鄰近於或毗連其的主體或摻雜區31。主體區31自半導體材料11之主表面18延伸。在一實施例中,主體區31包括p型傳導性,且具有適於形成作為裝置10之傳導通道45操作之反轉層的摻雜物濃度。主體區31自主表面18延伸至約1.0微米至約5.0微米之深度。如上文所陳述,主體區31包括複數個個別擴散區,或包括具有所選形狀的經連接、單一或一般擴散區。
N型源極區33形成於主體區31內、上方或其中,且自主表面18延伸至約0.2微米至約0.5微米的深度。在所示實施例中,主表面18之多個部分向下延伸,且接著自源極區33之邊緣向外延伸,使得藉由源極接觸層63而接觸源極區33之水平表面及豎直表面。在每一主體區31之至少一部分中形成一或多個p型主體接觸區36。主體接觸區36經組態以向主體區31提供較低接觸電阻,且降低在源極區33下方之主體區31的抑制寄生雙極效應之薄層電阻。
根據一較佳實施例,主體接觸區36及主體區31上覆於電荷補償渠溝22(如圖1中所示),且連同源極接觸層63經組態以向電荷補償渠溝22中之p型層222提供歐姆接觸並提供與電荷補償渠溝22中之p型層222的連續性。此歐姆接觸結構經組態以為p型層222提供接地結構,此消除主表面18處之橫向電場並改良裝置10的擊穿電壓效能。此結構亦消除(ground)存在於主表面18附近及存在於電荷補償渠溝22內或附近之任何缺陷的效應。裝置10之結構大大簡化與層222接觸之能力,此對於最佳化裝置效能為必要的。詳言之,裝置10避免使用上覆於電荷補償渠溝22之上部的任何複雜構形,此簡化歐姆接觸結構及方法。
裝置10進一步包含毗連主體區31及源極區33之渠溝閘或控制結構157。控制結構157與鄰近的電荷補償渠溝22橫向間隔開。亦即,控制結構157並不上覆於電荷補償渠溝22。渠溝閘結構157包含閘渠溝158及形成為上覆於閘渠溝158之表面的閘介電層43。在一實施例中,閘介電層43包括氧化矽,且具有約0.05微米至約0.1微米的厚度。在另一實施例中,閘介電層43在閘渠溝158之下表面處具有一厚度,該厚度大於或厚於沿閘渠溝158之側壁的閘介電層43之厚度。在替代實施例中,閘介電層43包括氮化矽、五氧化二鉭、二氧化鈦、鈦酸鍶鋇,或其包含與氧化矽或其類似者之組合的組合。
渠溝閘結構157進一步包含形成於控制或閘渠溝158內之導電閘區57,且該結構上覆於閘介電層43。在一實施例中,源極區33介入於導電閘區57與電荷補償渠溝22之間。導電閘區57包括(例如)n型多晶矽。儘管導電閘區57經展示為凹入於主表面18下方,但導電閘區57可延伸高於主表面18或在主表面18上方。渠溝閘結構157經組態以控制通道45之形成及裝置10中的電流傳導。
為了促進次級表面電流路徑,裝置10進一步包含n型摻雜層或次級表面摻雜層26。具體言之,摻雜層26經組態以在通道45之汲極端與n型層221之間提供次級表面傳導路徑,n型層221係在電荷補償渠溝22中之主傳導層或豎直傳導路徑。亦即,在裝置10中,電流豎直地流過通道45,接著水平地流過摻雜層26,且接著豎直地流過層221。摻雜層26經組態以使得電流藉由傳導性類型(p型)與摻雜層26(n型)相反之主體區31及主體接觸區36與主表面18隔離。此隔離特徵保持傳導路徑遠離在表面附近之缺陷區,藉此避免任何傳導相關問題。此外,經接地之p型層222的結構進一步隔離任何高缺陷密度區之效應與主傳導路徑。另外,藉由置放主體區31及主體接觸區36使得其上覆於摻雜區26,提供環繞n型層221及摻雜層26之較佳凹形接面。此有益地增強BVdss。
裝置10進一步包含形成為上覆於主表面18之層間介電區48,該層間介電區48經圖案化以向主體接觸區36及源極區33提供開口。層間介電區48之一部分保留而上覆於渠溝閘結構57以提供對傳導閘區57之隔離。層間介電區48包括(例如)諸如經沈積氧化物之氧化矽,且具有約0.4微米至約1.0微米的厚度。
源極接觸層63形成為上覆於主表面18,且與源極區33及主體接觸區36兩者接觸。在一實施例中,源極接觸層63包括鈦/氮化鈦障壁層及上覆於該障壁層而形成的鋁矽合金,或其類似者。汲極接觸層13經形成為上覆於半導體材料11之相對表面,且包括(例如)可軟焊金屬結構,諸如鈦鎳銀、鉻鎳金或其類似者。
總而言之,裝置10之結構及方法將主傳導層221置放於鄰近電荷補償渠溝22之側壁表面處。裝置10使用渠溝閘控制結構157,該控制結構157將通道45之汲極端或次級表面置放為與主表面18間隔開、與其遠離。裝置10將電連接通道45之次級表面汲極端至主傳導層221的次級表面摻雜層26併入於電荷補償渠溝22中。此方法移動主電流路徑遠離裝置之表面,此使其更不易受應力問題及缺陷影響,藉此改良效能。另外,因為以此方式組態裝置10之主電流路徑,所以簡化了在p型補償摻雜層222、主體區31、主體接觸區36及源極接觸層63之間形成歐姆接觸結構。
裝置10之操作如下繼續進行。假設源極端子63在零伏特之電位VS
下操作,傳導閘區157接收大於裝置10之傳導臨限值的控制電壓VG
=5.0伏特,且汲極端子13在汲極電位VD
=5.0伏特下操作。VG
及VS
之值使主體區31反轉鄰近的傳導閘區157以形成電連接源極區33至摻雜區26的豎直通道45。裝置電流ID
流自汲極端子13,且投送通過n型層221、摻雜層26、通道45、源極區33至源極端子63。因此,電流ID
豎直地流過n型層221以使電阻降低,且水平地流過保持電流路徑與主表面18隔離的次級表面摻雜層26。在一實施例中,ID
=1.0安培。為將裝置10切換至斷開狀態,將小於該裝置之傳導臨限值的控制電壓VG
施加至傳導閘區157(例如,VG
<5.0伏特)。此移除通道45,且ID
不再流過裝置10。在斷開狀態下,n型層221及p型層222彼此補償作為自主阻塞接面擴展的空乏區,此增強BVdss。裝置10之另一優點在於p型補償摻雜層222、主體區31、主體接觸區36及源極接觸層63之間的簡化之歐姆接觸結構增強切換特性。舉例而言,當裝置10自接通狀態切換至斷開狀態時,歐姆接觸更有效地自該結構牽引電子及電洞兩者。
現轉至圖2至圖14,描述根據一較佳實施例之用於形成裝置10的製程。圖2展示在早期製造階段處之裝置10的放大部分橫截面圖。結合上文之圖1而提供半導體材料11之主體之材料特性的實例。在一早期步驟中,介電層40形成為上覆於主表面18,且包括(例如)約0.2微米厚的熱氧化物。包括不同於介電層40之材料的介電層44接著形成為上覆於介電層40。藉由實例,當第一介電層40為氧化矽時,介電層44為氮化矽。在一實施例中,介電層44為大約0.2微米之氮化矽,且係使用習知沈積技術形成。接下來,介電層46形成為上覆於介電層44,且包括大約0.6微米之所沈積二氧化矽。此等層為後續處理提供硬遮罩結構112的一實例。
圖3展示在後續製造階段處之裝置10的放大部分橫截面圖。使用習知光微影及材料移除技術來圖案化硬遮罩結構112以形成暴露主表面18之多個部分的開口72。藉由實例,開口72具有約3.0微米至約4.0微米之寬度74。接下來,形成穿過開口72自主表面18延伸至半導體層14中的渠溝122。在一實施例中,半導體層14在鄰近之渠溝122之間具有約2.0微米至3.0微米的寬度75。為易於理解此實施例,寬度75經展示為大於寬度74,且理解寬度75可小於或等於寬度74。在一實施例中,渠溝122延伸至基板12之至少一部分中。渠溝122之深度由半導體層14之係BVdss之函數的厚度所確定。
在一實施例中,使用基於用氟或氯進行蝕刻之深反應離子蝕刻(DRIE)的化學處理來形成渠溝122。若干技術可用於DRIE蝕刻渠溝122,包含低溫、高密度電漿或Bosch DRIE處理。在一實施例中,渠溝122具有實質上豎直之側壁。在一替代實施例中,渠溝122具有錐形剖面,其中在渠溝下表面處之渠溝寬度小於寬度74。儘管渠溝122經陳述為複數的,但應理解,渠溝122可為單一連續渠溝或經連接之渠溝矩陣。或者,渠溝122可為具有閉合端並由半導體材料11之主體的多個部分分離的複數個個別渠溝。渠溝122之深度在自約3.0微米至約100微米的範圍內。
圖4展示在稍後製造階段處之裝置10的放大部分橫截面圖。在此時,在渠溝122中形成、生長或沈積半導體材料220之多個層作為形成電荷補償渠溝22的第一步驟。在一實施例中,使用單晶半導體磊晶生長技術來形成半導體材料220的多個層。
在第一步驟中,在渠溝122之側壁上形成諸如熱氧化物的薄氧化物(未圖示)以移除由材料移除步驟所引起的任何表面損壞。接著使用習知各向同性蝕刻技術(例如,10:1之潮濕氧化物剝離)來移除該薄氧化物。接下來,將半導體材料11置放至磊晶生長反應器中,且預清洗該半導體材料作為磊晶生長製程中的第一步驟。當矽為用於形成半導體材料220之多個層的所選半導體材料時,諸如三氯矽烷(SiHCl3
)、二氯矽烷(SiH2
Cl2
)、矽烷(SiH4
)或二矽烷(Si2
H6
)之矽源氣體適用於形成此等層。
現參看圖5,描述形成半導體材料220之多個層之一較佳實施例,圖5係圖4中之渠溝122之一部分5的部分橫截面圖。在一較佳實施例中,在磊晶反應器內部以連續方式生長構成半導體材料220之多個層的所有層。此外,發現在形成半導體材料220之多個層時,使用減壓磊晶反應器為較佳的。具體言之,磊晶生長條件經設定以提供粗略等於或大於渠溝122之深度的平均自由路徑係較佳的。渠溝122之縱橫比在自約1:1至約30:1之範圍內以提供良好品質磊晶層亦為較佳的。
使用選擇性磊晶生長製程以避免生長上覆於介電層46的磊晶矽為進一步較佳的,此將產生多晶矽。藉由向磊晶生長腔室添加足夠抑制介電層上之矽生長之量的HCl氣體而控制選擇性。較佳地,當使用二氯矽烷或矽烷作為矽源氣體時,HCl流動速率經設定為處於自大於零至約4至5倍矽源氣體之流動速率的範圍內。在一替代實施例中,生長毯覆式層(亦即,除渠溝122之外上覆於主表面18而生長的層),且使用平坦化技術來移除該等毯覆式層之上覆於主表面18的多個部分。
在所示實施例中,首先沿渠溝122之表面形成本徵層21,且其具有約0.05微米至約0.1微米的厚度。本徵層21較佳為非摻雜的,且起作用以消除(smooth out)在渠溝122之側壁及下表面上的任何不規則性。接著用合適的磷、砷或銻摻雜物源上覆於層21而形成n型層23。在一實施例中,n型層23係輕摻雜的,且具有大約為約1.0×1015
原子/cm3
至約1.0×1017
原子/cm3
的摻雜物濃度。N型層23具有通常小於約1.0微米之厚度,約0.1微米至約0.4微米之厚度為一較佳範圍。
接下來,本徵層24形.成為上覆於n型層23,且具有約0.1微米至約0.4微米之厚度。較佳地,本徵層24係非摻雜的。p型層25接著形成為上覆於第二本徵層24,硼作為合適之摻雜物源。藉由實例,p型層25具有大約為約1.0×1015
原子/cm3
至約1.0×1017
原子/cm3
的摻雜物濃度。P型層25具有通常小於約1.0微米之厚度,且約0.1微米至約0.3微米之厚度為一較佳範圍。本徵層24之一目的在於藉由降低在低汲極電壓下之層23及25的相互耗盡而改良傳導,此提供較高傳導效率。
接下來,本徵層27形成為上覆於p型層25,且具有約0.1微米至約1.0微米之厚度。在後續熱處理期間,n型層23中之n型摻雜物擴散至本徵層21及24中以形成如圖1及圖4中所示的n型層221,且p型層25擴散至本徵層24及27中以形成如圖1及圖4中所示的p型層222。為了易於理解,未在其他圖式中展示在圖5中所示的多個層。n型層221及p型層222之摻雜物濃度及厚度經組態以在裝置10在操作中時提供適當平衡的電荷。在一較佳實施例中,渠溝122之中心或中央部分保持開放(亦即,該部分未完全填充有固體材料)。另外,在一較佳實施例中,在形成半導體材料220之多個層之後,淨化磊晶反應器之HCl、源氣體及摻雜物氣體,且在升高之溫度下將裝置10暴露給氫。此使半導體材料220之多個層之外表面的構形平滑,此增強包含插塞91之形成的後續處理。
圖6展示在更進一步之製造階段處之裝置10的放大部分橫截面圖。第一介電層形成為上覆於主表面18及渠溝122中之半導體材料220的多個層。藉由實例,此第一介電層包括一氧化物。在一實施例中,形成0.02微米之乾燥氧化物,接著約0.2微米的所沈積氧化物。接下來,第二介電層形成為上覆於第一介電層。在一實施例中,第二介電層包括約0.1微米的氮化矽。使用習知沈積技術來形成第一介電層及第二介電層。接著使用習知乾式蝕刻技術來回蝕第一介電層及第二介電層,留下在渠溝122內之每一材料的介電隔片、隔片層,或介電層28及62,如圖6中所示。在所述之實例中,層28包括約0.02微米之乾燥氧化物及約0.2微米的所沈積氧化物,且層62包括約0.1微米之氮化矽。
接下來,如係在進一步處理之後之裝置10之放大部分橫截面圖的圖7中所示,將介電層28暴露給額外選擇性蝕刻步驟以移除介電材料的上部,使得介電層28自介電層62之上表面凹入。藉由實例,當介電層28包括一氧化物時,使用稀釋HF濕式蝕刻(例如,10:1歷時約8至11分鐘)來使介電層28凹入至介電層62下方大約1.2微米。在此等步驟期間,亦可移除介電層46。如圖8中所示,接著使用習知材料移除技術來移除介電層62及44。
圖9展示在額外處理之後之裝置10的放大部分橫截面圖。根據一較佳實施例,在渠溝122之剩餘開口內在介電層28上方且沿半導體材料220之多個層的暴露部分形成磊晶插塞、單晶插塞、半導體材料插塞或半導體插塞區91。根據此實施例,插塞91包括具有與半導體層14相反之傳導性類型的磊晶半導體材料。在所示實施例中,插塞91係p型的。在一實施例中,插塞91具有在約1.0×1017
原子/cm3
與約1.0×1019
原子/cm3
之間的摻雜物濃度。在一替代實施例中,插塞91係非摻雜的。較佳地,使用減壓及選擇性磊晶生長技術來形成插塞91。
在一用於形成插塞91之實施例中,二氯矽烷源氣體與氫及HCl一起使用,此使得生長僅對於渠溝122之上部為選擇性的。在替代實施例中,使用矽烷、二矽烷或三氯矽烷源氣體。視所選生長溫度而定,將反應器壓力設定於自大約十托至大氣壓力的範圍內。在一實施例中,使用單晶圓反應器,反應器壓力約為20托。二氯矽烷之合適生長溫度處於自約950攝氏度至約1050攝氏度之範圍內。矽烷或二矽烷之合適生長溫度處於自約575攝氏度至約700攝氏度的範圍內。三氯矽烷之合適生長溫度處於自約1050攝氏度至約1175攝氏度的範圍內。在較高生長溫度之情況下需謹慎,以避免在裝置10之各種磊晶層或摻雜區內之摻雜物的不合需要之混合。在一實施例中,插塞91具有在約0.10微米至約0.60微米之範圍內的厚度。藉由實例,視插塞91之所要結構而調整厚度(例如,接近閉合、完全閉合或過生長)。
在一實施例中,當使用選擇性磊晶生長及二氯矽烷時,使用每分鐘約0.30微米之生長速率。當使用非選擇性技術及二氯矽烷時,使用在每分鐘約1.0微米至每分鐘約2.0微米之範圍內的生長速率。氣體流動速率視反應器組態而定,且藉由所需之生長條件及結構而設定。在一實施例中,在選擇性生長製程中使用以下氣體流動範圍以使用二氯矽烷在閉合組態中形成插塞91:氫為每分鐘30至40標準公升(slm),HCl為0.70至0.80slm,二氯矽烷為0.20至0.25slm。
根據一較佳實施例,插塞91經組態以封鎖渠溝122中之空隙29,且經進一步組態以在與使用介電/多晶或多晶填充技術之結構相比的最小缺陷及可忽略應力的情況下進行此。藉由抑制缺陷及應力,裝置10之可靠性及品質得以改良。在一實施例中,密封核心29處於約20托之真空下,在密封核心29中存在來自磊晶生長製程的一些氫。
在形成插塞91之後,多晶半導體層92形成為上覆於主表面18。藉由實例,層92包括約0.6微米至約0.9微米厚之多晶矽層,且使用習知沈積技術來形成。接著上覆於多晶半導體層92而形成大約1.0至2.0微米之平坦化光阻層93。
圖10為在使用平坦化或大量移除製程移除層93、層92,及插塞91之暴露部分或上部之後的裝置10之放大部分橫截面圖。藉由實例,將習知回蝕技術用於此移除步驟。在替代實施例中,使用化學機械平坦化技術。接著使用(例如)濕式化學蝕刻移除層40。接下來,介電層94形成為上覆於主表面18,且包括(例如)具有約0.05微米至約0.09微米之厚度的植入氧化物。接著上覆於主表面18而形成經圖案化之光阻層96,以為形成摻雜層26作準備。
根據一較佳實施例,接著將經圖案化之光阻層96用作遮罩而將摻雜層26之摻雜物引入或提供至在主表面18下方的半導體層14中。在一實施例中,使用高能量離子植入來植入摻雜層26之摻雜物。藉由實例,使用MeV範圍磷植入物,且約1.0×1012
原子/cm2
之植入劑量係足夠的。在此實施例中,層26之摻雜物濃度大於半導體層14的摻雜物濃度,以提供在通道45(圖1中所示)與n型層221之間具有降低之電阻的路徑。在一較佳實施例中,如圖10中所示,高能量植入將摻雜層26置放於主表面18下方,使得摻雜層26為次級表面。接著移除經圖案化之光阻層96。所植入之摻雜物接著經熱處理以使n型摻雜物擴散至半導體層14中至一所選深度。藉由實例,摻雜層26延伸至約2.0微米至約3.0微米的深度。根據一較佳實施例,在最終結構中,摻雜層26具有大於主體區31之深度的深度。在一替代實施例中,如下文所述,在引入主體區31之摻雜物之後,使用經組合之熱處理步驟。在一替代實施例中,在渠溝122形成之前,形成摻雜層26。藉由實例,在圖2中所示之硬遮罩112形成之前,形成摻雜層26。
圖11展示在稍後製造步驟處之裝置10的放大部分橫截面圖。在主表面18處引入或提供主體區31的p型摻雜物。根據一較佳實施例,主體區31橫向延伸以上覆於電荷補償渠溝22之全部或部分。亦即,主體區31至少覆蓋p型層222。藉由實例,使用離子植入,其中硼植入劑量為約1.0×1013
原子/cm2
且植入能量為約160KeV。在一替代實施例中,使用一系列硼植入物以形成主體區31,其中首先出現較輕劑量/較高能量植入物,接著其後出現逐漸增加劑量且逐漸減少能量的植入物。在另一實施例中,此次序為顛倒的。所植入之p型摻雜物經熱處理以使摻雜物擴散及/或活化摻雜物以形成區31。藉由實例,主體區31具有約1.0微米至約2.0微米的深度。
圖12為在完成形成控制或閘渠溝158之預備步驟之後之裝置10的放大部分橫截面圖。在一早期步驟中,上覆於介電層94而形成介電層98。藉由實例,介電層98包括約0.1微米至約0.2微米厚之氮化矽層,且使用習知技術來形成。接下來,一光阻層(未圖示)上覆於介電層98而沈積,且一開口形成用於控制渠溝158。接著移除層98及94之多個部分以暴露主表面18的一部分。接著移除該光阻層。接下來,控制渠溝158經形成為自主表面18延伸,大體中央定位於鄰近之電荷補償渠溝22之間。藉由實例,使用習知各向異性乾式蝕刻來形成控制渠溝158。藉由實例,控制渠溝158具有約0.4微米至約0.7微米之寬度,且具有大於主體區31之深度的深度。在一較佳實施例中,控制渠溝158具有大於摻雜區26的深度。在一實施例中,控制渠溝158具有約2.2微米至約3.2微米之深度。
圖13為在進一步處理之後之裝置10的放大部分橫截面圖。在一實施例中,薄的熱氧化物上覆於控制渠溝158之暴露表面而生長。接著移除此氧化物。亦移除介電層98。接下來,上覆於控制渠溝158之表面而形成閘介電層43。在一實施例中,閘介電層43包括氧化矽,且具有約0.05微米至約0.1微米之厚度。在另一實施例中,閘介電層43沿控制渠溝158之底部及下側壁部分為較厚的。諸如摻雜或非摻雜多晶矽層之導電層接著上覆於閘介電層43而沈積,且經部分移除以形成閘導電區57。舉例而言,閘導電區57包括約0.2微米之摻雜或非摻雜多晶矽。若閘導電區57最初未經摻雜,則此區隨後在源極區33形成期間被摻雜。在一實施例中,閘導電區57凹入至主表面18下方。共同地,控制渠溝158、閘介電層43及閘導電區57形成控制結構157。在一替代實施例中,在電荷補償渠溝22形成之前形成控制結構157。當關注熱預算對層221及222之摻雜物分布的影響時,使用此替代方法。摻雜區26之組態係足夠方便靈活的以支援任一製程序列。
接下來,一光阻層(未圖示)經沈積且圖案化以提供開口用於鄰近控制結構157而形成源極區33。接著使用(例如)磷或砷離子植入及退火步驟而形成源極區33。藉由實例,使用砷植入物,其中1.0×1015
原子/cm2
至約5.0×1015
原子/cm2
之劑量為足夠的。在1030攝氏度下,使用(例如)45秒之快速退火來活化此摻雜物。在此實施例中,在控制結構157之兩側上形成源極區33。
接下來,上覆於主表面18而形成層間介電區48。藉由實例,層間介電質48包括一經沈積之氧化物,且具有大約為約1.0微米之厚度。接著使用習知接觸光阻及蝕刻製程來形成接觸開口116,開口116上覆於並暴露主表面18的多個部分,如圖14中所示。在一較佳實施例中,接著使用各向異性蝕刻來移除半導體層14之鄰近源極區33且在主體區31及補償渠溝22上方的一部分。藉由實例,移除來自半導體層14之足夠材料以延伸至約源極區33之深度或更深。接著將額外摻雜物添加至主表面18之在主體區31及補償渠溝22上方的多個部分,以形成主體接觸區36。藉由實例,使用硼離子植入物,其中大約1.0×1015
原子/cm2
至約5.0×1015
原子/cm2
的植入劑量為足夠的。接著使用(例如)快速退火製程來活化所植入之摻雜物。接著沿該等側移除層間介電層48之多個部分以暴露源極區33的上表面部分(圖1中所示)。接著上覆於主表面18而形成源極接觸層63,且其與源極區33及主體區36兩者接觸,如圖1中所示。在一實施例中,源極接觸層63包括鈦/氮化鈦障壁層及上覆於該障壁層而形成的鋁矽合金層,或其類似者。上覆於如圖1中所示之半導體材料11的相對表面而形成汲極接觸層13,且其包括(例如)可軟焊金屬結構,諸如鈦鎳銀、鉻鎳金,或其類似者。
總而言之,已描述一種包含製造方法的新的切換裝置結構,該結構具有電荷補償渠溝區、渠溝控制結構及次級表面摻雜層,且將渠溝控制結構電耦合至電荷補償渠溝區。次級表面摻雜區提供次級表面主導電路徑,其將該導電路徑與應力及缺陷區域隔離。此改良裝置效能。另外,此設計簡化接觸電荷補償渠溝區之歐姆接觸結構的形成。
儘管已參考本發明之具體實施例描述且說明了本發明,但本發明並不意欲限於此等說明性實施例。熟習此項技術者將認識到,可在不脫離本發明之精神的情況下進行修改及變化。因此,預期本發明包含屬於附加申請專利範圍之範疇的所有此等變化及修改。
5...部分
10...切換裝置或單元
11...半導體材料
12...n型矽基板
13...導電層/汲極接觸層/汲極端子
14...半導體層
18...主表面
21...本徵層
22...區域化之電荷補償區/電荷補償填充渠溝
23...n型層
24...本徵層
25...p型層
26...次級表面摻雜層
27...本徵層
28...介電層
29...空隙或密封核心
31...主體或摻雜區
33...源極區
36...p型主體接觸區
40...介電層
43...閘介電層
44...介電層
45...傳導通道
46...介電層
48...層間介電區/層間介電質
57...導電閘區
62...介電層
63...源極接觸層/源極端子
72...開口
74...寬度
75...寬度
91...插塞結構/半導體插塞區
92...多晶半導體層
93...平坦化光阻層
94...介電層
96...經圖案化之光阻層
98...介電層
112...硬遮罩結構
116...接觸開口
122...渠溝
157...渠溝閘或控制結構/傳導閘區
158...控制或閘渠溝
220...半導體材料
221...n型半導體材料層/主傳導層
222...補償p型半導體材料層
圖1說明根據本發明之一實施例之半導體裝置的放大部分橫截面圖;及
圖2至圖14說明製造之各種階段處的圖1之半導體裝置的放大部分橫截面圖。
為了說明之簡單及清楚的目的,圖式中之元件不必按比例繪製,且不同圖式中之相同參考數字大體指示相同元件。另外,為了描述簡單之目的,可忽略熟知步驟及元件的描述及細節。如本文所使用,載流電極意謂載運電流通過裝置(諸如,MOS電晶體之源極或汲極、或者雙極電晶體之發射極或集極,或者二極體的陰極或陽極)的裝置元件,且控制電極意謂控制電流通過裝置(諸如,MOS電晶體之閘極或雙極電晶體之基極)的裝置元件。儘管該等裝置在本文中經解釋為某些N型通道裝置,但一般熟習此項技術者將瞭解,P型通道裝置及補充裝置根據本發明亦為可能的。為了圖式清楚之目的,裝置結構之摻雜區經說明為具有大體直線邊緣及精確角度轉角。然而,熟習此項技術者理解,歸因於摻雜物之擴散及活化,摻雜區之邊緣大體上並非直線且轉角並非精確角度。
另外,本描述之結構可具體化蜂巢式基極設計(其中主體區係複數個相異且單獨之蜂巢式區)或單一基極設計(其中主體區係以伸長圖案形成之單一區,該單一區通常以蛇形圖案或具有所連接附加物之中央部分形成)。然而,為了易於理解,貫穿本描述,本描述之裝置將描述為蜂巢式基極設計。應理解,預期本發明包含蜂巢式基極設計及單一基極設計兩者。
10...切換裝置或單元
11...半導體材料
12...n型矽基板
13...導電層/汲極接觸層/汲極端子
14...半導體層
18...主表面
22...區域化之電荷補償區/電荷補償填充渠溝
26...次級表面摻雜層
28...介電層
29...空隙或密封核心
31...主體或摻雜區
33...源極區
36...p型主體接觸區
43...閘介電層
45...傳導通道
48...層間介電區/層間介電質
57...導電閘區
63...源極接觸層/源極端子
91...插塞結構/半導體插塞區
157...渠溝閘或控制結構/傳導閘區
158...控制或閘渠溝
220...半導體材料
221...n型半導體材料層/主傳導層
222...補償p型半導體材料層
Claims (21)
- 一種半導體裝置,其包括:半導體材料之一主體,其具有一主表面及一豎直電荷補償結構,其中該豎直電荷補償結構包含一第一傳導性類型半導體材料之至少一個導電層及一第二傳導性類型半導體材料的至少一個補償層,其中該第二傳導性類型與該第一傳導性類型相反;該第二傳導性類型之一主體區,其形成在與該豎直電荷補償結構鄰近之半導體材料的該主體中;該第一傳導性類型之一源極區,其形成在鄰近該主體區處;一渠溝控制結構,其形成在該源極區及該主體區鄰近處,其中該源極區經插入在該渠溝控制結構與該豎直電荷補償結構之間,其中該渠溝控制結構經組態以在該主體區內形成一通道區;及該第一傳導性類型之一摻雜區,其經形成以與該主表面隔開並位於該主體區的下面,並經組態以將該通道區之一汲極端電連接至該至少一個導電層。
- 如請求項1之裝置,其進一步包括上覆於主表面並電耦合至該源極區、該主體區及該至少一個補償層之一導電層。
- 如請求項1之裝置,其中半導體材料之該主體中提供該主體區的一部分包括該第二傳導性類型。
- 如請求項1之裝置,其中半導體材料之該主體包括該第 一傳導性類型。
- 如請求項1之裝置,其中該豎直電荷補償結構包括一具有側壁及一下表面的一般豎直渠溝,且其中該至少一個導電層上覆並毗鄰於該等側壁及該下表面,且其中該至少一個補償層上覆於該導電層。
- 如請求項1之裝置,其中該主體區將該摻雜區與該主表面電隔離。
- 如請求項1之裝置,其進一步包括在該主體區中形成的該第二傳導性類型之一主體接觸區,其中該主體接觸區提供一歐姆接觸至該至少一個補償層。
- 一種半導體裝置,其包括:一具有一主表面之半導體區;一豎直電荷補償結構,其自該主表面延伸而形成在該半導體區中,其中該豎直電荷補償結構包含與該半導體區鄰接的具有一第一傳導性類型的一第一半導體層,及與該第一半導體層鄰接的具有與該第一傳導性類型相反之一第二傳導性類型的一第二半導體層,且其中該第一半導體層係一導電層,且其中該第二半導體層係一補償層;一渠溝控制結構,其形成在該半導體區中,並與該豎直電荷補償結構橫向相隔;一主體區,其鄰接該渠溝控制及該豎直電荷補償結構並在該渠溝控制結構與該豎直電荷補償結構之間,其中該主體區具有該第二傳導性類型,具其中該渠溝控制結 構經組態以形成在該主體區中的一通道區;一源極區,其上覆於該主體區之一部分,並與該渠溝控制結構鄰接;該第一傳導性類型之一摻雜區,其與該主表面隔開並位於該主體區的下面,且自該通道區之一汲極端延伸至該導電層;及一導電層,其上覆於該主表面,並電耦合至該源極區、該主體區及該補償層。
- 如請求項8之裝置,其進一步包括在該第二半導體層上面形成的一緩衝層。
- 如請求項8之裝置,其進一步包括形成為插入在該第一半導體層與該第二半導體層之間的一緩衝層。
- 如請求項8之裝置,其中該導電層與該源極區之豎直表面及水平表面接觸。
- 如請求項8之裝置,其進一步包括在與該主體區之若干部分中形成的該第二傳導性類型之一主體接觸區。
- 如請求項12之裝置,其中該主體接觸區上覆並形成一歐姆接觸至該補償層。
- 如請求項8之裝置,其中該半導體區包括該第一傳導性類型之一半導體基板及上覆於該半導體基板之該第二傳導性類型的一半導體層,且其中該主體區形成於該半導體層中。
- 如請求項8之裝置,其中該半導體區包括該第一傳導性類型之一半導體基板及上覆於該半導體基板之該第一傳 導性類型的一半導體層,且其中該摻雜區之摻雜物濃度高於該半導體層。
- 一種用於形成一半導體裝置之方法,其包括以下步驟:提供具有一主表面的半導體材料之一主體;在半導體材料之該主體中形成自該主表面延伸的一豎直電荷補償結構,其中該豎直電荷補償結構包含一第一傳導性類型之至少一個導電層及與該第一傳導性類型相反之一第二傳導性類型的至少一個補償層;在半導體材料之該主體中形成一渠溝控制結構;在半導體材料之該主體中形成該第一傳導性類型的一摻雜區;在半導體材料之該主體中形成該第二傳導性類型的一主體區,其中該主體區上覆於該摻雜區;及形成鄰近該主體區的該第一傳導性類型之一源極區,其中該源極區經插入在該渠溝控制結構與該豎直電荷補償結構之間,且其中該渠溝控制結構經組態以在該主體區內形成一通道區,且其中該摻雜區在該通道區之一汲極端至該導電層之間延伸。
- 如請求項16之方法,其進一步包括形成上覆於該主表面並電耦合至該源極區、該主體區及該補償層之一導電層的步驟。
- 如請求項16之方法,其中該提供半導體材料之該主體的步驟包含:提供半導體材料的一主體,其中該豎直電荷補償結構包括一具有側壁及一下表面的一般豎直渠溝, 且其中該至少一個導電層上覆於該等側壁及該下表面,且其中該至少一個補償層上覆於該至少一個導電層。
- 如請求項16之方法,其進一步包括下列步驟:在該主體區中形成該第二傳導性類型之一主體接觸區的步驟,其中該主體接觸區上覆於該豎直電荷補償結構的一上部;及提供一導電層,其上覆於該主表面並電耦合至該源極區、該主體接觸區以及該至少一個補償層。
- 如請求項16之方法,其中該形成該渠溝控制結構之步驟發生在該形成該豎直電荷補償結構的步驟之後。
- 如請求項16之方法,其中該形成該渠溝控制結構之步驟發生在該形成該豎直電荷補償結構的步驟之前。
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KR20100029702A (ko) | 2010-03-17 |
US20100059814A1 (en) | 2010-03-11 |
US8372716B2 (en) | 2013-02-12 |
KR20150127007A (ko) | 2015-11-16 |
TW201017882A (en) | 2010-05-01 |
CN101673764A (zh) | 2010-03-17 |
US7960781B2 (en) | 2011-06-14 |
US20110207277A1 (en) | 2011-08-25 |
KR101626290B1 (ko) | 2016-06-01 |
TW201521206A (zh) | 2015-06-01 |
TWI580052B (zh) | 2017-04-21 |
KR101613092B1 (ko) | 2016-04-19 |
CN101673764B (zh) | 2013-03-13 |
HK1141136A1 (en) | 2010-10-29 |
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