TWI491001B - 積體電路總成 - Google Patents

積體電路總成 Download PDF

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Publication number
TWI491001B
TWI491001B TW099106499A TW99106499A TWI491001B TW I491001 B TWI491001 B TW I491001B TW 099106499 A TW099106499 A TW 099106499A TW 99106499 A TW99106499 A TW 99106499A TW I491001 B TWI491001 B TW I491001B
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Taiwan
Prior art keywords
integrated circuit
metal
metal layer
layer
package
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TW099106499A
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English (en)
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TW201044535A (en
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Ken M Lam
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Atmel Corp
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Publication of TW201044535A publication Critical patent/TW201044535A/zh
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    • H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
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  • Engineering & Computer Science (AREA)
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  • Condensed Matter Physics & Semiconductors (AREA)
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  • Wire Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

積體電路總成
本發明大體而言係關於積體電路封裝，且更具體而言係關於一種可選擇路徑陣列金屬積體電路封裝。
大多數電子或電腦化裝置具有包含一個或多個積體電路(通常稱作「晶片」)之電子電路。此等積體電路通常係相對大或複雜之電路，例如電腦處理器、記憶體陣列或其他此等裝置。積體電路中之實際電路通常係使用形成於一基板上之半導體裝置(例如形成於一矽基板上之經摻雜矽電晶體、電阻器及電容器)而形成。
一基板與形成於該基板上之電路之組合通常稱作一「晶粒」，且通常具有如此小以致於藉助肉眼不可能看見個別電子組件或電路跡線之電路。由於形成於該基板上之電路元件之小尺寸，該晶粒亦相對易碎且可容易藉由刮擦而損壞。以高功率運作之某些電路(例如高效能處理器或控制器)亦生產比積體電路晶粒可驅散之熱更多之熱，且因此在沒有驅散所產生之熱之某些構件之情形下為不可使用。
出於此等及其他原因，幾乎所有積體電路晶粒以封裝形式提供至裝置(例如電腦或蜂巢式電話)製造商，該等封裝經設計以保護該積體電路同時使其易於連接至其他電路。積體電路封裝通常包含接針、焊料球或經由小引線耦合至晶粒之電路之各個部分之其他電導體，從而實現自該封裝之外部至晶粒之電路的簡單且可靠之電連接。此等封裝提供與電連接不相關之各種功能，包含：自該晶粒將熱帶走至電路封裝之外部且可至一外部散熱器，及保護相對易碎之晶粒免受環境因素(例如磨損、濕氣及震動)之影響。
但是，封裝一積體電路晶粒本身具有數個挑戰。雖然一典型積體電路晶粒太小而不能形成至未經專門化之設備的連接，但仍可期望將經封裝之晶粒之尺寸保持為小以使得其可容易地整合至小型或可攜式電子裝置中。封裝之成本係一重要關注問題，此乃因提供良好熱管理、對晶粒之良好保護及至外部電路之簡單連接性之複雜封裝可係一經封裝之積體電路之成本之一重要部分。
因此期望以解決此等商業需要之一方式封裝積體電路晶粒。
本發明之一個實例性實施例包括一積體電路總成，其包含：一積體電路晶粒；及一可選擇路徑金屬層，其包括將複數個線接合墊鏈接至複數個外部連接墊之金屬跡線以使得該等金屬跡線在晶粒區下方可選擇路徑。一不導電黏合劑層將該積體電路晶粒耦合至該可選擇路徑金屬層，且複數個線接合將該積體電路晶粒上之電路鏈接至該可選擇路徑金屬層中之線接合墊。一覆蓋充填材料封包該積體電路晶粒、該複數個線接合及該封裝之外部連接墊之一個側。複數個焊料球形成於該複數個外部連接墊上。
在本發明之實例性實施例之以下實施方式中，藉助圖式及圖解說明對本發明之具體實例性實施例做出參考。充分詳細地闡述此等實例以使得熟習此項技術者能夠實踐本發明，且此等實例用於圖解說明本發明可如何應用至各種目的或實施例。本發明之其他實施例存在且屬於本發明之範疇內，且可在不違背本發明之標的或範疇之情形下做出邏輯、機械、電及其他改變。
儘管本文所闡述之本發明之各種實施例之特徵或限制對其併入於其中之實例性實施例為必要，但該等特徵或限制並不限制本發明之其他實施例或作為一整體之本發明，且對本發明、其元件、運作及應用之任何參考不限制作為一整體之本發明而是僅用於界定此等實例性實施例。因此以下實施方式不限制本發明之範疇，本發明之範疇僅由隨附申請專利範圍界定。
在一個實例性實施例中，本文所揭示之發明包括一積體電路總成，其包括：一積體電路晶粒；及一可選擇路徑金屬層，其包括將複數個線接合墊鏈接至複數個外部連接墊之金屬跡線，以使得該等金屬跡線在晶粒區下方可選擇路徑。一不導電黏合劑層將該積體電路晶粒耦合至該可選擇路徑金屬層，且複數個線接合將該積體電路晶粒上之電路鏈接至該可選擇路徑金屬層中之線接合墊。一覆蓋充填材料封包至少該積體電路晶粒及該複數個線接合及該封裝之外部連接墊之一個側。在一進一步實例中，複數個焊料球形成於該複數個外部連接墊上。
用於積體電路之封裝通常經設計以保護一相對易碎之積體電路晶粒免受其環境影響，以提供該晶粒與外部電路之間的可靠電連接，且在諸多情形下自該晶粒帶走熱。設計該封裝既要計及實體約束(例如此等實體約束)，亦要計及封裝製程及封裝該等晶粒所需要之設備之成本及複雜性。
圖1a至圖1g中圖解說明封裝晶粒之一個解決方案，其顯示一犧牲金屬基底條帶封裝製程。此實例性製程係使用一金屬基底條帶開始，將封裝物形成至該金屬基底條帶上，且完成之封裝物最後自該金屬基底條帶分隔開來。
在圖1a中，一銅基底條帶101具有施加至該銅基底條帶之表面之一電鍍抗蝕劑圖案，如102處所顯示。該銅基底條帶之底側亦具有電鍍抗蝕劑塗層之一未經圖案化之固體層，以防止至該底表面上之任一電鍍金屬沈積。頂側上之抗蝕劑圖案允許圖1b中所顯示之一電鍍步驟將電鍍材料沈積於經圖案化之抗蝕劑開口中以形成線接合金屬墊103及晶粒附接墊104。在各種實施例中，電鍍材料係一個或多個金屬層，例如金、鈀、鎳及銅。鈀及金極適於稍後將接合線路之金屬層表面，而例如鎳或銅之金屬則由於其高導電性及相對低之成本而經常用於電鍍步驟之本體。金亦具有抗氧化性，且因此經常用於金屬層之外部電鍍，以防止下伏之可軟銲金屬之氧化。
一旦完成該金屬電鍍製程，即將圖1a中所施加之抗蝕劑材料102在圖1c中移除，從而僅留下在圖1b中形成於銅條帶101上之金屬墊103及104。此處，區域104形成用於附接積體電路晶粒之一基底，如圖1d中所顯示。(例如)藉由使用一環氧樹脂或其他黏合劑，將晶粒105附接至金屬電鍍區域104。
然後在稱作一線接合製程之過程中藉由使用細線將積體電路晶粒上之各個電路連接至在電鍍製程期間形成之金屬墊103。如圖1e中所顯示，線106將積體電路晶粒上之各個電觸點連接至金屬墊103，以使得金屬墊103可最終耦合至完成之封裝外部之電連接以使積體電路耦合至外部電路。
在晶粒經由線接合線耦合至電鍍製程中所形成之金屬墊之後，用一包覆成型材料(如圖1f中107處所顯示)覆蓋該總成以封包並保護該晶粒及佈線及金屬墊。此包覆成型材料係一不導電材料，例如環氧樹脂或另一適合之材料。
然後，處理該經封包之總成以自該總成移除犧牲金屬基底條帶101，從而形成圖1g中所顯示之晶粒總成。藉由一化學蝕刻劑將此實例中之銅基底條帶自該晶粒總成移除，該化學蝕刻劑有效地移除銅但不附接至用於經電鍍之金屬墊103及104中之曝露的金屬或與其反應。然後，可使用焊料或導電黏合劑化合物或通過其他手段將圖1g中所顯示之總成中之金屬墊103及104耦合至下一水平板總成。
支撐該晶粒之金屬墊104係用以形成墊103之相同金屬，但圖1b之電鍍製程中所形成之金屬墊均不連接至任一其他金屬墊。圖1e之106處所顯示之接合線將該晶粒之電路耦合至金屬墊103，從而實現至外部電路之連接。由於在不冒因偶然接觸而使一個線電耦合至另一線之危險之情形下該等接合線不可彼此交叉，因此此封裝系統不提供使線交叉或選擇路徑至不同墊之能力。
本發明之一個實例性實施例藉由提供包含藉由圖案電鍍而形成之一可選擇路徑層之一犧牲金屬基底條帶封裝製程來解決圖1之總成之某些問題。此在為電路跡線選擇路徑時提供經改良之靈活性以促進外部連接。
圖2a及圖2b顯示包含一球柵格陣列(BGA)格局之一經圖案電鍍之犧牲金屬條帶晶粒封裝，其與本發明之一實例性實施例一致。亦常用無焊料球之其他封裝格局。在圖2a中，該晶粒封裝係自圖1g中所顯示之實例性晶粒封裝倒置，且包含替代圖1中該晶粒安裝至其上的大墊104之一可選擇路徑金屬層。
此處，導電跡線204之一可選擇路徑金屬層形成於犧牲金屬層上，包含形成於該晶粒安裝於其中的區中。該等跡線經由至金屬線接合墊203之線接合連接耦合至該晶粒，該等金屬線接合墊經由金屬層導電跡線204耦合至封裝墊201。焊料球202此處在焊料遮罩層206中之開口中形成於封裝墊201上，以供連接至外部電路。為防止該晶粒(其通常係矽材料)電短路至封裝墊金屬201及金屬跡線204，使用一不導電晶粒附接黏合劑材料205(例如環氧樹脂化合物)用於晶粒附接。此提供由於該金屬層中之可選擇路徑金屬跡線而在組態中具有增強之靈活性之一小型有效封裝。
圖2b中顯示圖2a之實例性封裝之一仰視圖。此處，顯示導電跡線204將各個焊料球202鏈接至各個金屬線接合墊203，以使得自該晶粒至線接合墊203之一線接合連接經由導電跡線204電耦合至焊料球202。某些焊料球(例如電力及接地連接)可連接至可選擇路徑金屬層上之多個墊以便可在該晶粒上之各個電路與外部電源之間形成多個電力及接地連接。在圖2b中於墊207處顯示一實例，該等墊經由該可選擇路徑金屬層上之金屬跡線彼此耦合且耦合至一單個焊料球。
圖3a至圖3f圖解說明使用一犧牲金屬條帶積體電路封裝製程形成具有一可選擇路徑金屬層之一晶粒封裝之一方法，其與本發明之一實例性實施例一致。在圖3a中，犧牲金屬條帶係一銅金屬基底301，且(例如)藉由使用如相對於圖1之實例更詳細闡述之一光可界定電鍍抗蝕劑材料及光遮罩，於該條帶上形成一可選擇路徑或經圖案化之金屬電路層302。此處之金屬層具有呈一金屬堆疊形式之一個或多個金屬層，其中不同類型之金屬可用於不同層中以提供不同性質。
舉例而言，在一個實施例中，包括如圖2a及2b中所圖解說明之線接合墊特徵203、封裝墊特徵201及選擇路徑跡線特徵204之金屬可選擇路徑層302在頂表面上包含一線可接合金屬(例如，鈀、銀或金)。一擴散障壁金屬層(例如鎳)緊接著位於該線可接合金屬層下面，且一導電金屬(例如銅)其次。於彼下面形成一焊料擴散障壁金屬(例如鎳)，且底層係一防氧化金屬(例如，銀、金或鈀)。在替代性實施例中，更多層、其他層或僅來自以上實例之選擇層包含於可選擇路徑金屬層302中。
經由一不導電環氧樹脂層303或經由另一不導電黏合劑材料將晶粒附接至圖3b中之可選擇路徑金屬層。因此該晶粒不直接電連接至在該晶粒下方選擇路徑之任何可選擇路徑金屬跡線，而是替代地經由接合線304耦合至可選擇路徑金屬層。將接合線304附接至各個墊305，該等墊經由該可選擇路徑金屬層耦合至外部電路連接。
然後，用一包覆成型材料306如圖3c中所顯示包封該總成，該包覆成型材料保護該晶粒及該等接合線免受磨損、濕氣及其他環境因素之影響。然後，(例如)藉由化學蝕刻如圖3d(顛倒顯示)中所顯示移除犧牲金屬條帶銅基底。此留下可選擇路徑金屬層及自圖3c中所施加之包覆成型曝露之晶粒附接環氧樹脂。在某些實例中，該犧牲金屬條帶係一長或連續之金屬條帶，在接近該封裝製程之結束時(例如)藉由鋸開該金屬條帶或該晶粒封裝將該長或連續之金屬條帶切割成個別晶粒封裝，如圖5中所顯示。
將焊料球施加至該可選擇路徑金屬層之曝露的焊料球區域309(如圖3d中所顯示)。在圖3e中，在各個點處施加焊料終止層307以在焊料球附接至墊區(如圖3f中之308處所顯示)期間約束焊料流至金屬跡線204上。
圖4a及圖4b呈現使用一全焊料遮罩層替代如圖3e及圖3f中所採用之焊料終止層來施加焊料球之一替代方法。在圖4a中，將一永久焊料遮罩401施加至積體電路封裝之除封裝金屬墊上方將接納焊料球(如圖4b中之402處所顯示)之區以外的整個底側。此焊料遮罩層可具有一光可界定或非光可界定特性、呈油墨或乾燥膜形式，且可在各種實施例中使用篩選或層壓製程施加此焊料遮罩層。
如先前在圖3中所呈現之實例中所論述，可在一長或連續之犧牲金屬條帶基底層上形成一系列積體電路總成，例如圖5中所顯示。然後，在積體電路封裝生產之最後階段中(例如)藉由鋸開將個別積體電路封裝501彼此分隔開。
因此本文所闡述之可選擇路徑金屬層積體電路總成技術提供優於先前技術積體電路安裝技術(例如圖1中所圖解說明之實例)之各種各樣之優點，包含提供全層選擇路徑能力之優點。一典型BGA封裝使用一有機基板用於選擇路徑。消除圖2至圖4中所圖解說明之可選擇路徑金屬層積體電路實例中之一有機基板使得此等實例顯著地比先前技術便宜，且大大降低成品積體電路總成之高度，此允許更薄之裝置(例如蜂巢式電話、個人數位助理裝置、全球定位系統及其他可攜式或手持式電子裝置)。
雖然本文已圖解說明且闡述了具體實施例，但熟習此項技術者將瞭解，達成相同目的、結構或功能之任何配置均可替代所顯示之具體實施例。本申請案意欲涵蓋本文所闡述之本發明之實例性實施例之任何修改或變化形式。本發明意欲僅由申請專利範圍及其等效內容之全部範疇限制。
101．．．銅基底條帶
102．．．抗蝕劑材料
103．．．金屬墊
104．．．金屬墊
105．．．晶粒
106．．．線
107．．．包覆成型材料
201．．．封裝墊
202．．．焊料球
203．．．線接合墊
204．．．導電跡線
205．．．不導電晶粒附接黏合劑材料
206．．．焊料遮罩層
207．．．墊
301．．．銅金屬基底
302．．．金屬可選擇路徑層
303．．．不導電環氧樹脂層
304．．．接合線
305．．．墊
306．．．包覆成型材料
307．．．焊料終止層
308．．．墊區
309．．．焊料球區域
401．．．永久焊料遮罩
402．．．焊料球
501．．．積體電路封裝
圖1a至圖1g顯示使用一犧牲金屬基底基板載體製作之一實例性積體電路總成，其與一先前技術實例一致；
圖2a顯示具有一可選擇路徑金屬層之一積體電路總成之一側視圖，其與本發明之某些實施例一致；
圖2b係具有圖2a之一可選擇路徑金屬層之積體電路總成之一仰視圖，其與本發明之一實例性實施例一致；
圖3a至圖3f圖解說明使用一犧牲基底層及局部焊料終止層形成具有一可選擇路徑金屬層之一積體電路總成之一實例性方法，其與本發明之一實例性實施例一致；
圖4a至圖4b圖解說明使用一犧牲基底層且使用一全焊料遮罩形成具有一可選擇路徑金屬層之一積體電路總成之一替代方法，其與本發明之一實例性實施例一致；及
圖5係形成於一犧牲金屬條帶基底層上之一系列積體電路總成之一俯視圖，其與本發明之一實例性實施例一致。
402．．．焊料球

Claims (19)

  1. 一種積體電路總成(assembly)，其包括：一積體電路晶粒(die)；一可選擇路徑(routable)金屬層，其包括可選擇路徑金屬跡線(traces)，該等可選擇路徑金屬軌跡經組態以將線接合墊(wire bond pads)耦接至封裝墊(package pads)，該等封裝墊經組態為該積體電路晶粒之一安裝座(mount)，該可選擇路徑金屬層包含至少一對金屬跡線，其使一對線接合墊直接耦接至一另一對，而不需要該積體電路晶粒裝於其上的一區(area)下方(under)之一中間(intervening)封裝墊；一電性上不導電黏合劑(electrically nonconductive adhesive)層，其將該積體電路晶粒耦接至該可選擇路徑金屬層，俾使該積體電路晶粒不直接電性連接至佈線(route)於該積體電路晶粒安裝於其上的該區下方之該等金屬跡線；及複數個接合線(bond wires)，該等接合線將該積體電路晶粒上之電路鏈接至該可選擇路徑金屬層中之該等線接合墊，在該積體電路晶粒與該可選擇路徑金屬層之間形成電性連接。
  2. 如請求項1之積體電路總成，其進一步包括一連續犧牲金屬條帶(strip)，其上形成複數個晶粒封裝件(die packages)，每一晶粒封裝件包含一積體電路晶粒及一可選擇路徑金屬層。
  3. 如請求項1之積體電路總成，其進一步包括一覆蓋充填(overfill)材料，其囊封(encapsulating)至少該積體電路晶粒及該複數個接合線。
  4. 如請求項3之積體電路總成，其中該覆蓋充填材料進一步填充該可選擇路徑金屬層中之該等金屬跡線之間的至少部分間隙(some gaps)。
  5. 如請求項1之積體電路總成，其中複數個焊料球(solder ball)形成於該可選擇路徑金屬層之暴露(exposed)焊料球區域(region)上。
  6. 如請求項5之積體電路總成，其中焊料終止層(solder stop)或焊料遮罩(rnask)中之至少一者用以限制焊料，以在將該等焊料球附接(attaching)至該可選擇路徑金屬層的該暴露焊料球區域期間避免焊料流至該等金屬跡線上。
  7. 如請求項1之積體電路總成，其中該等金屬跡線佈線於在其上該積體電路晶粒以黏合方式附接(adhesively attached)至該可選擇路徑金屬層之該區下方。
  8. 如請求項7之積體電路總成，其中該電性上不導電黏合劑層填充在佈線於該可選擇路徑金屬層中的兩個或更多個金屬跡線之間的間隙(gap)，該可選擇路徑金屬層係在於其上該積體電路晶粒以黏合方式附接至該可選擇路徑金屬層之該區下方。
  9. 如請求項1之積體電路總成，其中該可選擇路徑金屬層包括在一金屬堆疊(stack)中的金屬層，該等金屬層包 括：一上表面(top surface)，包含一可線接合金屬(wire-bondable metal)，該可線接合金屬係選自由下列組成之群組：鈀(palladium)及銀，一擴散障壁(diffusion barrier)金屬層，其包含緊接在該上表面之下的鎳，一傳導金屬層，其包含緊接在該擴散障壁金屬層之下的銅，一焊料擴散障壁金屬層，其包含在該傳導金屬層之下的鎳，及一底層(bottom layer)，其包含一防氧化金屬(oxidation prevention metal)層，該防氧化金屬層係選自由下列組成之群組：鈀及銀。
  10. 如請求項5之積體電路總成，其中該可選擇路徑金屬層的該暴露焊料球區域包含一封裝墊。
  11. 如請求項1之積體電路總成，其中該等金屬跡線經組態以將該等線接合墊的一子集(subset)耦接至一另一子集，並耦接至連接於一外部電源(power source)之一封裝墊，俾使複數個電力(power)及接地連接提供於該積體電路晶粒上的電路及該外部電源之間。
  12. 一種積體電路總成，其包括：一積體電路晶粒；一可選擇路徑金屬層，其包括金屬跡線，該等金屬跡線經組態以將線接合墊耦接至封裝墊，該可選擇路徑金 屬層包含至少一對金屬跡線，其使一對線接合墊直接耦接至一另一對，而不需要該積體電路晶粒安裝於其上的一區下方之一中間封裝墊，該等封裝墊經組態以用於安裝該積體電路晶粒；複數個焊料球，其形成於該等可選擇路徑金屬層之暴露焊料球區域上；及一陶瓷包裝件(encasing)，其經組態以包裝該積體電路總成。
  13. 如請求項12之積體電路總成，其中該複數個焊料球將該積體電路總成電耦合至一印刷電路板。
  14. 如請求項12之積體電路總成，其中該可選擇路徑金屬層包含金屬層，該等金屬層包含：一上表面，其包含一可線接合金屬，該可線接合金屬係選自由下列組成之群組：鈀及銀，一擴散障壁金屬之層，其緊接在該上表面之下，該擴散障壁金屬包含鎳，一傳導金屬之層，其緊接在該擴散障壁金屬之層之下，該傳導金屬包含銅，一焊料擴散障壁金屬之層，其在該傳導金屬之層之下，該焊料擴散障壁金屬包含鎳，及一防氧化金屬之層，其作為一底層，該防氧化金屬係選自由下列組成之群組：鈀及銀。
  15. 如請求項12之積體電路總成，其中該可選擇路徑金屬層的該暴露焊料球區域包含一封裝墊。
  16. 如請求項12之積體電路總成，其中該等金屬跡線經組態以用於將該等線接合墊之一子集耦接至一另一子集，並耦接至連接於一外部電源之一封裝墊，俾使複數個電力及接地連接提供於該積體電路晶粒上的電路及該外部電源之間。
  17. 如請求項16之積體電路總成，其中一或多個焊料球連接至該外部電源，並連接至耦接於一另一者的該等線接合墊，俾使該複數個電力及接地連接提供於該積體電路晶體上的電路及該外部電源之間。
  18. 一種積體電路總成，其包含：一積體電路晶粒；及一可選擇路徑金屬層，其包含金屬跡線，該等金屬跡線經組態以將線接合墊耦接至封裝墊，該等封裝墊經組態以作為該積體電路晶粒之一安裝座，該可選擇路徑金屬層包含至少一對金屬跡線，其使一對線接合墊直接耦接至一另一對，而不需要該積體電路晶粒安裝於其上的一區下方之一中間封裝墊。
  19. 如請求項18之積體電路總成，其包含：複數個焊料球，其形成於該等封裝墊上的暴露焊料球區域上，該複數個焊料球包含連接至一外部電源及附接至一封裝墊的一焊料球，該封裝墊利用該等金屬跡線耦接至該等線接合墊之一子集，俾使電性及接地連接提供至該積體電路晶粒上的電路，該積體電路晶粒上的該電路連接至該等線接合墊的該子集。
TW099106499A 2009-03-06 2010-03-05 積體電路總成 TWI491001B (zh)

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