TWI485809B - 互補式金氧半導體裝置及製作方法 - Google Patents

互補式金氧半導體裝置及製作方法 Download PDF

Info

Publication number
TWI485809B
TWI485809B TW101148608A TW101148608A TWI485809B TW I485809 B TWI485809 B TW I485809B TW 101148608 A TW101148608 A TW 101148608A TW 101148608 A TW101148608 A TW 101148608A TW I485809 B TWI485809 B TW I485809B
Authority
TW
Taiwan
Prior art keywords
mos device
metal
layer
type mos
gate
Prior art date
Application number
TW101148608A
Other languages
English (en)
Other versions
TW201327724A (zh
Inventor
Sheng Chen Chung
Ming Zhu
Harry Hak-Lay Chuang
Bao Ru Young
Wei Cheng Wu
Chia Ming Liang
Sin Hua Wu
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201327724A publication Critical patent/TW201327724A/zh
Application granted granted Critical
Publication of TWI485809B publication Critical patent/TWI485809B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008Making conductor-insulator-semiconductor electrodes
    • H01L21/28017Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28088Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being a composite, e.g. TiN
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232Field-effect technology
    • H01L21/8234MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568Lateral single gate silicon transistors
    • H01L29/66575Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/511Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51Insulating materials associated therewith
    • H01L29/517Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007Multistep manufacturing processes
    • H01L29/66075Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409Unipolar field-effect transistors
    • H01L29/66477Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76Unipolar devices, e.g. field effect transistors
    • H01L29/772Field effect transistors
    • H01L29/78Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7848Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being located in the source/drain region, e.g. SiGe source and drain

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Description

互補式金氧半導體裝置及製作方法
本發明係有關於金氧半導體裝置及其製作方法,且特別是有關於一種互補式金氧半導體裝置及其製作方法。
金氧半導體(Metal-Oxide-Semiconductor,MOS)裝置為積體電路的基本元件,現有的金氧半導體裝置通常具有一閘極,其包括p型或n型雜質摻雜的多晶矽,其摻雜方式可使用例如離子佈植或熱擴散。此閘極的功函數可調整至矽的能帶邊緣(band-edge)。對一n型金氧半導體(n-type Metal-Oxide-Semiconductor,NMOS)裝置,其功函數可調整至接近矽的傳導帶。對一p型金氧半導體(p-type Metal-Oxide-Semiconductor,PMOS)裝置,其功函數可調整至接近矽的價電帶。多晶矽閘極的功函數調整可藉由選定適當雜質達成。
具有多晶矽閘極的金氧半導體裝置可表現載子空乏效應(carrier depletion effect),即多晶矽閘極空乏效應(poly depletion effect)。此多晶矽閘極空乏效應在所加電場將載子由閘極介電層附近的閘極區域清除時發生,形成空乏層。在一n型多晶矽層中,此空乏層包括離子化之非移動施體位址(ionized non-mobile donor sites),而在一p型摻雜多晶矽層中,此空乏層包括離子化之非移動受體位址(ionized non-mobile acceptor sites)。此空乏效應造成閘極介電層的有效厚度上升,使得在半導 體表面反轉層(inversion layer)的形成更加困難。
多晶矽閘極空乏的問題可藉由形成金屬閘極或金屬矽化物閘極解決,其中使用在n型金氧半導體裝置及p型金氧半導體裝置的金屬閘極亦可具有能帶邊緣的功函數。由於n型金氧半導體裝置及p型金氧半導體裝置對功函數具有不同需求而使用雙閘極互補式金氧半導體裝置(dual-gate CMOS),其可使用一後閘極製程(gate-last approach)形成。
此後閘極製程通常包括形成p型金氧半導體裝置及n型金氧半導體裝置兩者之虛設閘極(dummy gate)的步驟。此p型金氧半導體裝置及n型金氧半導體裝置的虛設閘極隨後被移除,以不同功函數的金屬填入p型金氧半導體裝置及n型金氧半導體裝置之虛設電極留下的開口。
本發明一實施例提供一種互補式金氧半導體裝置的製作方法,包括:形成一p型金氧半導體裝置,包括:形成一閘極介電層於一半導體基板上之p型金氧半導體區域;形成一第一含金屬層於該p型金氧半導體裝置區域之該閘極介電層上;以一含氧製程氣體實施一處理於該p型金氧半導體區域之該第一含金屬層;以及形成一第二含金屬層於該p型金氧半導體裝置區域之該第一含金屬層上方,其中該第二含金屬層的功函數低於矽之中間能隙功函數,其中該第一含金屬層及該第二含金屬層形成該p型金氧半導體裝置之閘極。
本發明另一實施例提供一種互補式金氧半導體裝置,包括:一p型金氧半導體裝置包括一第一閘極,其中該第一閘極包括:一閘極介電層設置於一半導體基板上;一第一含金屬層設置於該閘極介電層上,其中該第一含金屬層包含氧;以及一第二含金屬層設置於該第一含金屬層上,其中該第二含金屬層的功函數小於矽之中間能隙功函數。
為讓本發明之上述和其他目的、特徵、和優點能更明顯易懂,下文特舉出較佳實施例,並配合所附圖式,作詳細說明如下:
本發明實施例的製作與使用如下所述。需要注意的是,上述實施例提供數個可應用的發明概念在各種特定背景下的具體實現,這些討論的特定實施例僅供說明之用,並非用以限定本發明。
根據本發明各實施例,提供一種互補式金氧半導體裝置及其製作方法,說明形成此互補式金氧半導體裝置的中間步驟,並討論各實施例的不同。相同的元件符號在各個圖及實施例中用以標示相同的元件。
第1~10圖為一系列剖面圖,用以說明根據本發明數實施例之互補式金氧半導體裝置的數個中間製作步驟。參見第1圖,提供基板20,其可由一半導體材料例如矽、矽化鍺(SiGe)等形成。淺溝渠隔離(shallow trench isolation)21形成於基板20,可用以定義主動區104及204。主動區104位於n型金氧半導體裝置區域100內, 主動區204位於p型金氧半導體裝置區域200內。界面層22形成於基板20上,界面層22可包括化學氧化物、熱氧化物、矽氮氧化物等,並可藉由氧化基板20形成。
數層24、26、28及30隨後形成,並延伸至n型金氧半導體裝置區域100及p型金氧半導體裝置區域200。介電層24形成於界面層22上。根據一些實施例,介電層24包括氧化矽、氮化矽或前述之積層物。在其它實施例中,介電層24由高介電常數材料形成,因而在描述時也可視為高介電常數層24。高介電常數層24可具有一大於約7.0的k值,且可包括金屬氧化物或鉿(Hf)、鋁(Al)、鋯(Zr)、鑭(La)、鎂(Mg)、鋇(Ba)、鈦(Ti)、鉛(Pb)之矽化物或前述之組合。舉例而言,此材料可包括MgOx 、BaTix Oy 、BaSrx Tiy Oz 、PbTix Oy 、PbZrx Tiy Oz 等,其中X及Y的數值介於0至1。此高介電常數層24的厚度可介於約1nm至約10nm。然而,本技術領域中具有通常知識者應可理解本說明書中述及的尺寸皆為例示之用,可改為不同數值。介電層24的形成方法可包括分子束沈積法(Molecular-Beam Deposition,MBD)、原子層沈積法(Atomic Layer Deposition,ALD)、物理氣相沈積法(Physical Vapor Deposition,PVD)等。
在介電層24上形成一中間能隙含金屬層26。在一些實施例中,中間能隙含金屬層26具有一中間能隙功函數,其可接近矽之傳導帶與價電帶的中間能階(mid-level)。矽的傳導帶及價電帶分別為5.17eV及4.05eV,因此,矽的傳導帶及價電帶的中間能階約為 4.6eV。在一些實施例中,此中間能隙功函數含金屬層26介於約4.5eV至4.7eV。在一些實施例中,中間能隙含金屬層26包括例如氮化鈦(TiN)。在其它實施例中,中間能隙含金屬層26的材料包括例如含鉭材料及/或含鈦材料例如碳化鉭(TaC)、氮化鉭(TaN)、氮化鋁鉭(TaAlN)、氮化矽鉭(TaSiN)、氮化碳鉭(TaCN)或前述之組合。
虛設多晶矽層28及硬罩幕層30相繼形成。虛設多晶矽層28的厚度可介於約30nm至約100nm,使用不同厚度亦可。硬罩幕層30可包括介電材料例如氮化矽、氧化矽、氮氧化矽、碳化矽等。
第2圖顯示了第1圖中堆疊層的圖案化結果,使閘極堆疊138形成於n型金氧半導體裝置區域100,閘極堆疊238形成於p型金氧半導體裝置區域200,其中閘極堆疊138及238中的膜層為第1圖中對應層的剩餘部份。閘極堆疊138包括界面層122、介電層124、中間能隙含金屬層126、虛設多晶矽層128及硬罩幕層130,閘極堆疊238包括界面層222、介電層224、中間能隙含金屬層226、虛設多晶矽層228及硬罩幕層230。
第3圖分別顯示了n型金氧半導體裝置區域100中n型金氧半導體裝置102及p型金氧半導體裝置區域200中p型金氧半導體裝置202的部份構件之形成。這些構件可包括源極/汲極延伸區域142及242、閘極間隔物143及243、源極/汲極區域144及244、及源極/汲極矽化物146及246。接觸窗蝕刻終止層(Contact Etch Stop Layer, CESL)140,其可具有一拉伸應力(tensile stress),形成於n型金氧半導體裝置102上。接觸窗蝕刻終止層240,其可具有一壓縮應力(compressive stress),形成於p型金氧半導體裝置202上。p型金氧半導體裝置202可更包括可由矽化鍺形成之壓力源(stressors,未顯示於圖中),其中源極及汲極區域144可形成於此壓力源內。
在第4圖中,首先毯覆性地形成層間介電質(Inter-Layer Dielectric,ILD)54,使其高度高於硬罩幕層130及230的頂部表面高度。在一些實施例中,層間介電質54可包括含碳氧化物。隨後實施化學機械研磨(Chemical Mechanical Polish,CMP)以移除多餘的層間介電質54,使層間介電質54的頂部表面54A分別與硬罩幕層130及230的頂部表面130A及230A等高。
第5圖顯示了硬罩幕層230及虛設多晶矽層228之上部部份的選擇性移除,虛設多晶矽層228的下部部份並未被移除。在一些實施例中,形成光阻156以覆蓋n型金氧半導體裝置區域100。硬罩幕層230可使用稀釋氫氟酸(dilute HF)移除,多晶矽層228的上部部份可使用乾或濕蝕刻移除。在使用乾蝕刻時,製程氣體可包括CF4 、CHF3 、NF3 、Br2 、HBr、Cl2 或前述之組合。
在一些實施例中,留下的虛設多晶矽層228厚度T2可介於移除前的虛設多晶矽層128厚度T1(第4圖)的約三分之一至約二分之一,但厚度T2亦可較此範圍大或小。在一些實施例中,厚度T2小於約300nm,且可介於約200nm至約300nm。在蝕刻虛設閘極多晶矽層228之 後,移除光阻156。
第6圖顯示了n型金氧半導體裝置區域100中硬罩幕層130的移除。在一些實施例中,硬罩幕層130的移除過程不形成光阻,雖然亦可形成光阻以覆蓋p型金氧半導體裝置區域200。選定可移除硬罩幕層130的蝕刻劑並以蝕刻劑攻擊硬罩幕層130,虛設多晶矽層128及228則實質上不受蝕刻。
參見第7圖,同時蝕刻虛設多晶矽層128及228以露出中間能隙含金屬層226。上述虛設多晶矽層128的上部部份受到蝕刻,虛設多晶矽層128的下部部份則保持覆蓋中間能隙含金屬層126。選定蝕刻劑使中間能隙含金屬層226露出後實質上不受蝕刻劑蝕刻。舉例而言,在一些實施例中,虛設多晶矽層128的厚度T3大於約200nm。厚度T3亦可介於厚度T1(第4圖)的約三分之一至約二分之一。
在露出中間能隙含金屬層226之後,使用一含氧製程氣體對此中間能隙含金屬層226進行處理。此含氧製程氣體可包括氧氣(O2 )、臭氧等。載體氣體亦可使用例如氮氣(N2 )、氫氣(H2 )等。在一些實施例中,此含氧製程氣體中的氧氣體積比可大於約百分之10、大於約百分之25、或大於約百分之50。此含氧製程氣體亦可為純氧。
此處理可使用一電漿處理實施。在一些實施例中,此電漿處理的功率介於約200 watts至約1,000 watts。此含氧製程氣體的壓力可介於約2 mTorr至約5mTorr。偏 壓功率(bias power)可小於約50 watts。處理時間可介於約5秒至約60秒。
處理時,因虛設多晶矽層128保持在中間能隙含金屬層126的上方,故中間能隙含金屬層126不受到處理且其功函數不變。中間能隙含金屬層226受到此處理且其功函數上升,舉例而言,由一中間能隙功函數變為更接近矽的價電帶。在一些實施例中,透過此處理可使中間能隙含金屬層226的功函數上升約0.5eV或更多。因此,在例示的一些實施例中,含金屬層226可能不再為一中間能隙含金屬層。在此處理之後,中間能隙含金屬層226的功函數可能大於中間能隙含金屬層126的功函數,舉例而言,相差約0.5eV,即使中間能隙含金屬層126及226一開始是由相同材料形成。此外,受到此處理的影響,中間能隙含金屬層226可比中間能隙含金屬層126含有更多氧。
在上述處理之後,移除虛設多晶矽層128。虛設多晶矽層128及228造成的溝渠(trenches)隨後被充填,如第8圖所示。此充填之含金屬層的整體功函數可低於矽的中間能隙功函數。在一些實施例中,首先充填氮化鉭層60,隨後形成含金屬層62。舉例而言,此含金屬層62的功函數可大於約4.1eV。含金屬層62的材料可包括例如碳化鉭(TaC)、鋁化鈦(TiAl)、鈦(Ti)、氮化鋁鈦(TiAlN)、氮化矽鉭(TaSiN)、氮化碳鉭(TaCN)、前述之組合、及前述之積層物。在一例示之實施例中,金屬層62包括一鋁化鈦層、位於此鋁化鈦層上之一氮化 鉭層、及位於此氮化鉭層上之一氮化鈦層。留下的溝渠可使用一充填金屬例如鋁充填,其以金屬層64表示。
參見第9圖,實施一化學機械研磨(CMP)製程以移除多餘金屬,使金屬層60/62/64的頂部表面與層間介電質54的頂部表面等高。此金屬層留下的部份以160及260、162及262、164及264表示。n型金氧半導體裝置102的替換閘極(replacement gate)168及p型金氧半導體裝置202的替換閘極268因而形成,其中替換閘極168包括層126、160、162及164,替換閘極268包括層226、260、262及264。第10圖顯示了層間介電質70及接觸插塞(contact plug)72形成之後的結構。n型金氧半導體裝置102及p型金氧半導體裝置202的形成因而完成。
在製成的n型金氧半導體裝置102中,替換閘極168包括在中間能隙含金屬層126上的低功函數金屬層(例如層162)。製成的閘極168因此具有低功函數,其適用於偏好低功函數的n型金氧半導體裝置102。另一方面,在p型金氧半導體裝置202中,替換閘極268包括高功函數含金屬層226上的低功函數金屬層(例如262)。因為高功函數含金屬層226的存在,製成的閘極268具有比閘極168高的功函數。閘極268的功函數因此適用於偏好高功函數的p型金氧半導體裝置202。
根據一些實施例,第11及第12圖分別顯示了一例示之俯視圖及一例示之剖面圖,用以說明n型金氧半導體裝置102及p型金氧半導體裝置202。在第11圖及第12圖的實施例中,n型金氧半導體裝置102的閘極及p 型金氧半導體裝置202的閘極相互連接為一連續閘極條(gate strip)。第11及12圖中的實施例是作為例示之用,第10圖中的替換閘極168及268在其它實施例中可不相互連接。根據第11圖,閘極168及268為從n型金氧半導體裝置102的主動區104延伸至p型金氧半導體裝置202的主動區204的同一金屬閘極條68的一部份。如第12圖所示,閘極168及268可具有實質上相同結構。閘極168中的各層在閘極268中可具有對應層,其中閘極168及268中的對應層由實質上相同的材料形成,具有實質上相同厚度,但層226可具有比層126高的氧濃度。相同地,閘極268中的各層在閘極168中可具有對應層,其中閘極168及268中的對應層由實質上相同的材料形成,具有實質上相同厚度,但層226可具有比層126高的氧濃度。此外,p型金氧半導體裝置202包括含金屬層226上的低功函數層(例如第10圖中的層262)。
如第12圖所示,形成閘極168及268的金屬層由主動區104連續延伸至主動區204。線178繪示閘極168的邊界,線278繪示閘極268的邊界。需要注意的是,在閘極168及268之間,閘極條68可不具有任何在第12圖中線76的方向延伸的明顯界面。這是因為金屬閘極168及268中的全部層皆使用相同的沈積程序沈積。相較於此,在傳統的裝置中,在共享同一閘極條之p型金氧半導體裝置及n型金氧半導體裝置的閘極之間,此處可能會有明顯界面,例如因p型金氧半導體裝置及n型金氧半導體裝置使用不同金屬形成閘極的緣故。
實驗結果指出,上述處理可明顯提昇使用低功函數金屬形成之p型金氧半導體裝置的表現。舉例而言,在一實驗中,分別製作一第一、第二、第三、第四p型金氧半導體裝置樣本。上述第一p型金氧半導體裝置樣本包括一未受處理的氮化鈦層。上述第二p型金氧半導體裝置樣本包括一受體積百分比百分之10的氧氣(O2 )處理的氮化鈦層,製程氣體其餘百分之90為載體氣體。上述第三p型金氧半導體裝置樣本包括一受體積百分比百分之25的氧氣(O2 )處理的氮化鈦層,製程氣體其餘百分之75為載體氣體。上述第四p型金氧半導體裝置樣本包括一受體積百分比百分之100的氧氣(O2 )處理的氮化鈦層。結果發現第二樣本的飽和臨界電壓(saturation threshold voltage)低於第一樣本約50mV,第三樣本的飽和臨界電壓低於第一樣本約100mV,第四樣本的飽和臨界電壓低於第一樣本約150mV。相同地,第二、第三、第四樣本的線性臨界電壓(linear threshold voltage)亦明顯低於第一樣本,第二、第三、第四樣本具有遞減的線性臨界電壓。這些結果指出p型金氧半導體裝置的表現明顯提昇是來自於上述處理。此外,上述結果亦指出可藉由調整處理條件,例如處理製程氣體中氧的百分比,來調整p型金氧半導體裝置的表現。
根據本發明數個實施例,提供一種金氧半導體裝置的製作方法,其包括形成一p型金氧半導體裝置。此方法包括形成一閘極介電層於一半導體基板上之p型金氧半導體裝置區域內、形成一第一含金屬層於p型金氧半 導體裝置區域內之上述閘極介電層上、使用一含氧製程氣體實施一處理於此p型金氧半導體裝置區域內之第一含金屬層、及形成一第二含金屬層於此p型金氧半導體裝置區域內之第一含金屬層上。上述第二含金屬層的功函數小於矽之中間能隙功函數。上述第一含金屬層及第二含金屬層形成上述p型金氧半導體裝置之閘極。
根據本發明其它數個實施例,提供一種金氧半導體裝置的製作方法包括形成一閘極介電層於一半導體基板上,其中此閘極介電層包括一位於一p型金氧半導體裝置區域內的第一部份及一位於一n型金氧半導體裝置區域內的第二部份;形成一第一含金屬層於上述閘極介電層上,其中此第一含金屬層包括一位於一p型金氧半導體裝置區域內的第一部份及一位於一n型金氧半導體裝置區域內的第二部份;形成一虛設層於上述第一含金屬層上,其中此虛設層包括一位於一p型金氧半導體裝置區域內的第一部份及一位於一n型金氧半導體裝置區域內的第二部份;移除上述虛設層之第一部份以露出上述第一含金屬層的第一部份;實施一處理於此第一含金屬層之第一部份,在此處理時,上述第一含金屬層的第二部份被上述虛設層之第二部份的至少一下部部份覆蓋;移除上述虛設層之第二部份的至少下部部份;以及將一第二含金屬層同時填入一第一開口及一第二開口,其中上述第一開口是因移除上述虛設層的第一部份所留下,上述第二開口是因移除上述虛設層的第二部份所留下。
根據本發明其它又數個實施例,提供一p型金氧半 導體裝置包括一閘極介電層設置於一半導體基板上;一第一含金屬層設置於上述閘極介電層上,其中此第一含金屬層包括氧。此p型金氧半導體裝置更包括一第二含金屬層設置於上述第一含金屬層上,其中此第二含金屬層的功函數小於矽之中間能隙功函數。
雖然本發明已以數個較佳實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明之精神和範圍內,當可作任意之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
100‧‧‧n型金氧半導體裝置區域
200‧‧‧p型金氧半導體裝置區域
102‧‧‧n型金氧半導體裝置
202‧‧‧p型金氧半導體裝置
104、204‧‧‧主動區
12‧‧‧線
20‧‧‧基板
21‧‧‧淺溝渠隔離
22、122、222‧‧‧界面層
24、124、224‧‧‧介電層(高介電常數層)
26、126、226‧‧‧中間能隙含金屬層
28、128、228‧‧‧虛設多晶矽層
30、130、230‧‧‧硬罩幕層
130A‧‧‧硬罩幕層130的頂部表面
230A‧‧‧硬罩幕層230的頂部表面
138、238‧‧‧閘極堆疊
140、240‧‧‧接觸窗蝕刻終止層
142、242‧‧‧源極/汲極延伸區域
143、243‧‧‧閘極間隔物
144、244‧‧‧源極/汲極區域
146、246‧‧‧源極、汲極矽化物
54‧‧‧層間介電質
54A‧‧‧層間介電質54頂部表面
156‧‧‧光阻
60、160、260‧‧‧氮化鉭層
62、162、262‧‧‧含金屬層
64、164、264‧‧‧金屬層
68‧‧‧金屬閘極條
70‧‧‧層間介電層
72‧‧‧接觸插塞
76‧‧‧線
168‧‧‧n型金氧半導體裝置的替換閘極
178‧‧‧閘極168的邊界線
268‧‧‧p型金氧半導體裝置的替換閘極
278‧‧‧閘極268的邊界線
T1‧‧‧移除前的虛設多晶矽層128厚度
T2、T3‧‧‧移除後的虛設多晶矽層128厚度
第1~10圖為一系列剖面圖,用以說明根據本發明數實施例之互補式金氧半導體裝置的數個製作步驟。
第11圖為一俯視圖,用以說明根據本發明數實施例之p型金氧半導體裝置及n型金氧半導體裝置,其中此p型金氧半導體裝置的閘極及此n型金氧半導體裝置的閘極為一連續閘極條的一部份。
第12圖為根據本發明數實施例之第11圖中裝置的剖面圖。
100‧‧‧n型金氧半導體裝置區域
200‧‧‧p型金氧半導體裝置區域
102‧‧‧n型金氧半導體裝置
202‧‧‧p型金氧半導體裝置
20‧‧‧基板
122、222‧‧‧界面層
124、224‧‧‧介電層(高介電常數層)
126、226‧‧‧中間能隙含金屬層
140、240‧‧‧接觸窗蝕刻終止層
143、243‧‧‧閘極間隔物
144、244‧‧‧源極/汲極區域
146、246‧‧‧源極、汲極矽化物
160、260‧‧‧氮化鉭層
162、262‧‧‧含金屬層
164、264‧‧‧金屬層
168‧‧‧n型金氧半導體裝置的替換閘極
268‧‧‧p型金氧半導體裝置的替換閘極
70‧‧‧層間介電層
72‧‧‧接觸插塞

Claims (8)

  1. 一種互補式金氧半導體裝置的製作方法,包括:形成一p型金氧半導體裝置及一n型金氧半導體裝置,包括:同時形成一閘極介電層於一半導體基板上之一p型金氧半導體區域及一n型金氧半導體區域;同時形成一第一含金屬層於該p型金氧半導體裝置區域及該n型金氧半導體裝置區域之該閘極介電層上;在形成該第一含金屬層的步驟之後,形成一虛設層於該第一含金屬層上,其中該虛設層在該p型金氧半導體裝置區域及該n型金氧半導體裝置區域具有相同材料及厚度;形成一光阻以覆蓋該n型金氧半導體裝置區域,且蝕刻位於該p型金氧半導體裝置區域之虛設層的一上部分,使位於該p型金氧半導體裝置區域之虛設層的一下部分之厚度小於位於該n型金氧半導體裝置區域的該虛設層之厚度;移除覆蓋該n型金氧半導體裝置區域的該光阻之後,同時蝕刻位於該p型金氧半導體裝置區域之虛設層的該下部分及位於該n型金氧半導體裝置區域的該虛設層,藉以暴露出位於該p型金氧半導體裝置區域之該第一含金屬層;以一含氧製程氣體實施一處理於該p型金氧半導體區域之該第一含金屬層;以及形成一第二含金屬層於該p型金氧半導體裝置區域 之該第一含金屬層上方,其中該第二含金屬層的功函數低於矽之中間能隙功函數,其中位於該p型金氧半導體區域之該第一含金屬層及該第二含金屬層形成該p型金氧半導體裝置之閘極。
  2. 如申請專利範圍第1項所述之互補式金氧半導體裝置的製作方法,其中該第一含金屬層的功函數接近矽之中間能隙功函數。
  3. 如申請專利範圍第2項所述之互補式金氧半導體裝置的製作方法,其中該第一含金屬層包括氮化鈦。
  4. 如申請專利範圍第1項所述之互補式金氧半導體裝置的製作方法,更包括:在形成該p型金氧半導體裝置區域之第二含金屬層的步驟時,同時形成該n型金氧半導體裝置區域的第二含金屬層,其中該n型金氧半導體裝置之閘極包括位於該n型金氧半導體區域之該第一含金屬層及該第二含金屬層。
  5. 如申請專利範圍第1項所述之互補式金氧半導體裝置的製作方法,更包括:在實施該處理的步驟之後,移除該虛設層在該n型金氧半導體裝置區域的部份。
  6. 一種互補式金氧半導體裝置,包括:一p型金氧半導體裝置包括一第一閘極,其中該第一閘極包括:一閘極介電層設置於一半導體基板上;一第一含金屬層設置於該閘極介電層上,其中該第 一含金屬層包含氧;一第二含金屬層設置於該第一含金屬層上,其中該第二含金屬層的功函數小於矽之中間能隙功函數;以及一包括一第二閘極之n型金氧半裝置,其中:該第二閘極具有與該第一閘極實質上相同之結構;該第一閘極中的各層在該第二閘極中具有一對應層;該第二閘極中的各層在該第一閘極中具有一對應層,其中該第一閘極中的各層包括與該第二閘極中對應層實質上相同之材料及厚度;以及該第一閘極及該第二閘極屬於同一閘極條,其中在同一閘極條且在該第一閘極及該第二閘極之間連續延伸的膜層在該第一閘極至該第二閘極之間、垂直於該半導體基板之一主要表面的方向不具有看得到的界面。
  7. 如申請專利範圍第6項所述之互補式金氧半導體裝置,其中該第一含金屬層包括氮化鈦。
  8. 如申請專利範圍第6項所述之互補式金氧半導體裝置,其中該第二閘極包括一第三含金屬層,且該第三含金屬層與該第一閘極中的第一含金屬層具有實質上相同高度及厚度,其中該第一含金屬層及該第三含金屬層包括一相同金屬,其中該第三含金屬層的氧濃度低於該第一含金屬層。
TW101148608A 2011-12-20 2012-12-20 互補式金氧半導體裝置及製作方法 TWI485809B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/331,214 US9142414B2 (en) 2011-12-20 2011-12-20 CMOS devices with metal gates and methods for forming the same

Publications (2)

Publication Number Publication Date
TW201327724A TW201327724A (zh) 2013-07-01
TWI485809B true TWI485809B (zh) 2015-05-21

Family

ID=48609261

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101148608A TWI485809B (zh) 2011-12-20 2012-12-20 互補式金氧半導體裝置及製作方法

Country Status (4)

Country Link
US (1) US9142414B2 (zh)
KR (1) KR101347943B1 (zh)
CN (1) CN103178012B (zh)
TW (1) TWI485809B (zh)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9147747B2 (en) 2013-05-02 2015-09-29 United Microelectronics Corp. Semiconductor structure with hard mask disposed on the gate structure
US9520477B2 (en) 2015-03-16 2016-12-13 Taiwan Semiconductor Manufacturing Company Semiconductor device and fabricating method thereof
US10141321B2 (en) * 2015-10-21 2018-11-27 Silicon Storage Technology, Inc. Method of forming flash memory with separate wordline and erase gates
US10043886B2 (en) * 2016-08-03 2018-08-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate formation through etch back process
US10804140B2 (en) 2018-03-29 2020-10-13 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnect formation and structure
US11315786B2 (en) * 2020-03-06 2022-04-26 Nanya Technology Corporation Semiconductor device structure with fine patterns at different levels and method for forming the same

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060084217A1 (en) * 2004-10-20 2006-04-20 Freescale Semiconductor, Inc. Plasma impurification of a metal gate in a semiconductor fabrication process
US20100244141A1 (en) * 2009-03-31 2010-09-30 Sven Beyer Threshold adjustment of transistors including high-k metal gate electrode structures comprising an intermediate etch stop layer

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4237332B2 (ja) 1999-04-30 2009-03-11 株式会社東芝 半導体装置の製造方法
JP2001257344A (ja) 2000-03-10 2001-09-21 Toshiba Corp 半導体装置及び半導体装置の製造方法
JP2002198441A (ja) 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
KR100384774B1 (ko) * 2000-11-16 2003-05-22 주식회사 하이닉스반도체 반도체 소자의 게이트 제조방법
JP2004152995A (ja) 2002-10-30 2004-05-27 Toshiba Corp 半導体装置の製造方法
US7229873B2 (en) 2005-08-10 2007-06-12 Texas Instruments Incorporated Process for manufacturing dual work function metal gates in a microelectronics device
EP2061076A1 (en) * 2007-11-13 2009-05-20 Interuniversitair Micro-Elektronica Centrum Vzw Dual work function device with stressor layer and method for manufacturing the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20060084217A1 (en) * 2004-10-20 2006-04-20 Freescale Semiconductor, Inc. Plasma impurification of a metal gate in a semiconductor fabrication process
US20100244141A1 (en) * 2009-03-31 2010-09-30 Sven Beyer Threshold adjustment of transistors including high-k metal gate electrode structures comprising an intermediate etch stop layer

Also Published As

Publication number Publication date
CN103178012A (zh) 2013-06-26
US9142414B2 (en) 2015-09-22
CN103178012B (zh) 2016-05-04
KR20130071328A (ko) 2013-06-28
US20130154022A1 (en) 2013-06-20
KR101347943B1 (ko) 2014-01-07
TW201327724A (zh) 2013-07-01

Similar Documents

Publication Publication Date Title
JP4459257B2 (ja) 半導体装置
TWI416667B (zh) 半導體元件及其製造方法
TWI420652B (zh) 半導體裝置及其製造方法
TWI485809B (zh) 互補式金氧半導體裝置及製作方法
US10217640B2 (en) Methods of fabricating semiconductor devices
TW200939399A (en) Hybrid process for forming metal gates of MOS devices
JP2006108602A (ja) 半導体装置及びその製造方法
JP2007208260A (ja) 二重仕事関数金属ゲートスタックを備えるcmos半導体装置
TWI469262B (zh) 半導體裝置之製造方法及半導體裝置
TW200810122A (en) Semiconductor device and method for manufacturing the same
TWI663656B (zh) 具有金屬閘極之半導體元件及其製作方法
JP5203905B2 (ja) 半導体装置およびその製造方法
US20080023774A1 (en) Semiconductor device and method for fabricating the same
JP2010232426A (ja) 半導体装置およびその製造方法
TWI619176B (zh) 半導體裝置的製造方法、高介電常數介電結構及其製造方法
WO2010146641A1 (ja) 半導体装置及びその製造方法
US8350332B2 (en) Semiconductor device and method of manufacturing the same
JP2006108355A (ja) 半導体装置およびその製造方法
TW201036071A (en) Metal gate transistor with barrier layer
JP2008103613A (ja) 半導体装置及びその製造方法
TWI525714B (zh) 雙工作函數半導體元件及其形成方法
JP5407645B2 (ja) 半導体装置及びその製造方法
JP5305989B2 (ja) 半導体装置の製造方法
CN104752316A (zh) 一种制作半导体器件的方法
CN108155235A (zh) 半导体结构及其形成方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees