TWI479644B - 影像感應模組 - Google Patents

影像感應模組 Download PDF

Info

Publication number
TWI479644B
TWI479644B TW098122855A TW98122855A TWI479644B TW I479644 B TWI479644 B TW I479644B TW 098122855 A TW098122855 A TW 098122855A TW 98122855 A TW98122855 A TW 98122855A TW I479644 B TWI479644 B TW I479644B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
image sensing
pads
sensing module
insulating region
Prior art date
Application number
TW098122855A
Other languages
English (en)
Other versions
TW201037822A (en
Inventor
Seung Hyun Lee
Chan Ki Hwang
Seung Ho Lee
Hee Jin Park
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW201037822A publication Critical patent/TW201037822A/zh
Application granted granted Critical
Publication of TWI479644B publication Critical patent/TWI479644B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14625Optical elements or arrangements associated with the device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14618Containers
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/15Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components having potential barriers, specially adapted for light emission
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/0557Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/0556Disposition
    • H01L2224/05571Disposition the external layer being disposed in a recess of the surface
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554External layer
    • H01L2224/05573Single external layer
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/06Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
    • H01L2224/061Disposition
    • H01L2224/0612Layout
    • H01L2224/0613Square or rectangular array
    • H01L2224/06134Square or rectangular array covering only portions of the surface to be connected
    • H01L2224/06135Covering only the peripheral area of the surface to be connected, i.e. peripheral arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/1356Disposition
    • H01L2224/13562On the entire exposed surface of the core
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/1369Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/13698Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13699Material of the matrix
    • H01L2224/1379Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/1354Coating
    • H01L2224/13599Material
    • H01L2224/13698Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/13798Fillers
    • H01L2224/13799Base material
    • H01L2224/138Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/1462Coatings
    • H01L27/14621Colour filter arrangements
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144Devices controlled by radiation
    • H01L27/146Imager structures
    • H01L27/14601Structural or functional details thereof
    • H01L27/14636Interconnect structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/06Polymers
    • H01L2924/078Adhesive characteristics other than chemical
    • H01L2924/07802Adhesive characteristics other than chemical not being an ohmic electrical conductor

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Solid State Image Pick-Up Elements (AREA)
  • Transforming Light Signals Into Electric Signals (AREA)

Description

影像感應模組
本發明係關於數位影像裝置,特別是關於一種用以縮短製造時間之影像感應模組。
一般,影像感應模組係經由偵測入射至半導體元件上之光線而產生數位影像。該影像感應模組可裝設於數位相機、筆記型電腦等裝置上。經由使用影像感應模組可實現動畫或靜態影像。
該影像感應模組係包含一具有半導體元件之半導體晶片,和一裝設半導體晶片之基板。該半導體晶片和基板藉由導線而相互電性連接。
在該半導體晶片和基板經由導線而相互電性連接之情況,當影像感應模組較大時,即需要大量時間來製造該影像感應模組。
本發明之具體實施例係針對一種適用於縮短製造時間並且減小影像感應模組尺寸之影像感應模組。
本發明之一實施態樣中,一影像感應模組係包括一半導體晶片,係具有一半導體晶片體、一置於半導體晶片體上表面之影像感應區、及數個置於半導體晶片體上表面之焊墊;一固定座,係置於該半導體晶片上,並且具有一位於與該半導體晶片體之上表密垂直之處之絕緣區、數個置於該絕緣區之下表面並且與數個焊墊電性連接之連接圖案、及一面向該影像感應區並且與該絕緣區耦合之透明上蓋;及一介於該固定座和半導體晶片之耦合構件,將該固定座和半導體晶片耦合。
該耦合構件係包括非導電膠(NCA)、非導電膜(NCF)、或異方性導電膜(ACF)之任一者。
該影像感應模組又包括數個介於數個焊墊和連接圖案之間之凸塊,使得該焊墊和連接圖案電性連接。
該絕緣區係包含一光學元件,像是安置於絕緣區中之濾光器和透鏡。
該影像感應模組又包括一基板,其係設置於與上表面相對之半導體晶片體之下表面,並且具有與連接圖案電性連接之連接焊墊。
該半導體晶片可被接收並且套疊於該基板之一接收槽中。
該基板可為一軟性基板。
該絕緣區係包含一向內彎曲之底板,其中該絕緣區和半導體晶片體相互接觸,該連接圖案係包含在底板之下表面形成之第一連接圖案部份和由第一連接圖案部份延伸至底板側面之第二連接圖案部份。
該影像感應模組又包括將第二連接圖案部份和基板之連接焊墊電性連接之連接構件。
該絕緣區係包含一向外彎曲之底板,其係由半導體晶片突出,其中該絕緣區和半導體晶片體係相互接觸,該連接焊墊和數個焊墊經由位於底板下表面之連接圖案而相互電性連接。
該絕緣區係包含一向內和向外彎曲之底板,其中該絕緣區和半導體晶片體係相互接觸,該連接焊墊和數個焊墊經由位於底板下表面之連接圖案而相互電性連接。
該影像感應模組又包括數個錫球盤,係與各焊墊電性連接,並且設置於與該半導體晶片體之上表面相對之下表面;及與各錫球盤連接之導電構件。
該影像感應模組又包括穿通電極,係通過該半導體晶片而使該焊墊和錫球盤電性連接。
在本發明之一實施態樣,一影像感應模組係包括一半導體晶片,具有一半導體晶片體、一置於該半導體晶片體之上表面之影像感應區、及數個設置於半導體晶片體上表面之焊墊;一置有半導體晶片並且具有與各焊墊對應之連接焊墊之基板;一固定座,係置於半導體晶片上,並且具有一豎立於半導體晶片上之絕緣區、一與絕緣區相接並且與該半導體晶片平行之底板、置於底板之下表面並且使數個焊墊和與各焊墊對應之連接焊墊電性連接之連接圖案、及一面向影像感應區並且與絕緣區耦合之透明上蓋;及一耦合構件,係介於固定座和半導體晶片之間,以使該固定座和半導體晶片耦合。
該耦合構件係包括非導電膠(NCA)、非導電膜(NCF)、或異方性導電膜(ACF)任一者。
該影像感應模組又包括數個凸塊,係介於數個焊墊和連接圖案之間,並且使該焊墊和連接圖案電性連接。
該基板具有一用以接收半導體晶片之接收槽。
在此,附加圖示未必成比例,有些實例可能增大,以清楚說明本發明之某些特徵。根據本發明之一影像感應模組係包含一半導體晶片、一固定座、及一耦合構件。
該半導體晶片係包含一半導體晶片體、一置於半導體晶片體之上表面之影像感應區、及數個沿著半導體晶片體之上表面之邊緣設置之焊墊。
該固定座係包含一沿著和上表面垂直之邊緣設置之絕緣區、數個置於絕緣區之下表面並且與數個焊墊電性連接之連接圖案、及一面向該影像感應區並且與絕緣區耦合之透明上蓋。
該耦合構件係使絕緣區與半導體晶片體相互耦合。該影像感應區由於該耦合構件而被密封。
茲將參照各附加圖示說明根據本發明之各具體實施例之影像感應模組。
第1圖係一顯示根據本發明之第一具體實施例之影像感應模組之剖面圖。
參照第1圖,一影像感應模組100係包含一半導體晶片10、一固定座20、及一耦合構件30。該影像感應模組100又可包含一基板40。
第2圖係一顯示第1圖所示之半導體晶片之平面圖。
參照第2圖,半導體晶片10係包含一半導體晶片體12、一影像感應區14、及數個焊墊16。在本具體實施例,半導體晶片10又可包含數個凸塊18。
半導體晶片體12可能呈任一幾何形狀,其中較佳配置即半導體晶片體12為一長方六面體形。在一較佳具體實施例中,該長方六面體形之半導體晶片體12具有一上表面和一與上表面相反之下表面。
影像感應區14,可放置於半導體晶片體12上之任何地方,最好是放置於半導體晶片體12上表面之中間部分。影像感應區14係包含數個發光二極體(未顯示於圖中)和一包括數個用以驅動該發光二極體之電晶體之驅動單元(未顯示於圖中)。
數個焊墊16,亦可放置於半導體晶片體上之任何地方,最好是放置於半導體晶片體12之上表面。較佳具體實施例即是使數個焊墊16沿著影像感應區14之周圍放置。詳言之,數個焊墊16可沿著半導體晶片體12上表面之邊緣設置。
數個凸塊18係放置於各焊墊16上。該凸塊18最好包括數塊金凸塊和(或)鎳凸塊。
第3圖係一顯示第1圖所示之絕緣區之底視圖。第4圖係一顯示第1圖所示之絕緣區之側視圖。
往前參照第1圖,固定座20係置於該半導體晶片10上方。該固定座20係包含一絕緣區22、連接圖案25、及一透明上蓋29。
現在參照第3、4圖,絕緣區22可能呈任一幾何形狀,其中絕緣區22最好為一具有開放上、下端之中空矩形框狀。如圖所示,絕緣區22具有數個側壁23和一底板24。底板24可具有任一形狀,其中該底板24所呈現形狀最好係經由將側壁23之下端部向內彎曲而面向該半導體晶片10。
絕緣區22之側壁23係沿著半導體晶片體12上表面之邊緣設置。可以具任一數量之側壁23,然而,最好只有四個側壁23。絕緣區22之四個側壁23係相互連接。各側壁23最好位於與半導體晶片體12之上表面垂直之處。舉例而言,該絕緣區22可以任何類型之絕緣材料製成。雖然在此具體實施例中描述之絕緣區22具有一中空之矩形框狀,該絕緣區22亦可以其他配置方式形成,例如呈一中空圓柱框狀、中空橢圓框狀、中空鑽石框狀、中空三角框狀、中空五角框狀、及中空六角框狀。
可將至少一光學元件28,例如簡單透鏡、複合透鏡、減光鏡、抗反射濾光片、偏光鏡、紫外線(UV)截止濾光片、彩色濾光片或紅外線(IR)濾光片,穩固地放置於絕緣區22之側壁23中。
連接圖案25可為任何形狀並且具各種幾何外觀。較佳配置方式係使連接圖案25包含第一連接圖案部份26和第二連接圖案部份27。第一連接圖案部份26最好設置於絕緣區22之底板24之下表面,第二連接圖案部份27最好是沿著絕緣區22之底板24之側面放置。各連接圖案25之第一連接圖案部份26和第二連接圖案部份27最好是相互電性連接。因此,當從第1圖之橫截面看,連接圖案25呈一「L」形。
在此具體實施例,連接圖案25之第一連接圖案部份26係置於底板24之下表面、與半導體晶片10之各凸塊18對應之位置。因此,各個第一連接圖案部份26係設置於半導體晶片10之各對應凸塊18之上方。
透明上蓋29可為任何形狀並且具各種幾何外觀。透明上蓋29最好具有一上蓋部29a和一耦合部29b。
上蓋部29a最好為透明並且呈一板狀。該上蓋部29a最好被校準而面向半導體晶片10之影像感應區14。該耦合部29b係由上蓋部29a延伸出來,最好剛好在側壁23上,以致該上蓋部29a在絕緣區22之內部。
透明上蓋29,最好能防止或至少使外物導入於影像感應區14之發生減至最少。該透明上蓋29最好能讓外部光線到達影像感應區14。
耦合構件30,能使連接圖案25和與其對應之半導體晶片10之各凸塊18實質和(或)電耦合。在此具體實施例,該耦合構件30係沿著絕緣區22之底板24之一封閉連續線形成。因此,該耦合構件30能防止或至少使外部污染物進入固定座20中以及到達影像感應區14上之發生減至最少,藉此能防止或使不想要之污染物遠離外部。
在此具體實施例之耦合構件30,只要可以使連接圖案25和與其對應之半導體晶片10之各凸塊18實質和(或)電耦合,可以任何類型之材料構成。用以形成耦合構件30之材料包含非導電膠(NCA)、非導電膜(NCF)、及異方性導電膜(ACF)。
基板40係與半導體晶片10耦合。該基板40和半導體晶片10係相互電性連接。
在此具體實施例,基板40可包括,舉例而言,一最好較薄之印刷電路板,一接收槽41係界定於基板40之上表面,因此可在接收槽41中接收或套疊半導體晶片10,較佳情況下,接收槽41之深度係與半導體晶片10之厚度相當。由於可以將半導體晶片10套疊於基板40之接收槽41中,因此可縮減影像感應模組100之整體體積。亦可能防止或至少將易損壞之半導體晶片10之下表面暴露於外部之情況減至最少。
基板40又可包含數個連接焊墊42、錫球盤44、及導電球46。
連接焊墊42最好是沿著接收槽41周圍之基板40上表面配置。在此具體實施例,各連接焊墊42最好放置於鄰近第二連接圖案部份27之位置。
錫球盤44係沿著基板40之下表面(其係與上表面相反)設置,並且與連接焊墊42電性連接。
導電球46係與各錫球盤44電性連接。舉例而言,該導電球46可包括含有焊料之錫球。
在此具體實施例,基板40之連接焊墊42和與各連接焊墊42對應之第二連接圖案部份27係藉由連接構件45(例如焊料)而相互電性連接。
根據此具體實施例,由於半導體晶片10之數個焊墊16與基板40之連接焊墊42絕緣區22而相互隔離,該焊墊16和連接焊墊42不需使用導線即可電性連接。亦即,數個焊墊16和連接焊墊42可藉由連接圖案25和連接構件45而相互電性連接。因此,可顯著地減少製造影像感應模組100所需之時間,以及縮減影像感應模阻100之體積。
第5圖係一顯示根據本發明之第二具體實施例之影像感應模組之剖面圖。除了絕緣區和連接圖案之外,第5圖所示之影像感應模組係具有與上述第1圖所示之影像感應模組一樣之結構。因此,將省略相同元件之詳細描述,將用相同專有名詞和圖號來指稱相同或相似之元件。
參照第5圖,一影像感應模組100係包含一半導體晶片10、一固定座20、及一耦合構件30。該影像感應模組100又可包含一基板40。
在上述元件中,固定座20係置於半導體晶片10上。該固定座20係包含一絕緣區22、連接圖案25、及一透明上蓋29。
絕緣區22最好呈一具有開放之上、下端之中空之矩形框狀。該絕緣區22具有數個側壁23和一最好呈一「L」形之底板24。在此具體實施例,至少部分之絕緣區22之底板24係經由將側壁23之下端部向內彎曲而形成,並且由半導體晶片10之側面向外突出。
絕緣區22之側壁23,最好是沿著半導體晶片體12上表面之四邊配置。因此,最好有四個側壁23。在此具體實施例,絕緣區22之四個側壁23係相互連接。各側壁23最好置於與半導體晶片體12之上表面垂直之處。該絕緣區22可以任何類型之絕緣材料製成。雖然在此具體實施例中描述之絕緣區22具有一中空之矩形框狀,該絕緣區22亦可以其他配置方式形成,例如呈一中空圓柱框狀、中空橢圓框狀、中空鑽石框狀、中空三角框狀、中空五角框狀、及中空六角框狀。
可將至少一光學元件28,例如簡單透鏡、複合透鏡、減光鏡、抗反射濾光片、偏光鏡、紫外線(UV)截止濾光片、彩色濾光片或紅外線(IR)濾光片,放置於絕緣區22之側壁23內。
連接圖案25係設置於絕緣區22之底板24之下表面。在此具體實施例,部分連接圖案25係設置於半導體晶片10之數個凸塊18上,其他部分之連接圖案25係面向基板40之連接墊42。在此具體實施例,連接墊42和連接圖案25係藉由含有焊料之連接構件45而相互電性連接。
根據此具體實施例,由於絕緣區22之橫截面呈一「L」形,底板24延伸向外。因此,可簡化連接圖案25之結構,並且減少必須數量之連接構件45。
第6圖係根據本發明之第三具體實施例之一影像感應模組之剖面圖。除了絕緣區和連接圖案之外,第6圖所示之影像感應模組具有與上述第1圖所示之影像感應模組一樣之結構。因此,將省略相同元件之詳細描述,將用相同專有名詞和圖號來指稱相同或相似之元件。
參照第6圖,一影像感應模組100係包含一半導體晶片10、一固定座20、及一耦合構件30。該影像感應模組100可能又包含一基板40。
在上述元件中,固定座20係設置於半導體晶片10上。該固定座20係包含一絕緣區22、連接圖案25、及一透明上蓋29。
絕緣區22呈一具有開放上、下端之中空矩型框狀。該絕緣區22具有數個側壁23和一底板24。該絕緣區22從橫截面看呈一顛倒之「T」形,因此從側壁23之位置看,底板24係面向半導體晶片10,並且向內和向外延展。因此,在此具體實施例,至少部分之底板24由側壁23向外延伸,並且由半導體晶片10之側面凸出。
絕緣區22之側壁23係沿著半導體晶片體12上表面之四邊緣設置。因此,在此具體實施例中有四個側壁23。又,在此具體實施例,絕緣區22之四個側壁23係相互連接。各側壁23係置於與半導體晶片體12之上表面垂直之處。絕緣區22可以任何類型之絕緣材料製成。雖然在此具體實施例中描述之絕緣區22具有一中空之矩形框狀,該絕緣區22亦可以其他配置方式形成,例如呈一中空圓柱框狀、中空橢圓框狀、中空鑽石框狀、中空三角框狀、中空五角框狀、及中空六角框狀。
可將至少一光學元件28,例如簡單透鏡、複合透鏡、減光鏡、抗反射濾光片、偏光鏡、紫外線(UV)截止濾光片、彩色濾光片或紅外線(IR)濾光片,放置於絕緣區22之側壁23中。
連接圖案25,係置於絕緣區22之底板24之整個下表面。在此具體實施例,部分連接圖案25係放置於半導體晶片10之數個凸塊18上,其他部分之連接圖案25係面向基板40之連接墊42。在此具體實施例,連接墊42和連接圖案25係經由最好含有焊料之連接構件45而相互電性連接。
根據此具體實施例,由於絕緣區22之底板24係由側壁23向內和向外延伸,因此連接圖案25之結構可以相當簡單。因此,有可能防止或至少使連接圖案25和數個凸塊18以及連接圖案25和連接墊42之錯誤排列之發生減至最少。
第7圖係根據本發明之第四具體實施例之一影像感應模組之剖面圖。
參照第7圖,一影像感應模組100係包含一半導體晶片10、一固定座20、一耦合構件30、穿通電極47、及數條重配置線49。
半導體晶片10係包含一半導體晶片體12、一影像感應區14、及數個焊墊16。在此具體實施例,半導體晶片10又可包含數個凸塊18。
舉例而言,半導體晶片體12具有一長方六面體形。該長方六面體型之半導體晶片體12係具有一上表面和一與該上表面相反之下表面。
影像感應區14係設置於半導體晶片體12之上表面之中間部分。該影像感應區14係包含數個發光二極體(未顯示於圖中)和一包含數個用以驅動發光二極體之電晶體之驅動單元(未顯示於圖中)。
數個焊墊16係設置於半導體晶片體12之上表面。舉例而言,該焊墊16最好沿著影像感應區14之周圍配置。詳言之,該焊墊16最好沿著半導體晶片體12之上表面之各邊設置。
穿通電極47係通過半導體晶片體12之上表面和與該上表面相反之下表面。舉例而言,穿通電極47係通過半導體晶片體12之數個焊墊16。
數條重配置線49,係置於半導體晶片體12之下表面。部分之重配置線49係與穿通電極47電性連接,數顆錫球係附著於另一部分之重配置線49上。
在本具體實施例,一絕緣層48可介於半導體晶片體12之下表面和數條重配置線49之間,並且維持該重配置線49和穿通電極47之間之電性連接。
數個凸塊18係置於有穿通電極47通過之各焊墊16上。該凸塊18最好包括金凸塊和(或)鎳凸塊。
固定座20係設置於半導體晶片10上方。該固定座20係包含一絕緣區22、連接圖案25、及一透明上蓋29。
絕緣區22呈一具有開放上、下端之中空矩型框狀。該絕緣區22係具有數個側壁23和一將面向半導體晶片10之側壁23之下端部向內彎曲而形成之底板24。
絕緣區22之側壁23,係沿著半導體晶片體12上表面之四邊緣設置。因此,此具體實施例中有四個側壁23。該絕緣區22之四個側壁23係相互連接。各側壁23係置於與半導體晶片體12之上表面垂直之處。舉例而言,絕緣區22可以任何類型之絕緣材料製成。雖然在此具體實施例中描述之絕緣區22具有一中空之矩形框狀,該絕緣區22亦可以其他配置方式形成,例如呈一中空圓柱框狀、中空橢圓框狀、中空鑽石框狀、中空三角框狀、中空五角框狀、及中空六角框狀。
至少可將一光學元件28,例如簡單透鏡、複合透鏡、減光鏡、抗反射濾光片、偏光鏡、紫外線(UV)截止濾光片、彩色濾光片或紅外線(IR)濾光片,放置於絕緣區22之側壁23內。
連接圖案25係包含第一連接圖案部份26和第二連接圖案部份27。第一連接圖案部份26係置於絕緣區22之底板24之下表面,第二連接圖案部份27係置於絕緣區22之底板24之側面。各第一連接圖案部份26及其對應之第二連接圖案部份27係相互電性連接。因此,當從橫截面看,連接圖案25之剖面呈一「L」形。
在本具體實施例,連接圖案25之第一連接圖案部份26係設置底板24之下表面、與半導體晶片10之各凸塊18對應之位置。因此,各第一連接圖案部份26係置於半導體晶片10之各凸塊18。
透明上蓋29,係具有一上蓋部29a和一耦合部29b。
上蓋部29a,係具有一透明板狀,並且面向半導體晶片10之影像感應區14。該耦合部29b係由上蓋部29a延伸出來,而且正好在絕緣區22之側壁23之內部。
透明上蓋29,能防止或至少能將外物導入影像感應區14之情況減至最少,並且能讓外部光線到達影像感應區14。
耦合構件30,係使連接圖案25和半導體晶片10之數個凸塊18相互實際和(或)電耦合。在此具體實施例,耦合構件30最好於沿著絕緣區22之底板24之一封閉線上形成。該耦合構件30能防止或至少使外部污染物進入固定座20和影像感應區14之發生情況減至最少。
在此具體實施例,用以形成耦合構件30之材料包含非導電膠(NCA)、非導電膜(NCF)、及異方性導電膜(ACF)。
根據此具體實施例,由於穿通電極47係通過半導體晶片10,並且與在半導體晶片10之下表面之數條重配置線49相互電性連接。數顆錫球係附著於數條重配置線49上。因此,有可能實現一具有小尺寸之影像感應模組。
第8圖係根據本發明之第五具體實施例之一影像感應模組之剖面圖。
參照第8圖,一影像感應模組100係包含一半導體晶片10、一固定座20、一耦合構件30、及一基板40。
半導體晶片10係包含一半導體晶片體12、一影像感應區14、及數個焊墊16。在此具體實施例,該半導體晶片10又可包含數個凸塊18。
舉例而言,半導體晶片體12具有一長方六面體形。該長方六面體形之半導體晶片體12係具有一上表面和一與該上表面相反之下表面。
影像感應區14,舉例而言,係設置於半導體晶片體12之上表面之中間部份。該影像感應區14係包含數個發光二極體(未顯示於圖中)和一包含數個用以驅動發光二極體之電晶體之驅動單元(未顯示於圖中)。
數個焊墊16,最好置於半導體晶片體12之上表面。舉例而言,該焊墊16最好沿著影像感應區14之周邊配置。詳言之,該焊墊16最好沿著半導體晶片體12上表面之邊緣配置。
數個凸塊18,最好直接放置於與其對應之各焊墊16上方。該凸塊18可包括各種類型之導電材料,例如由金凸塊和(或)鎳凸塊構成。
基板40係與半導體晶片10相互耦合,在此具體實施例,基板40可包括,舉例而言,一薄形印刷電路板。一接收槽41最好被界定於基板40之上表面,因此可在接收槽41中接收並且套疊半導體晶片10,在較佳情況下,接收槽41之深度與半導體晶片10之厚度相當,由於半導體晶片10係於基板40之接收槽41被接收,因此可縮減影像感應模組100之整體體積。因此,有可能防止或至少將易損壞之半導體晶片10之下表面直接暴露於外部之情形減至最少。
基板40係包含數個連接墊42、錫球盤44、及導電球46。
連接墊42最好設置於接收槽41周圍之基板40之上表面。在此具體實施例,各連接墊42最好設置於與半導體晶片10之數個焊墊16對應之位置。
錫球盤44,係置於基板40之下表面,並且與連接墊42電性連接。導電球46係與錫球盤44電性連接。該導電球46可包括各種類型之導電材料,例如含有焊料之錫球。
固定座20係包含一絕緣區22、連接圖案25、及一透明上蓋29。
絕緣區22為具有開放之上、下端之中空矩形框狀。該絕緣區22具有數個側壁23和一經由將側壁23之下端部向內彎曲而形成之底板24。
絕緣區22之側壁23,係沿著半導體晶片體12之上表面之四邊設置。因此,該絕緣區22係有四個相互連接之側壁23。各側壁23係置於與半導體晶片體12之上表面垂直之處。該絕緣區22可由一絕緣材料構成。雖然在此具體實施例中描述之絕緣區22具有一中空之矩形框狀,該絕緣區22亦可以其他配置方式形成,例如呈一中空圓柱框狀、中空橢圓框狀、中空鑽石框狀、中空三角框狀、中空五角框狀、及中空六角框狀。
可將至少一光學元件28,例如簡單透鏡、複合透鏡、減光鏡、抗反射濾光片、偏光鏡、紫外線(UV)截止濾光片、彩色濾光片或紅外線(IR)濾光片,放置於絕緣區22之側壁23內。
連接圖案25係設置於絕緣區22之底板24之下表面。
在此具體實施例,連接圖案25係面向半導體晶片10之各凸塊18及分別與該凸塊18對應之各連接墊42。該連接墊42和連接圖案25係經由連接構件45(該構件最好包括焊料和錫球)而相互電性連接。
透明上蓋29係具有一上蓋部29a和一耦合部29b。
上蓋部29a最好為一透明板,並且面向半導體晶片10之影像感應區14。該耦合部29b係由上蓋部29a延伸出來,並且正好侷限於絕緣區22之側壁23內。
透明上蓋29,最好能防止或至少使導入影像感應區14之外物減至最少。該透明上蓋29能讓外部光線穿透然後到達影像感應區14。
耦合構件30,係使連接圖案25和數個凸塊18相互實質和(或)電耦合。在此具體實施例,該耦合構件30最好沿著絕緣區22之底板24之一封閉線上形成。耦合構件30能防止或至少使外部污染物進入固定座20和影像感應區14之情況減至最少。
在此具體實施例,用以形成耦合構件30之材料包含非導電膠(NCA)、非導電膜(NCF)、及異方性導電膜(ACF)。。
第8圖所示之具體實施例可適用於固定座20和(或)光學元件28之區域大於半導體晶片10之區域時。
第9~11圖係顯示根據本發明製造影像感應模組之方法之剖面圖。
第9圖係顯示一用於製造一影像感應模組之半導體晶片之方法之剖面圖。
參照第9圖,舉例而言,為了製造一影像感應模組,最好事先預備一半導體晶片10。
一影像感應區14和數個焊墊16係於具有一長方六面體形之半導體晶片10之半導體晶片體12之上表面形成。數個凸塊18分別於數個焊墊16上形成。
影像感應區14,最好於半導體晶片體12上表面之中間部分形成。該影像感應區14係包含數個發光二極體(未顯示於圖中)和一包括數個用以驅動該發光二極體之電晶體之驅動單元(未顯示於圖中)。
於半導體晶片體12之上表面形成之數個焊墊16,最好沿著影像感應區14之周邊設置。詳言之,數個焊墊16最好沿著半導體晶片體12之上表面之各邊設置。
於各焊墊16形成之數個凸塊18,最好包括金凸塊和(或)鎳凸塊。
參照第10圖,當數個凸塊18於半導體晶片10上形成之後,一耦合構件30係沿著半導體晶片10之上表面各邊之一close line形成。用以形成該耦合構件30之材料包括非導電膠(NCA)、非導電膜(NCF)、及異方性導電膜(ACF)。
參照第11圖,一固定座20係於半導體晶片10上形成。
固定座20之一絕緣區22呈一具有開放上、下端之中空矩形框狀。該絕緣區22之側壁23之下端部,其係面向半導體晶片10並且向內彎曲,因此,一底板24形成時係與該側壁23垂直。
可將至少一光學元件28,例如簡單透鏡、複合透鏡、減光鏡、抗反射濾光片、偏光鏡、紫外線(UV)截止濾光片、彩色濾光片或紅外線(IR)濾光片,穩固地放置於絕緣區22之側壁23內。
連接圖案25,最好於絕緣區22之底板24之側面和下表面形成。連接圖案25形成時最好具有第一連接圖案部份26和第二連接圖案部份27。
第一連接圖案部份26係置於絕緣區22之底板24之下表面,第二連接圖案部份27係置於絕緣區22之底板24之側面。各個第一連接圖案部份26和與其對應之第二連接圖案部份27最好相互整合形成。從橫截面看,連接圖案25呈一「L」形。
在此具體實施例,連接圖案25之第一連接圖案部份26,係配置於底板24上、與半導體晶片10之各凸塊18對應之位置。第一連接圖案部份26和數個凸塊18係藉由耦合構件30而互相電性連接。該耦合構件30可將數個凸塊18和第一連接圖案部份26實質或電性連接。
透明上蓋29係具有一上蓋部29a和一耦合部29b。上蓋部29a最好呈一透明板狀,並且在一面向半導體晶片10之影像感應區14之位置形成。該耦合部29b係由上蓋部29a延伸出來,並且正好侷限於絕緣區22之側壁23內。
透明上蓋29能防止或至少使外物導入影像感應區14之情形減至最少,並且能讓外部光線到達影像感應區14。
相互耦合之半導體晶片10和固定座20,係裝設於一基板40上。
基板40可包括,舉例而言,一薄形印刷電路板。一接收槽41係界定於基板40之上表面,因此可於接收槽41中接收並且套疊半導體晶片10。該接收槽41之深度最好與半導體晶片10之厚度相當。
由於半導體晶片10係於基板40之接收槽41被接收,因此可縮減影像感應模組100之整個體積。據此,有可能防止或至少使易損壞之半導體晶片10之下表面之外部暴露之情形減至最少。
基板40係包含數個連接墊42、錫球盤44、及導電球46。該連接墊42係設置於基板40之上表面。
連接墊42,係置於接收槽41之周圍。在此具體實施例,各連接墊42可放置於分別與第二連接圖案部份27對應之位置。
錫球盤44最好置於與基板40之上表面相反之下表面,並且與連接墊42電性連接。
導電球46係與錫球盤44電性連接。舉例而言,導電球46最好包括含有焊料之錫球。
在此具體實施例,基板40之連接墊42和與各連接墊42對應之第二連接圖案部份27,係經由連接構件45(例如:焊料)而電性連接。
由以上說明可知,在本發明,可顯著地縮短製造一影像感應模組所需之時間,並且可顯著地縮減該影像感應模組之體積。
雖然本發明較佳具體實施例主要係作為說明之用,那些熟悉本技術的人將察覺到各種修改、增加及替換,而沒有偏離揭示於下之申請專利範圍中的範圍和精神,均有其可能性。
100...影像感應模組
10...半導體晶片
12...半導體晶片體
14...影像感應區
16...焊墊
18...凸塊
20...固定座
22...絕緣區
23...側壁
24...底板
25...連接圖案
26...第一連接圖案部份
27...第二連接圖案部份
28...光學元件
29...透明上蓋
29a...上蓋部
29b...耦合部
30...耦合構件
40...基板
41...接收槽
42...連接焊墊
44...錫球盤
45...連接構件
46...導電球
第1圖係一顯示根據本發明之第一具體實施例之影像感應模組之剖面圖。
第2圖係一顯示第1圖所示之半導體晶片之平面圖。
第3圖係一顯示第1圖所示之絕緣區之底視圖。
第4圖係一顯示第1圖所示之絕緣區之側視圖。
第5圖係一顯示根據本發明之第二具體實施例之影像感應模組之剖面圖。
第6圖係一顯示根據本發明之第三具體實施例之影像感應模組之剖面圖。
第7圖係一顯示根據本發明之第四具體實施例之影像感應模組之剖面圖。
第8圖係一顯示根據本發明之第五具體實施例之影像感應模組之剖面圖。
第9~11圖係顯示根據本發明製造該影像感應模組之方法之剖面圖。
100...影像感應模組
10...半導體晶片
12...半導體晶片體
14...影像感應區
16...焊墊
18...凸塊
20...固定座
22...絕緣區
23...側壁
24...底板
25...連接圖案
26...第一連接圖案部份
27...第二連接圖案部份
28...光學元件
29...透明上蓋
29a...上蓋部
29b...耦合部
30...耦合構件
40...基板
41...接收槽
42...連接焊墊
44...錫球盤
45...連接構件
46...導電球

Claims (8)

  1. 一種影像感應模組,包含:一半導體晶片,包括:一半導體晶片體;在該半導體晶片體上之一影像感應區,及在該半導體晶片體上之數個焊墊;在該半導體晶片上之一固定座,該固定座包含:一位於該半導體晶片體上方之絕緣區;其中該絕緣區包含一向內彎曲之底板,該絕緣區和該半導體晶片體相互接觸;在該絕緣區上並且有與數個焊墊電耦合之連接圖案;其中該連接圖案包含於該底板形成之第一連接圖案部份和由該第一連接圖案部份延伸至該底板側面之第二連接圖案部份;及一在該影像感應區上方並且與該絕緣區相接之透明上蓋;一耦合構件,係介於該固定座和該半導體晶片之間,使該固定座的第一連接圖案部份和該半導體晶片的數個焊墊耦合;一基板,設於該半導體晶片體之下表面,該基板具有連接墊以與該第二連接圖案電性連接;其中該半導體晶片係設置於該基板之一接收槽中;以及 將該第二連接圖案部份和該基板之連接墊電性連接之連接構件。
  2. 如申請專利範圍第1項之影像感應模組,其中該耦合構件係包括非導電膠(NCA)、非導電膜(NCF)、或異方性導電膜(ACF)之任一者。
  3. 如申請專利範圍第1項之影像感應模組,進一步包含數個介於數個焊墊和連接圖案之間之凸塊,該凸塊係使該焊墊和連接圖案相互電性連接。
  4. 如申請專利範圍第1項之影像感應模組,進一步包含一在該影像感應區上方之光學元件。
  5. 如申請專利範圍第1項之影像感應模組,其中該基板為軟性。
  6. 如申請專利範圍第1項之影像感應模組,其中該光學元件係由包含簡單透鏡、複合透鏡、減光鏡、抗反射濾光片、偏光鏡、紫外線(UV)截止濾光片、彩色濾光片、紅外線(IR)濾光片、及其組合之群組中選出。
  7. 如申請專利範圍第1項之影像感應模組,又包括:數個與各焊墊電性連接之錫球盤,該錫球盤係位於該半導體晶片體上;及與該錫球盤連接之導電構件。
  8. 如申請專利範圍第7項之影像感應模組,又包括通過半導體晶片之穿通電極,係使數個焊墊和錫 球盤相互電性連接。
TW098122855A 2009-04-10 2009-07-07 影像感應模組 TWI479644B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020090031415A KR100997797B1 (ko) 2009-04-10 2009-04-10 이미지 센서 모듈

Publications (2)

Publication Number Publication Date
TW201037822A TW201037822A (en) 2010-10-16
TWI479644B true TWI479644B (zh) 2015-04-01

Family

ID=42934074

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098122855A TWI479644B (zh) 2009-04-10 2009-07-07 影像感應模組

Country Status (4)

Country Link
US (1) US8223248B2 (zh)
KR (1) KR100997797B1 (zh)
CN (1) CN101859786B (zh)
TW (1) TWI479644B (zh)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9419032B2 (en) * 2009-08-14 2016-08-16 Nanchang O-Film Optoelectronics Technology Ltd Wafer level camera module with molded housing and method of manufacturing
KR20130106619A (ko) 2012-03-20 2013-09-30 삼성전자주식회사 이미지 센서 및 그 제조 방법
JP2013232756A (ja) * 2012-04-27 2013-11-14 Sony Corp 光学モジュール
KR20150021659A (ko) * 2013-08-21 2015-03-03 주식회사 동부하이텍 이미지 센서의 제조 방법
CN108417644B (zh) * 2018-03-20 2020-07-03 烟台艾睿光电科技有限公司 一种红外探测器的封装结构以及封装方法
US11329083B2 (en) * 2018-09-26 2022-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Wafer level image sensor package
CN109905584A (zh) * 2019-03-28 2019-06-18 昆山丘钛微电子科技有限公司 摄像头模组及终端
TW202127642A (zh) * 2020-01-14 2021-07-16 力晶積成電子製造股份有限公司 影像感測器結構及其製造方法
USD993931S1 (en) * 2020-07-28 2023-08-01 Ebs Sp Zo.O Housing for an electronic device
USD971168S1 (en) * 2020-11-24 2022-11-29 Bae Systems Information And Electronic Systems Integration Inc. Clip for a semiconductor chip tray

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200723512A (en) * 2005-12-09 2007-06-16 Advanced Semiconductor Eng An image sensor package
TW200742008A (en) * 2006-04-28 2007-11-01 Optronics Technology Inc A A packaging structure of flip chip camera module and its packaging method
CN101339285A (zh) * 2007-07-06 2009-01-07 三星电机株式会社 相机模块封装

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4000507B2 (ja) * 2001-10-04 2007-10-31 ソニー株式会社 固体撮像装置の製造方法
CN1508878A (zh) * 2002-12-20 2004-06-30 胜开科技股份有限公司 射出成型的影像感测器及其制造方法
JP4838501B2 (ja) * 2004-06-15 2011-12-14 富士通セミコンダクター株式会社 撮像装置及びその製造方法
JP4271625B2 (ja) * 2004-06-30 2009-06-03 株式会社フジクラ 半導体パッケージ及びその製造方法
KR100744925B1 (ko) 2005-12-27 2007-08-01 삼성전기주식회사 카메라 모듈 패키지
CN2891286Y (zh) * 2005-12-30 2007-04-18 华东科技股份有限公司 影像感测封装构造
JP4950542B2 (ja) * 2006-04-07 2012-06-13 岩手東芝エレクトロニクス株式会社 固体撮像装置およびその製造方法
CN101075624A (zh) * 2006-05-18 2007-11-21 大瀚光电股份有限公司 覆晶式取像模块封装结构及其封装方法
KR101070921B1 (ko) 2006-10-19 2011-10-06 삼성테크윈 주식회사 이미지 센서용 칩 패키지 및 그 제조방법
CN101179086A (zh) * 2006-11-08 2008-05-14 欣相光电股份有限公司 镶嵌式影像感测芯片的封装结构
KR100896179B1 (ko) * 2007-01-05 2009-05-12 삼성전자주식회사 스택 패키지 및 그 제조방법
KR20080079086A (ko) 2007-02-26 2008-08-29 삼성테크윈 주식회사 이미지 센서 모듈과 이를 구비한 카메라 모듈 및 그 제조방법
CN101285921A (zh) * 2007-04-13 2008-10-15 鸿富锦精密工业(深圳)有限公司 成像模组
KR100833312B1 (ko) * 2007-05-10 2008-05-28 삼성전기주식회사 카메라 모듈
CN101325205A (zh) * 2007-06-14 2008-12-17 鸿富锦精密工业(深圳)有限公司 影像感测晶片封装结构
US7923298B2 (en) * 2007-09-07 2011-04-12 Micron Technology, Inc. Imager die package and methods of packaging an imager die on a temporary carrier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200723512A (en) * 2005-12-09 2007-06-16 Advanced Semiconductor Eng An image sensor package
TW200742008A (en) * 2006-04-28 2007-11-01 Optronics Technology Inc A A packaging structure of flip chip camera module and its packaging method
CN101339285A (zh) * 2007-07-06 2009-01-07 三星电机株式会社 相机模块封装

Also Published As

Publication number Publication date
KR20100112891A (ko) 2010-10-20
TW201037822A (en) 2010-10-16
CN101859786B (zh) 2015-07-01
CN101859786A (zh) 2010-10-13
KR100997797B1 (ko) 2010-12-02
US20100259657A1 (en) 2010-10-14
US8223248B2 (en) 2012-07-17

Similar Documents

Publication Publication Date Title
TWI479644B (zh) 影像感應模組
US8199250B2 (en) Camera module package
KR100744925B1 (ko) 카메라 모듈 패키지
US8730369B2 (en) Wafer level camera module and method of manufacture
US20050161805A1 (en) Semiconductor device, module for optical devices, and manufacturing method of semiconductor device
TWI690779B (zh) 感光晶片封裝模組及其形成方法
CN110661938A (zh) 感光组件、摄像模组及其制作方法
US20070228403A1 (en) Micro-element package module and manufacturing method thereof
WO2021056960A1 (zh) 影像感测模块
US20070152345A1 (en) Stacked chip packaging structure
JP2004327918A (ja) 固体撮像装置およびその製造方法
JP2004242166A (ja) 光モジュール及びその製造方法並びに電子機器
JP2010166021A (ja) 半導体装置及びその製造方法
US20110267534A1 (en) Image sensor package and camera module using same
WO2020039733A1 (ja) 半導体装置、電子機器、および半導体装置の製造方法
JP2004507134A (ja) 小寸の画像記録装置、特にカメラまたはビデオ・カメラ
WO2017036344A1 (zh) 影像传感器封装结构及其封装方法
JP2004221874A (ja) 光モジュール及びその製造方法、回路基板並びに電子機器
JP4145619B2 (ja) 光モジュール及びその製造方法、回路基板並びに電子機器
JP2004289423A (ja) 光モジュール及びその製造方法並びに電子機器
JP2004214788A (ja) 光モジュール及びその製造方法並びに電子機器
JP4463193B2 (ja) 固体撮像装置および固体撮像装置の製造方法
JP2005268963A (ja) 撮像モジュールとマザーボードへのその実装方法およびその製造方法
TWM448054U (zh) 影像感測晶片之封裝結構
WO2024053466A1 (ja) 半導体装置および電子機器

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees