TWI478298B - 用於晶片封裝的環狀結構及積體電路結構 - Google Patents

用於晶片封裝的環狀結構及積體電路結構 Download PDF

Info

Publication number
TWI478298B
TWI478298B TW101103228A TW101103228A TWI478298B TW I478298 B TWI478298 B TW I478298B TW 101103228 A TW101103228 A TW 101103228A TW 101103228 A TW101103228 A TW 101103228A TW I478298 B TWI478298 B TW I478298B
Authority
TW
Taiwan
Prior art keywords
frame portion
corner
substrate
wafer
package
Prior art date
Application number
TW101103228A
Other languages
English (en)
Other versions
TW201312710A (zh
Inventor
Wen Yi Lin
Yu Chih Liu
Ming Chih Yew
Tsung Shu Lin
Bor Rung Su
Jing Ruei Lu
Wei Ting Lin
Original Assignee
Taiwan Semiconductor Mfg Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Mfg Co Ltd filed Critical Taiwan Semiconductor Mfg Co Ltd
Publication of TW201312710A publication Critical patent/TW201312710A/zh
Application granted granted Critical
Publication of TWI478298B publication Critical patent/TWI478298B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/02Containers; Seals
    • H01L23/10Containers; Seals characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/16Fillings or auxiliary members in containers or encapsulations, e.g. centering rings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/34Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001Core members of the bump connector
    • H01L2224/13099Material
    • H01L2224/131Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • H01L2224/331Disposition
    • H01L2224/3318Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/33181On opposite sides of the body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73253Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/33Structure, shape, material or disposition of the layer connectors after the connecting process of a plurality of layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/35Mechanical effects
    • H01L2924/351Thermal stress
    • H01L2924/3511Warping

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
  • Wire Bonding (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

用於晶片封裝的環狀結構及積體電路結構
本發明係有關於一種半導體晶片封裝體,特別係有關於一種晶片封裝的環狀結構。
當晶片封裝體在經歷溫度循環及/或在正常操作期間,在半導體晶片封裝體中,在一半導體晶片固定於一基板上之處,會受到可靠度的問題。覆晶球栅陣列,其為一種類型的晶片封裝技術,係以上下顛倒的方式,將晶片的主動側固定於一基板上方,且藉由接觸至位於晶片上之輸入/輸出接合墊的複數個焊料凸塊接合至上述基板。因為晶片和晶片封裝體元件之間的熱膨脹係數不匹配,例如基板和填充材(underfill)(流動於晶片和基板之間的一黏著劑),在晶片封裝體中會時常發生封裝體翹曲和熱應力。
這些高溫應力和翹曲不僅會於晶片中的低介電常數(low-k)內連線層中導致脫層(delamination)問題,而且也會引起焊料凸塊破裂,而導致晶片封裝體的失效或長期操作可靠度的降低。減少晶片封裝體翹曲的一種方法為,於封裝體內部貼附一環狀結構。然而,即使於封裝體中使用環狀結構,封裝體仍會受到某種程度的翹曲。舉例來說,翹曲和因而產生的應力仍會存在於晶片封裝體的一區域中,例如晶片所位於的晶片封裝體的一中央區域。
有鑑於此,本發明揭露之一實施例係提供一種用於晶片封裝的環狀結構。上述環狀結構包括一框狀部分,係調整以接合至一基板。上述框狀部分環繞一半導體晶片和定義一內部開口,且上述內部開口暴露上述基板的一表面的一部分。至少一轉角部分,上述轉角部分從上述框狀部分的一轉角朝上述半導體晶片延伸,且上述至少一轉角部分的一末端不為一尖角。
本發明揭露之另一實施例係提供一種用於晶片封裝的環狀結構。上述環狀結構包括一框狀部分,係調整以接合至一基板。上述框狀部分具有環繞一半導體晶片的一內部開口,上述內部開口暴露上述基板的一表面的一部分。至少一中段部分,上述框狀部分環繞一半導體晶片和定義上述內部開口,且上述至少一中段部分的一末端不為一尖角。
本發明揭露之又另一實施例係提供一種積體電路結構。上述積體電路結構包括一基板、一半導體晶片和一環狀結構。上述環狀結構具有一框狀部分,係調整以接合至上述基板。上述框狀部分環繞上述半導體晶片和定義一內部開口,上述內部開口暴露上述基板的一表面的一部分。至少一轉角部分,上述轉角部分從上述框狀部分的上述內部開口的一轉角朝上述半導體晶片延伸,且上述至少一轉角部分的一末端不為一尖角。
以下以各實施例詳細說明並伴隨著圖式說明之範例,做為本發明之參考依據。在圖式或說明書描述中,相似或相同之部分皆使用相同之圖號。且在圖式中,實施例之形狀或是厚度可擴大,並以簡化或是方便標示。再者,圖式中各元件之部分將以分別描述說明之,值得注意的是,圖中未繪示或描述之元件,為所屬技術領域中具有通常知識者所知的形式。
第1圖為一覆晶球栅陣列(以下簡稱FCBGA)封裝體10半成品的剖面圖,其具有固定在一第一基板20的一環狀結構2。為了方便顯示和易於了解,在一些圖中,FCBGA封裝體10的元件和尺寸會被放大。然而,熟習此技藝者可知在一實際裝置中,這些元件具有與第1圖中不同之相對尺寸。FCBGA封裝體10包含一晶片30,其具有一上表面32和相對於上表面32的一下表面34。一組焊料凸塊40,連接至位於晶片30的下表面34上的接觸墊(圖未顯示)。晶片30和焊料凸塊40的結合體為習知且可視為一覆晶晶片。晶片30係固定於其下的一第一基板20。焊料凸塊40黏著至位於晶片30的上表面32上的接觸墊(圖未顯示)。一填充材(underfill)50可填充於晶片30和第一基板20之間以使FCBGA封裝體10變得堅硬且進一步防止晶片30遭受彎曲損害。一組焊球60可固定於位於晶片30的下表面34上的接觸墊(圖未顯示)。焊球60也可固定至一第二基板70上的接觸墊(圖未顯示)。第二基板70可為一印刷線路板(有時也稱為一印刷電路板)或可為對於熟習此技藝者而言的一多層模組。
FCBGA封裝體10也可包括一散熱物80,散熱物80和環狀結構2可防止封裝體結構產生額外翹曲。散熱物80係固著於晶片30的頂部以分散晶片30產生的熱,且反向均衡晶片30和第一基板20之間因熱膨脹係數不匹配所產生的應力。環狀結構2係藉由黏著物(圖未顯示)固著於第一基板20和散熱物80之間。第2圖係顯示環狀結構2的上視平面圖。然而,如上所述,即使使用環狀結構2,上述封裝體仍會遭受某種程度的翹曲。
本發明多種實施例的環狀結構係提供高於環狀結構2之一種程度的剛性,以對抗和翹曲和扭轉。第3圖為本發明一實施例之一環狀結構3的上視平面圖。環狀結構3具有儘可能多的固著於第一基板20的表面積,使環狀結構3具有儘可能大的寬度,以助於結構性加強FCBGA封裝體10,使FCBGA封裝體10能抵抗翹曲和扭轉。環狀結構3的尺寸主要被封裝體尺寸決定,且依據第一基板20的尺寸和形狀的至少一個而定。在本發明一實施例中,環狀結構3的厚度可為500μm至1000μm。
環狀結構3具有一堅硬、平坦的框狀部分4,使第一基板20接合於其一側上,而例如散熱物80的一散熱元件接合於其另一側上。在本發明一些實施例中,框狀部分4由一硬式材料形成。在本發明至少一實施例中,框狀部分4包括一導電材料、銅、鎢、鋁、多晶矽、矽化物、陶瓷、比相鄰之一介電材料堅固的一材料、上述合金或上述組合。然而,熟習此技藝者了解可由能夠對晶片封裝體提足夠硬度以對抗和翹曲和扭轉的任何材料形成框狀部分4。
環狀結構3的框狀部分4具有一開口於其中,上述開口用以環繞例如晶片30的積體電路元件。可以了解的是,環狀結構3的上述開口的尺寸係依據環狀結構3必須容納和環繞之積體電路元件(晶片)的尺寸而定。在本發明一些實施例中,係改變上述開口和環狀結構3的尺寸以使環狀結構3的表面積最大化,使其可以固定於第一基板20上,儘可能降低翹曲和扭轉。
再參考第3圖,框狀部分4包括複數個轉角部分6。可將轉角部分6拉大,使環狀結構3固定於第一基板20的表面積變得非常大,其可改善晶片封裝體的結構強度。框狀部分4和轉角部分6會降低因為晶片30和FCBGA封裝體10之間可能存在的熱膨脹係數不匹配而產生的翹曲。如第3圖所示,在本發明至少一實施例中,框狀部分4具有複數個轉角部分6,形成於框狀部分4的轉角。在本發明一些實施例中,轉角部分6的末端會稍微圓潤且因而不會是一尖角。上述稍微圓潤的末端可有助於降低存在於轉角部分6和基板之間的接觸點的應力,因而有助於降低晶片封裝體的翹曲。
在本發明一些實施例中,轉角部分6可由一硬式材料形成。在本發明至少一實施例中,轉角部分6可包括一導電材料、銅、鎢、鋁、多晶矽、矽化物、陶瓷、比相鄰之一介電材料堅固的一材料、上述合金或上述組合。然而,熟習此技藝者了解可由能夠對晶片封裝體提足夠硬度以對抗和翹曲和扭轉的任何材料形成轉角部分6。在本發明一些實施例中,一或多個轉角部分6包括與框狀部分4相同的材料。在本發明其他實施例中,一或多個轉角部分6包括與框狀部分4不同的材料。
如第4圖所示,在本發明另一實施例中,框狀部分4具有複數個中段部分8,形成於框狀部分4的中間區域。如第5圖所示,在本發明另一實施例中,框狀部分4具有複數個轉角部分6,形成於框狀部分4的轉角,以及具有複數個中段部分8,形成於框狀部分4的中間區域。
如第3-5圖所示的實施例中,框狀部分4、轉角部分6和中段部分8可藉由強化晶片封裝體以降低晶片封裝體的翹曲和扭轉。相較於使用習知環狀結構的積體電路封裝體,本發明實施例的環狀結構係強化上述晶片封裝體以預防翹曲和扭轉,因而改善晶片封裝體的性能。依據本發明實施例,可以了解環狀結構有許多不同的變化,而圖式僅顯示一部分的變化例。為了說明本發明的實施例和優點,本發明實施例的環狀結構係應用於FCBGA封裝體;然而上述環狀結構並未限制FCBGA封裝體。本發明實施例可同樣應用於任何類型的晶片封裝體。
依據本發明一實施例,一種用於晶片封裝的環狀結構,包括一框狀部分,係調整以接合至一基板。上述框狀部分環繞一半導體晶片和定義一內部開口,且上述內部開口暴露上述基板的一表面的一部分。至少一轉角部分,上述轉角部分從上述框狀部分的一轉角朝上述半導體晶片延伸,且上述至少一轉角部分的一末端不為一尖角。
依據本發明另一實施例,一種用於晶片封裝的環狀結構,包括一框狀部分,係調整以接合至一基板。上述框狀部分具有環繞一半導體晶片的一內部開口,上述內部開口暴露上述基板的一表面的一部分。至少一中段部分,上述框狀部分環繞一半導體晶片和定義上述內部開口,且上述至少一中段部分的一末端不為一尖角。
依據本發明又另一實施例,一種積體電路結構,包括一基板、一半導體晶片和一環狀結構。上述環狀結構具有一框狀部分,係調整以接合至上述基板。上述框狀部分環繞上述半導體晶片和定義一內部開口,上述內部開口暴露上述基板的一表面的一部分。至少一轉角部分,上述轉角部分從上述框狀部分的上述內部開口的一轉角朝上述半導體晶片延伸,且上述至少一轉角部分的一末端不為一尖角。
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾,因此本發明之保護範圍當視後附之申請專利範圍所界定為準。
2、3...環狀結構
4...框狀部分
6...轉角部分
8...中段部分
10...覆晶球栅陣列封裝體
20...第一基板
30...晶片
32...上表面
34...下表面
40...焊料凸塊
50...填充材
60...焊球
70...第二基板
80...散熱物
第1圖為一覆晶球栅陣列封裝體半成品的剖面圖,其具有固定在一基板的一環狀結構。
第2圖為一環狀結構的上視平面圖。
第3圖為本發明一實施例之一環狀結構的上視平面圖。
第4圖為本發明另一實施例之一環狀結構的上視平面圖。
第5圖為本發明又另一實施例之一環狀結構的上視平面圖。
3...環狀結構
4...框狀部分
6...轉角部分
20...第一基板
30...晶片

Claims (10)

  1. 一種用於晶片封裝的環狀結構,包括:一框狀部分,係調整以接合至一基板,該框狀部分環繞一半導體晶片和定義一內部開口,該內部開口暴露該基板的一表面的一部分;以及至少一轉角部分,該轉角部分從該框狀部分的一轉角朝該半導體晶片延伸,且該至少一轉角部分的一末端不為一尖角且為一圓潤的末端,其中該框狀部分的厚度為500μm至1000μm。
  2. 如申請專利範圍第1項所述之用於晶片封裝的環狀結構,其中該至少一轉角部分包括與該框狀部分相同的材料。
  3. 如申請專利範圍第1項所述之用於晶片封裝的環狀結構,其中該至少一轉角部分包括與該框狀部分不同的材料。
  4. 如申請專利範圍第1項所述之用於晶片封裝的環狀結構,其中該至少一轉角部分包括導電材料、金屬、銅、鎢、鋁、多晶矽、矽化物、陶瓷、比相鄰之一介電材料堅固的一材料、上述合金或上述組合。
  5. 一種用於晶片封裝的環狀結構,包括:一框狀部分,係調整以接合至一基板,該框狀部分具有環繞一半導體晶片的一內部開口,該內部開口暴露該基板的一表面的一部分;以及至少一中段部分,該至少一中段部分從該框狀部分的一側壁朝該內部開口延伸,且該至少一中段部分的一 末端不為一尖角且為一圓潤的末端,其中該至少一中段部分係垂直於該框狀部分的該側壁。
  6. 如申請專利範圍第5項所述之用於晶片封裝的環狀結構,其中該至少一中段部分包括與該框狀部分相同的材料。
  7. 如申請專利範圍第5項所述之用於晶片封裝的環狀結構,其中該至少一中段部分包括與該框狀部分不同的材料。
  8. 如申請專利範圍第5項所述之用於晶片封裝的環狀結構,其中該至少一中段部分包括導電材料、金屬、銅、鎢、鋁、多晶矽、矽化物、陶瓷、比相鄰之一介電材料堅固的一材料、上述合金或上述組合。
  9. 一種積體電路結構,包括:一基板;一半導體晶片;以及一環狀結構,包括:一框狀部分,係調整以接合至該基板,該框狀部分環繞該半導體晶片和定義一內部開口,該內部開口暴露該基板的一表面的一部分;至少一轉角部分,該轉角部分從該框狀部分的該內部開口的一轉角朝該半導體晶片延伸,且該至少一轉角部分的一末端不為一尖角且為一圓潤的末端;以及至少一中段部分,該至少一中段部分從該框狀部分的一側壁朝該內部開口延伸,且該至少一中段部分的一末端不為一尖角且為一圓潤的末端,其中該至少一中段 部分係垂直於該框狀部分的該側壁。
  10. 如申請專利範圍第9項所述之積體電路結構,其中該至少一轉角部分包括與該框狀部分相同的材料。
TW101103228A 2011-09-08 2012-02-01 用於晶片封裝的環狀結構及積體電路結構 TWI478298B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US13/227,983 US9887144B2 (en) 2011-09-08 2011-09-08 Ring structure for chip packaging

Publications (2)

Publication Number Publication Date
TW201312710A TW201312710A (zh) 2013-03-16
TWI478298B true TWI478298B (zh) 2015-03-21

Family

ID=47829106

Family Applications (1)

Application Number Title Priority Date Filing Date
TW101103228A TWI478298B (zh) 2011-09-08 2012-02-01 用於晶片封裝的環狀結構及積體電路結構

Country Status (3)

Country Link
US (1) US9887144B2 (zh)
CN (1) CN103000591B (zh)
TW (1) TWI478298B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9209046B2 (en) * 2013-10-02 2015-12-08 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor device and manufacturing method thereof
JP6421050B2 (ja) 2015-02-09 2018-11-07 株式会社ジェイデバイス 半導体装置
US10607963B2 (en) * 2016-09-15 2020-03-31 International Business Machines Corporation Chip package for two-phase cooling and assembly process thereof
US11387176B2 (en) 2017-03-14 2022-07-12 Mediatek Inc. Semiconductor package structure
US11101236B2 (en) * 2018-08-31 2021-08-24 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor package and method of forming the same
TWI688361B (zh) * 2019-02-19 2020-03-21 廣達電腦股份有限公司 可拆解分離的機器人系統
TWI730891B (zh) * 2019-09-08 2021-06-11 聯發科技股份有限公司 半導體封裝結構
CN113571477A (zh) * 2020-04-28 2021-10-29 华为机器有限公司 一种加强圈及表面封装组件
US20230064277A1 (en) * 2021-08-30 2023-03-02 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and formation method of chip package with reinforcing structures

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020221A (en) * 1996-12-12 2000-02-01 Lsi Logic Corporation Process for manufacturing a semiconductor device having a stiffener member
US20070069366A1 (en) * 2005-09-29 2007-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Novel constraint stiffener design

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US122005A (en) * 1871-12-19 Improvement in advertising-albums
FI944939A0 (fi) * 1994-10-20 1994-10-20 Labsystems Oy Foerfarande foer separering av partiklar
US6191480B1 (en) * 1999-09-07 2001-02-20 International Business Machines Corporation Universal land grid array socket engagement mechanism
TW505267U (en) * 2001-01-04 2002-10-01 Hon Hai Prec Ind Co Ltd Fastener for heat sink device
US6861750B2 (en) * 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers
KR100621555B1 (ko) * 2004-02-04 2006-09-14 삼성전자주식회사 리드 프레임, 이를 이용한 반도체 칩 패키지 및 그의 제조방법
US7432586B2 (en) * 2004-06-21 2008-10-07 Broadcom Corporation Apparatus and method for thermal and electromagnetic interference (EMI) shielding enhancement in die-up array packages
CN100448117C (zh) * 2005-12-29 2008-12-31 富士康(昆山)电脑接插件有限公司 电连接器组件及用于该电连接器组件的电连接器
US8283777B2 (en) * 2010-03-05 2012-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Compressive ring structure for flip chip packaging

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6020221A (en) * 1996-12-12 2000-02-01 Lsi Logic Corporation Process for manufacturing a semiconductor device having a stiffener member
US20070069366A1 (en) * 2005-09-29 2007-03-29 Taiwan Semiconductor Manufacturing Co., Ltd. Novel constraint stiffener design

Also Published As

Publication number Publication date
US20130062752A1 (en) 2013-03-14
TW201312710A (zh) 2013-03-16
CN103000591A (zh) 2013-03-27
US9887144B2 (en) 2018-02-06
CN103000591B (zh) 2016-04-20

Similar Documents

Publication Publication Date Title
TWI478298B (zh) 用於晶片封裝的環狀結構及積體電路結構
US7271480B2 (en) Constraint stiffener design
TWI576969B (zh) 翹曲控制結構、翹曲控制圖案及半導體封裝
US20120126404A1 (en) Semiconductor device
US20060249852A1 (en) Flip-chip semiconductor device
JP4899406B2 (ja) フリップチップ型半導体装置
US7439170B1 (en) Design structure for final via designs for chip stress reduction
JP5181261B2 (ja) 集積回路のためのコンタクトパッドおよびコンタクトパッドの形成方法
JP2018113414A (ja) 半導体装置とその製造方法
JP2009064848A (ja) 半導体装置
US20120205802A1 (en) Printed circuit board and flip chip package using the same with improved bump joint reliability
US7002246B2 (en) Chip package structure with dual heat sinks
JP2007266150A (ja) 熱伝導性接合材、半導体パッケージ、ヒートスプレッダ、半導体チップ、及び半導体チップとヒートスプレッダとを接合する接合方法
JP2007250712A (ja) 半導体装置及びその製造方法
US20060278975A1 (en) Ball grid array package with thermally-enhanced heat spreader
US8502083B2 (en) Mounting substrate and electronic device
US20060118947A1 (en) Thermal expansion compensating flip chip ball grid array package structure
US20170148745A1 (en) Electrical package including bimetal lid
US20060180944A1 (en) Flip chip ball grid array package with constraint plate
US11373968B2 (en) Via structure for semiconductor dies
US20170084562A1 (en) Package structure, chip structure and fabrication method thereof
JP7473156B2 (ja) 半導体パッケージ
JP2010161399A (ja) 半導体装置
KR20220005354A (ko) 반도체 소자용 범프 구조물
JP2010040890A (ja) フリップチップbga基板