TWI473246B - 發光二極體晶粒等級封裝 - Google Patents

發光二極體晶粒等級封裝 Download PDF

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TWI473246B
TWI473246B TW97151602A TW97151602A TWI473246B TW I473246 B TWI473246 B TW I473246B TW 97151602 A TW97151602 A TW 97151602A TW 97151602 A TW97151602 A TW 97151602A TW I473246 B TWI473246 B TW I473246B
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light
electrode
emitting diode
layer
semiconductor structure
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TW201025556A (en
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Chia Liang Hsu
Shu Ting Hsu
Min Hsun Hsieh
Chih Chiang Lu
Alexander Wang
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Epistar Corp
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Priority to JP2009127957A priority patent/JP5711874B2/ja
Priority to US12/648,911 priority patent/US8344412B2/en
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/36Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes
    • H01L33/38Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape
    • H01L33/385Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the electrodes with a particular shape the electrode extending at least partially onto a side surface of the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/32257Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic the layer connector connecting to a bonding area disposed in a recess of the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481Disposition
    • H01L2224/48151Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73251Location after the connecting process on different surfaces
    • H01L2224/73265Layer and wire connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/48Semiconductor devices with at least one potential-jump barrier or surface barrier specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
    • H01L33/62Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Description

發光二極體晶粒等級封裝
本發明係有關於一種發光二極體元件,特別是關於發光二極體晶粒等級封裝。
發光二極體產業蓬勃發展,而封裝業已成為其中的一個主力戰場,從以往經驗我們可以理解輕薄短小、低成本、高效率是不變的設計標竿。目前,發光二極體晶粒須與其他元件組合以形成一發光裝置(light-emitting apparatus)。第11圖為習知之發光裝置結構示意圖,如第11圖所示,一發光裝置600包含一具有至少一電路之次載體(sub-mount)64;至少一銲料62(solder)位於上述次載體64上;一發光二極體晶粒400位於上述次載體64上,其至少具有一基板58;一半導體磊晶疊層54位於上述基板58上;一電極56位於上述半導體磊晶疊層54上;以及一電性連接結構66。藉由銲料62將上述發光二極體晶粒400黏結固定於次載體64上並使發光二極體晶粒400之基板58與次載體64上之電路形成電性連接,再利用電性連接結構66將發光二極體晶粒400之電極56與次載體64上的電路形成電性連接。其中,上述 之次載體64可以是導線架(lead frame)或大尺寸鑲嵌基底(mounting substrate),以方便發光裝置600之電路規劃並提高其散熱效果。使用支架與射出成型的塑膠碗杯技術都可能成為過去式,取而代之的是晶圓等級封裝(Wafer Level Package)、晶粒等級封裝(Chip Level Package),甚至是三維立體封裝(3D Package)。從節省成本與輕薄短小的角度而言,晶粒等級封裝(Chip Level Package)是較可行的方式。
本發明藉由晶粒等級封裝技術,達到縮小發光二極體元件封裝尺寸與簡化封裝製程之目的,同時提升發光二極體元件出光效率。
本發明之一實施例提供一永久基板可以內埋被動元件,且被動元件與磊晶半導體層結構之間可以串聯或並聯方式電性連接。
本發明之一實施例提供一永久基板,可為絕緣材料與高導熱率材料複合而成。其中絕緣材料可為陶瓷材料、玻璃、或高分子材料,高導熱率材料可為銀、銅、石墨、碳化矽、或金。其中在高導熱率材料區域具有複數個熱傳導通孔,以達到高散熱之功效。
本發明之一實施例提供一出光微結構位於磊晶半導體層結構之上,其形狀可以是柱狀、Fresnel透鏡狀、鋸齒狀等,其目的為增加光取出效率。
本發明之一實施例提供一光子晶體(photonic crystal)結構,係利用壓印技術形成。其目的在使侷限於發光二極體中的光不會向任意方向發射,大幅增加了光向上方發射機會,進而降低發光二極體發散角並提升其效率。
本發明之一實施例提供一以交流電操作之光電元件,其由複數個發光二極體元件以串聯方式電性連結所組成。
以下配合第1A圖~第1L圖描述本發明第一實施例發光二極體元件100之製程。首先,請參照第1A圖,提供一成長基板101,包含一第一平面101a及一第二平面101b,其材料為氧化鋁(sapphire),於成長基板101之第一平面101a上形成一磊晶結構116。磊晶結構116係藉由一磊晶製程所形成,例如有機金屬氣相沉積磊晶法(MOCVD)、液相磊晶法(LPE)或分子束磊晶法(MBE)等磊晶製程。此磊晶結構116至少包含一第一電性半導體層110,例如為一n型氮化鋁鎵銦(AlxGa1-x)yIn1-yN層;一活性層112,例如為氮化鋁鎵銦(AlxGa1-x)yIn1-yN所形成的多重量子井結構;以及一第二電性半導體層114,例如為一p型氮化鋁鎵銦(AlxGa1-x)yIn1-yN層。另外,本實施例之活性層112可由例如同質結構、單異質結構、雙異質結構、或是多 重量子井結構所堆疊而成。請參照第1B圖,將成長基板101之上的磊晶結構116蝕刻形成圖形化半導體結構118。請參照第1C圖,分別在第一電性半導體層110及第二電性半導體層114之上形成一第三電極120a及一第四電極120b。請參照第1D圖,提供一暫時基板102,利用連接層122將圖形化半導體結構118與暫時基板102連接。請參照第1E圖,以研磨或蝕刻方式去除至少部份成長基板101,使得成長基板厚度至10μm左右。請參照第1F圖,依序於成長基板101之第二平面101b上形成一反射層124及一金屬黏接層126。再切割金屬黏接層126、反射層124及成長基板101等,如第1G圖所示。接著於圖形化半導體結構118、成長基板101、反射層124及金屬黏接層126之側壁形成一絕緣層127,如第1H圖所示。
請參照第1I圖,提供一永久基板103,包含一第一平面103a及一第二平面103b;其材料可為陶瓷材料、玻璃、複合材料、或高分子材料。於永久基板103形成複數個孔洞以貫通整個永久基板,並將複數個孔洞充填導電物質130;且分別於永久基板之第一平面103a及第二平面103b分別形成第一電極132a及第二電極132b。藉由金屬黏接層126將第1H圖之結構與第1I圖之永久基板黏接,並移除暫時基板102及連接層122,如第1J圖所示。再藉由電鍍 或鍍膜相關製程形成電性連接結構134將發光二極體元件之第三電極120a,第四120b與永久基板上之第一電極132a做連接,如第1K圖所示。切割形成如第1L圖所示結構之發光二極體元件100。發光二極體元件100藉由永久基板上之第二電極132b與發光裝置之電路板電性連接,不須再藉由連接次載體達到散熱效果。
請參照第2圖,於發光二極體元件100之永久基板可為絕緣材料與高導熱率材料複合而成。其中絕緣材料可為陶瓷材料、玻璃、或高分子材料,高導熱率材料可為銀、銅、石墨、碳化矽、或金。且在高導熱率材料區域具有複數個熱傳導通孔140,以達到散熱之功效。
請參照第3圖,分別於發光二極體元件100之第一電性半導體層110上表面未覆蓋電極之區域及第二電性半導體層114上表面未覆蓋電極之區域形成一出光微結構136,其形狀可以是柱狀、Fresnel透鏡狀、鋸齒狀等,此出光微結構目的為增加光取出效率。請參照第4圖,也可於發光二極體元件100之第一電性半導體層110上表面未覆蓋電極之區域及第二電性半導體層114上表面未覆蓋電極之區域形成一光子晶體(photonic crystal)結構137。此光子晶體結構可使得侷限於發光二極體中的光不會向任意方向發射,大幅增加了光導向上方發射機會,進而 降低發光二極體發散角並提升其效率。
本發明第二實施例發光二極體元件200之製程,前半段製程與實施例一製程第1A至1D圖相同。再參照第5A圖,將成長基板101藉由化學選擇性蝕刻或研磨方式去除。請參照第5B圖,依序於第一電性半導體層110下方形成一絕緣反射層124及一金屬黏接層126。接著,如第5C圖所示切割金屬黏接層126及絕緣反射層124,再於圖形化半導體結構118、絕緣反射層124及金屬黏接層126之側壁形成一絕緣層127,如第5D圖所示。
請參照第5E圖,提供一永久基板103,包含一第一平面103a及一第二平面103b;其材料可為陶瓷材料、玻璃、複合材料、或高分子材料。於永久基板103形成複數個孔洞以貫通整個永久基板,並將複數個孔洞充填導電物質130;分別於永久基板之第一平面103a及第二平面103b分別形成第一電極132a及第二電極132b。藉由金屬黏接層126將第5D圖之結構與第5E圖之永久基板黏接,並移除暫時基板102及連接層122,如第5F圖所示。再藉由電鍍或鍍膜相關製程形成電性連接結構134,將發光二極體元件之第三電極120a,第四電極120b與永久基板上之第一電極132a做連接,如第5G圖所示。最後切割形成如第5H圖所示結構之發光二極體元件200。發光二極體元件 200藉由永久基板上之第二電極132b與發光裝置之電路板電性連接,不須再藉由連接次載體達到散熱效果。
請參照第6圖,分別於發光二極體元件200之第一電性半導體層110上表面未覆蓋電極之區域及第二電性半導體層114上表面未覆蓋電極之區域形成一出光微結構136,其形狀可以是柱狀、Fresnel透鏡狀、鋸齒狀等,此出光微結構目的為增加光取出效率。請參照第7圖,也可於發光二極體元件200之第一電性半導體層110上表面未覆蓋電極之區域及第二電性半導體層114上表面未覆蓋電極之區域形成一光子晶體(photonic crystal)結構137。此光子晶體結構可使得侷限於發光二極體中的光不會向任意方向發射,大幅增加了光導向上方發射機會,進而降低發光二極體發散角並提升其效率。
以下配合第8A圖~第8G圖描述本發明第三實施例發光二極體元件300之製程。首先,請參照第8A圖,提供一成長基板101,包含一第一平面101a及一第二平面101b,其材料為砷化鎵(GaAs),於成長基板101之第一平面101a上形成一磊晶結構116。磊晶結構116係藉由一磊晶製程所形成,例如有機金屬氣相沉積磊晶法(MOCVD)、液相磊晶法(LPE)或分子束磊晶法(MBE)等磊晶製程。此磊晶結構116至少包含一第一電性半導體層 110,例如為一n型磷化鋁鎵銦(AlxGa1-x)yIn1-yP層;一活性層112,例如為磷化鋁鎵銦(AlxGa1-x)yIn1-yP所形成的多重量子井結構;以及一第二電性半導體層114,例如為一p型磷化鋁鎵銦(AlxGa1-x)yIn1-yP層。另外,本實施例之活性層112可由例如同質結構、單異質結構、雙異質結構、或是多重量子井結構所堆疊而成。接著,形成一透明黏接層138於磊晶結構116之上。
請參照第8B圖,提供一永久基板103,包含一第一平面103a及一第二平面103b;其材料可為陶瓷材料、玻璃、複合材料、或高分子材料。於永久基板103形成複數個孔洞以貫通整個永久基板,並將複數個孔洞充填導電物質130;分別於永久基板之第一平面103a及第二平面103b分別形成第一電極132a及第二電極132b。接著,在永久基板之第一平面103a上除了第一電極132a區域外形成一透明黏接層138。藉由透明黏接層138將第8A圖之結構與第8B圖之永久基板黏接,如第8C圖所示。請參照第8D圖,將成長基板101藉由化學選擇性蝕刻或研磨方式去除,將磊晶結構116及透明黏接層138蝕刻形成圖型化半導體結構118。請參照第8E圖,分別在第一電性半導體層110及第二電性半導體層114之上形成一第三電極120a及一第四電極120b。再於圖形化半導體結構118之側壁形成一絕緣 層127。接著,藉由電鍍或鍍膜相關製程形成電性連接結構134,將發光二極體元件之第三電極120a,第四電極120b與永久基板上之第一電極132a做連接,如第8F圖所示。切割形成如第8G圖所示結構之發光二極體元件300。發光二極體元件300藉由永久基板上之第二電極132b與發光裝置之電路板電性連接,不須再藉由連接次載體達到散熱效果。
請參照第9圖,分別於發光二極體元件300之第一電性半導體層110上表面未覆蓋電極之區域及第二電性半導體層114上表面未覆蓋電極之區域形成一出光微結構136,其形狀可以是柱狀、Fresnel透鏡狀、鋸齒狀等,此出光微結構目的為增加光取出效率。請參照第10圖,也可於發光二極體元件300之第一電性半導體層110上表面未覆蓋電極之區域及第二電性半導體層114上表面未覆蓋電極之區域形成一光子晶體(photonic crystal)結構137。此光子晶體結構可使得侷限於發光二極體中的光不會向任意方向發射,大幅增加了光導向上方發射機會,進而降低發光二極體發散角並提升其效率。
在晶粒製程的佈局也可以採用多電極串聯設計以達到交流電操作需求,且永久基板可以內埋相關被動元件如電阻或電容,可以達到節省空間之設計。
以上提供之實施例係用以描述本發明不同之技術特徵,但根據本發明之概念,其可包括或運用於更廣泛之技術範圍。須注意的是,實施例僅用以揭示本發明製程、裝置、組成、製造和使用之特定方法,並不用以限定本發明,任何熟習此技藝者,在不脫離本發明之精神和範圍內,當可作些許之更動與潤飾。因此,本發明之保護範圍,當視後附之申請專利範圍所界定者為準。
100,200,300‧‧‧發光二極體元件
101‧‧‧成長基板
101a‧‧‧成長基板第一平面
101b‧‧‧成長基板第二平面
102‧‧‧暫時基板
103‧‧‧永久基板
110‧‧‧第一電性半導體層
112‧‧‧活性層
114‧‧‧第二電性半導體層
116‧‧‧磊晶結構
118‧‧‧圖形化半導體結構
120a‧‧‧第三電極
120b‧‧‧第四電極
122‧‧‧連接層
124‧‧‧反射層
126‧‧‧金屬黏接層
127‧‧‧絕緣層
130‧‧‧導電物質
132a‧‧‧第一電極
132b‧‧‧第二電極
134‧‧‧電性連接結構
136‧‧‧出光微結構
137‧‧‧光子晶體結構
138‧‧‧透明黏接層
140‧‧‧熱傳導通孔
54‧‧‧半導體磊晶疊層
56‧‧‧電極
58‧‧‧基板
62‧‧‧焊料
64‧‧‧次載體
66‧‧‧電性連接結構
400‧‧‧發光二極體晶粒
600‧‧‧發光裝置
第1A圖~第1L圖描述本發明第一實施例發光二極體元件100之製程。
第2圖描述本發明第一實施例發光二極體元件100結構之另一設計。
第3圖描述本發明第一實施例發光二極體元件100結構之另一設計。
第4圖描述本發明第一實施例發光二極體元件100結構之再一設計。
第5A圖~第5H圖描述本發明第二實施例發光二極體元件200之製程。
第6圖描述本發明第二實施例發光二極體元件200結構之另一設計。
第7圖描述本發明第二實施例發光二極體元件200結構之再一設計。
第8A圖~第8G圖描述本發明第三實施例發光二極體 元件300之製程。
第9圖描述本發明第三實施例發光二極體元件300結構之另一設計。
第10圖描述本發明第三實施例發光二極體元件300結構之再一設計。
第11圖描述習知之發光裝置結構示意圖。
100‧‧‧發光二極體元件
101‧‧‧成長基板
101a‧‧‧成長基板第一平面
101b‧‧‧成長基板第二平面
103‧‧‧永久基板
110‧‧‧第一電性半導體層
112‧‧‧活性層
114‧‧‧第二電性半導體層
116‧‧‧磊晶結構
118‧‧‧圖形化半導體結構
120a‧‧‧第三電極
120b‧‧‧第四電極
122‧‧‧連接層
124‧‧‧反射層
126‧‧‧金屬黏接層
127‧‧‧絕緣層
130‧‧‧導電物質
132a‧‧‧第一電極
132b‧‧‧第二電極
134‧‧‧電性連接結構

Claims (10)

  1. 一種發光二極體元件,包括:一永久基板,其中該永久基板具有一第一平面及一第二平面;一第一電極位於該永久基板之該第一平面上;一黏接層位於該永久基板之第一平面上除該第一電極之外區域;一圖形化半導體結構,係位於該黏接層之上,其中該圖形化半導體結構至少包括一第一型半導體層和一第二型半導體層;一第三電極及一第四電極,係位於該圖形化半導體結構上,且分別與該第一型半導體層和該第二型半導體層電性連結;一電性連接結構,係位於該圖形化半導體結構之側壁,且為該第三電極和該第四電極與該第一電極之間電性連接;及一絕緣層,係位於該圖形化半導體結構之側壁與該電性連接結構之間,以於該側壁電性隔絕該圖形化半導體結構與該電性連接結構。
  2. 如申請專利範圍第1項所述之發光二極體元件,更包括一成長基板位於該黏接層與該圖形化半導體結構之間。
  3. 如申請專利範圍第1項所述之發光二極體元件,更包括一熱傳導通孔位於該永久基板之中。
  4. 如申請專利範圍第1項所述之發光二極體元件,其中該永久基板之材料可為陶瓷材料、玻璃、複合材料、或 高分子材料。
  5. 如申請專利範圍第1項所述之發光二極體元件,更包括一出光微結構位於該圖形化半導體結構之上。
  6. 如申請專利範圍第5項所述之發光二極體元件,其中該出光微結構之形狀為柱狀、Fresnel透鏡狀、或鋸齒狀。
  7. 如申請專利範圍第1項所述之發光二極體元件,更包括一光子晶體結構位於該圖形化半導體結構之上。
  8. 如申請專利範圍第1項所述之發光二極體元件,更包括一第二電極位於該永久基板之該第二平面上。
  9. 如申請專利範圍第8項所述之發光二極體元件,其中該永久基板具有複數個充填導電物質之孔洞,以導通該第一電極與該第二電極。
  10. 如申請專利範圍第1項所述之發光二極體元件,更包括一反射層位於該黏接層與該圖形化半導體結構之間。
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