TWI458099B - 製造薄膜電晶體之方法及具有其之有機發光二極體顯示裝置 - Google Patents

製造薄膜電晶體之方法及具有其之有機發光二極體顯示裝置 Download PDF

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TWI458099B
TWI458099B TW099127059A TW99127059A TWI458099B TW I458099 B TWI458099 B TW I458099B TW 099127059 A TW099127059 A TW 099127059A TW 99127059 A TW99127059 A TW 99127059A TW I458099 B TWI458099 B TW I458099B
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layer
amorphous germanium
forming
electrode
pattern
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Ji-Su Ahn
Won-Pil Lee
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Samsung Display Co Ltd
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Description

製造薄膜電晶體之方法及具有其之有機發光二極體顯示裝置
本發明之一態樣係關於製造薄膜電晶體及具有該薄膜電晶體之有機發光二極體顯示裝置之方法，其可藉由防止在對與半導體層電性連接之金屬層施加電場後產生之焦耳熱(Joule heat)所引起的半導體層結晶期間產生電弧而使裝置之缺陷減至最少並增加生產量。
退火技術通常包括利用加熱爐之爐退火技術、利用輻射熱(諸如鹵素燈)之快速熱退火(rapid thermal annealing，RTA)技術、利用雷射之雷射退火技術及利用焦耳熱之退火技術。退火技術取決於材料及方法之特徵，諸如退火溫度之範圍、退火溫度之均勻性、加熱速率、冷卻速率、採購價及維護成本。特定言之，當由於材料及方法之特徵而僅在材料之局部區域需要高溫退火或高速退火時，退火技術之選擇非常有限。
雷射退火技術可使材料之表面快速退火，但雷射退火僅適用於有限的一系列材料，因為退火之可行性取決於待退火之材料之種類 。特定言之，因為退火大尺寸裝置時經掃描之線性雷射束會重疊，所以隨著時間流逝雷射束之強度及照射度會不均勻。再者，雷射退火需要極昂貴的維護成本高的設備。
RTA技術廣泛應用於半導體製造方法中，但當前的TRA技術不能應用於直徑大於300mm之矽晶圓。因此，難以在超大型基板上應用RTA技術。此外，RTA之最高加熱速率為400攝氏度/秒，因此不能應用於需要更高加熱速率之方法。
因此，已廣泛研究可解決此等問題且無處理限制之退火技術。其間，藉由對導電層施加電場及產生焦耳熱進行之快速退火技術可藉由高熱量之傳遞而使所選擇材料快速退火，且其加熱速率遠高於RTA技術。然而，以上利用藉由施加電場所產生之焦耳熱的技術不能避免由焦耳熱產生之電弧所引起的物理缺陷。
本發明之態樣提供製造薄膜電晶體之方法，其包括藉由對金屬層施加電場而使半導體層結晶、隨後將金屬層圖案化成用於裝置中之電極；及具有該薄膜電晶體之有機發光二極體(OLED)顯示裝置。根據此等技術，金屬層與半導體層直接接觸，由此可防止在結晶過程中產生電弧，從而以較簡單之方法得到改良之生產量。
本發明之一態樣提供一種薄膜電晶體，其包括基板、配置於基板上之緩衝層、配置於緩衝層上之半導體層、配置於半導體層上且與半導體層直接接觸之源電極及汲電極、配置於基板之整個表面上之閘極絕緣層、配置於閘極絕緣層上與半導體層相對應之閘極電極、及配置於基板之整個表面上之保護層，其中源電極及汲電 極對閘極電極電絕緣且閘極電極不與源電極或汲電極重疊。
半導體層上與源電極及汲電極相對應之區域可摻有雜質。源電極及汲電極可包括諸如以下材料：鉬(Mo)、鉻(Cr)、鎢(W)、鉬-鎢(MoW)、鋁(Al)、鋁-釹(Al-Nd)、鈦(Ti)、氮化鈦(TiN)、銅(Cu)、Mo合金、Al合金及Cu合金。半導體層可為藉由焦耳熱方法製造之多晶矽層。
本發明之另一態樣提供一種製造薄膜電晶體之方法，其包括提供基板，在基板上形成緩衝層，在緩衝層上形成非晶矽層圖案，在基板之整個表面上形成金屬層，藉由對金屬層施加電場以使非晶矽層圖案結晶而形成半導體層，藉由使金屬層圖案化而形成與半導體層連接的源電極及汲電極，在基板之整個表面上形成閘極絕緣層，在閘極絕緣層上與半導體層相對應形成閘極電極，及在基板之整個表面上形成保護層。
該方法亦可包括在形成非晶矽層圖案後使部分非晶矽層圖案摻有雜質。雜質可為N型或P型雜質。非晶矽層圖案可包括與摻有雜質之非晶矽層圖案部分對應的源電極區及汲電極區。可利用與用於使金屬層圖案化以產生源電極及汲電極之遮罩相同的遮罩來使非晶矽層圖案摻雜。金屬層可在基板之整個表面上形成50nm至300nm之厚度。施加於金屬層以使非晶矽層圖案結晶之電場可在100V/cm至10000V/cm之範圍內。源電極及汲電極及金屬圖案可包括諸如以下材料：鉬(Mo)、鉻(Cr)、鎢(W)、鉬-鎢(MoW)、鋁(Al)、鋁-釹(Al-Nd)、鈦(Ti)、氮化鈦(TiN)、銅(Cu)、Mo合金、Al合金及Cu合金。
本發明之另一態樣提供一種製造有機發光二極體(OLED)顯示裝置之方法，其包括提供基板；在基板之整個表面上形成緩衝層；在緩衝層上形成非晶矽層圖案；在基板之整個表面上形成金屬層；藉由對金屬層施加電場以使非晶矽層圖案結晶而形成半導體層；藉由使金屬層圖案化而形成與半導體層連接的源電極及汲電極；在基板之整個表面上形成閘極絕緣層；在閘極絕緣層上在與半導體層相對應之位置形成閘極電極；在基板之整個表面上形成保護層；在保護層上形成平坦化層；及在平坦化層上形成與源電極或汲電極電性連接之第一電極、有機層及第二電極。
該方法亦可包括在形成非晶矽層圖案後使部分非晶矽層圖案摻有雜質。雜質可為N型或P型雜質。非晶矽層圖案可包括與摻有雜質之非晶矽層圖案部分對應的源電極區及汲電極區。可利用與用於使金屬層圖案化以產生源電極及汲電極之遮罩相同的遮罩來使非晶矽層圖案摻雜。金屬層可在基板之整個表面上形成50nm至300nm之厚度。施加於金屬層以使非晶矽層圖案結晶之電場可在100V/cm至10000V/cm之範圍內。源電極及汲電極及金屬圖案可包括諸如以下材料：鉬(Mo)、鉻(Cr)、鎢(W)、鉬-鎢(MoW)、鋁(Al)、鋁-釹(Al-Nd)、鈦(Ti)、氮化鈦(TiN)、銅(Cu)、Mo合金、Al合金及Cu合金。
100‧‧‧基板
110‧‧‧緩衝層
120‧‧‧半導體層
120'‧‧‧非晶矽層圖案
120a‧‧‧源電極區
120b‧‧‧汲電極區
120c‧‧‧通道區域
130A‧‧‧金屬層
130a‧‧‧源電極
130b‧‧‧汲電極
140‧‧‧閘極絕緣層
150‧‧‧閘極電極
160‧‧‧保護層
170‧‧‧平坦化層
180‧‧‧第一電極
185‧‧‧像素定義層
190‧‧‧有機層
195‧‧‧第二電極
a‧‧‧通孔
圖1A至1F說明一種製造本發明薄膜電晶體之方法；及圖2A與2B說明一種製造本發明OLED顯示裝置之方法。
藉由參考以下實施方式同時結合隨附圖式考慮，本發明之更完全 的評價及其附帶之許多優點將顯而易見，同時也變得更易理解，隨附圖式中同樣的參考符號指示相同或相似的組件。
現在詳細描述本發明之具體實例，其實施例顯示於隨附圖式中，其中同樣的參考數字始終係指同樣的元件。以下藉由參考圖式來描述具體實例以說明本發明。
(例示性具體實例)
圖1A至1F說明一種製造本發明例示性具體實例之薄膜電晶體之方法。
參看圖1A，製備基板100，在基板100上形成緩衝層110。基板100可由玻璃或塑膠製成，緩衝層110用於防止濕氣或雜質自基板100向外擴散，或用於藉由控制結晶期間之熱傳遞速率而促進非晶矽層結晶。緩衝層110可由諸如氧化矽層或氮化矽層、或其組合之絕緣層製成。
隨後，參看圖1B，在緩衝層110上形成非晶矽層圖案120'。隨後，使非晶矽層圖案之源電極區120a及汲電極區120b摻有雜質。此處，雜質可為N型或P型。未摻雜質之區域120c將用作通道區域。
隨後，參看圖1C，在基板100之整個表面上形成金屬層130A。接著對金屬層130A施加電場以使非晶矽層120'結晶成半導體層120。
金屬層130A可由以下一種材料製成：鉬(Mo)、鉻(Cr)、鎢(W)、鉬-鎢(MoW)、鋁(Al)、鋁-釹(Al-Nd)、鈦(Ti)、氮化鈦(TiN)、銅(Cu)、Mo合金、Al合金或Cu合金。
金屬層130A通常形成適於形成源電極130a及汲電極130b之厚度，其較佳在50nm至300nm之範圍內。當金屬層130A之厚度小於50nm時，針對源電極與汲電極之金屬層130A形成不均勻，因而由於不均勻的熱傳遞而導致結晶不均勻。此外，厚度為300nm或300nm以下之金屬層在圖案化後宜用作源電極及汲電極，所以此範圍之厚度適合於薄膜裝置。
此處，施加100V/cm至10000V/cm之電場持續1微秒至1秒以利於結晶。小於100V/cm之電場不能產生足以結晶之焦耳熱，且大於10000V/cm之電場會產生局部電弧。此外，當施加電場少於1微秒時，由於焦耳熱不足而不能促進結晶，且當施加電場超過1秒時，因為結晶產生熱傳遞，所以基板會在邊緣處彎曲或具有缺陷，其會對裝置產生負面影響。
隨後，將金屬層130A圖案化以產生源電極130a及汲電極130b。此處，將源電極130a及汲電極130b圖案化以與半導體層120之源電極區120a及汲電極區120b相對應。
接著，參看圖1E，在基板100之整個表面上形成閘極絕緣層140。閘極絕緣層140可為氧化矽層、氮化矽層、或其組合。
參看圖1F，在閘極絕緣層140上在與半導體層120相對應之位置形成閘極電極150。閘極電極150可在半導體層120之通道區域120c上方形成，以免與源電極130a或汲電極130b重疊。閘極電極150可形成為由鋁或諸如Al-Nd合金之鋁合金製成之單層結構。或者，閘極電極150可為多層結構，其中Al合金層堆疊在Cr或Mo合金層上。
隨後，在基板100之整個表面上形成保護層160，且因而完整形成本發明薄膜電晶體。
圖2A與2B為具有本發明例示性具體實例之薄膜電晶體之OLED顯示裝置的橫剖面圖。此處，OLED顯示裝置被描述為具有圖1F之薄膜電晶體。
參看圖2A，在基板100之整個表面上形成平坦化層170，其具有參看圖1A至1F描述之本發明例示性具體實例之薄膜電晶體。平坦化層170可由諸如以下材料製成：氧化矽；氮化矽；及玻璃上之矽酸鹽；由聚醯亞胺、基於苯并環丁烯之樹脂或丙烯酸酯製成之有機層。或者，平坦化層170可為無機層與有機層之堆疊結構。
蝕刻閘極絕緣層140、保護層160及平坦化層170，由此形成通孔a且因此部分曝露源電極130a或汲電極130b。
隨後，形成經由通孔a與曝露的源電極130a或汲電極130b連接之第一電極180。第一電極180可為陽極或陰極。當第一電極180為陽極時，陽極可由諸如氧化銦錫(ITO)、氧化銦鋅(IZO)或氧化銦錫鋅(ITZO)之透明導電材料製成，且當第一電極180為陰極時，陰極可由Mg、Ca、Al、Ag、Ba或其合金製成。
隨後，參看圖2B，在第一電極180上形成像素定義層185，其具有可部分曝露第一電極180之表面的開口，且在曝露的第一電極180上形成有機層190，其具有發射層。有機層190可進一步包括一或多個電洞注入層、電洞傳遞層、電洞阻擋層、電子阻擋層、電子注入層及電子傳遞層。接著，在有機層190上形成第二電極195。 因此完整形成本發明例示性具體實例之OLED顯示裝置。
為形成電極，當藉由對金屬薄膜施加電場以使非晶矽層結晶成多晶矽層時，可防止在形成多晶矽層過程中出現由焦耳熱引起之電弧。因為金屬層直接形成於非晶矽層圖案上，所以結晶可有效進行，且接著使金屬層圖案化以形成源電極及汲電極，由此以簡單的製造方法來增加生產量。
雖然本發明已參看其預定之例示性具體實例來描述，但熟習此項技術者會瞭解，可在不背離隨附申請專利範圍及其等效物中定義之本發明精神或範疇下對本發明進行多種修改及改變。
100‧‧‧基板
110‧‧‧緩衝層
120‧‧‧半導體層
120a‧‧‧源電極區
120b‧‧‧汲電極區
120c‧‧‧通道區域
130A‧‧‧金屬層

Claims (16)

  1. 一種製造薄膜電晶體之方法，其包含：提供一基板；在該基板上形成一緩衝層；在該緩衝層上形成一非晶矽層圖案，該非晶矽層圖案係為單一層；在該基板之整個表面上形成一金屬層；藉由對該金屬層施加電場以使該非晶矽層圖案結晶而形成一半導體層；藉由使該金屬層圖案化而形成與該半導體層連接之源電極及汲電極；在該基板之該整個表面上形成一閘極絕緣層；在該閘極絕緣層上與該半導體層相對應形成一閘極電極；及在該基板之該整個表面上形成一保護層。
  2. 如申請專利範圍第1項所述之方法，其進一步包含在形成該非晶矽層圖案後使該非晶矽層圖案之部分摻有雜質。
  3. 如申請專利範圍第2項所述之方法，其中該等雜質為N型或P型雜質。
  4. 如申請專利範圍第2項所述之方法，其中該非晶矽層圖案包括與該非晶矽層圖案之摻有該等雜質之該等部分相對應的源電極區及汲電極區。
  5. 如申請專利範圍第2項所述之方法，其中該非晶矽層圖案之摻雜係 利用與用於使該金屬層圖案化以產生該等源電極及汲電極之遮罩相同的遮罩進行。
  6. 如申請專利範圍第1項所述之方法，其中該金屬層在該基板之該整個表面上形成50nm至300nm之厚度。
  7. 如申請專利範圍第1項所述之方法，其中施加於該金屬層以使該非晶矽層圖案結晶之該電場係在100V/cm至10000V/cm之範圍內。
  8. 如申請專利範圍第1項所述之方法，其中該源電極及汲電極及一金屬圖案包含選自由以下組成群組之材料：鉬(Mo)、鉻(Cr)、鎢(W)、鉬-鎢(MoW)、鋁(Al)、鋁-釹(Al-Nd)、鈦(Ti)、氮化鈦(TiN)、銅(Cu)、Mo合金、Al合金及Cu合金。
  9. 一種製造有機發光二極體(OLED)顯示裝置之方法，其包含：提供一基板；在該基板之整個表面上形成一緩衝層；在該緩衝層上形成一非晶矽層圖案，該非晶矽層圖案係為單一層；在該基板之該整個表面上形成一金屬層；藉由對該金屬層施加電場以使該非晶矽層圖案結晶而形成一半導體層；藉由使該金屬層圖案化而形成與該半導體層連接之源電極及汲電極；在該基板之該整個表面上形成一閘極絕緣層；在該閘極絕緣層上在與該半導體層相對應之位置形成一閘極電極；在該基板之該整個表面上形成一保護層；在該保護層上形成一平坦化層；及 在該平坦化層上形成一與該源電極或該汲電極電性連接之第一電極、一有機層及一第二電極。
  10. 如申請專利範圍第9項所述之方法，其進一步包含在形成該非晶矽層圖案之後使該非晶矽層圖案之部分摻有雜質。
  11. 如申請專利範圍第10項所述之方法，其中該等雜質為N型或P型雜質。
  12. 如申請專利範圍第10項所述之方法，其中該非晶矽層圖案包括與該非晶矽層圖案之摻有該等雜質之該等部分相對應的源電極區及汲電極區。
  13. 如申請專利範圍第10項所述之方法，其中該摻雜係利用與用於使該金屬層圖案化之遮罩相同的遮罩進行。
  14. 如申請專利範圍第9項所述之方法，其中該金屬層形成50nm至300nm之厚度。
  15. 如申請專利範圍第9項所述之方法，其中施加於該金屬層以使該非晶矽層圖案結晶之該電場係在100V/cm至10000V/cm之範圍內。
  16. 如申請專利範圍第9項所述之方法，其中該源電極及該汲電極及該金屬層包含選自由以下組成群組之材料：鉬(Mo)、鉻(Cr)、鎢(W)、鉬-鎢(MoW)、鋁(Al)、鋁-釹(Al-Nd)、鈦(Ti)、氮化鈦(TiN)、銅(Cu)、Mo合金、Al合金及Cu合金。
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JP2011040710A (ja) 2011-02-24
US20110037073A1 (en) 2011-02-17
US8871616B2 (en) 2014-10-28
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