TWI456673B - 具有銲接凸塊之配線基板的製造方法 - Google Patents

具有銲接凸塊之配線基板的製造方法 Download PDF

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Publication number
TWI456673B
TWI456673B TW100108855A TW100108855A TWI456673B TW I456673 B TWI456673 B TW I456673B TW 100108855 A TW100108855 A TW 100108855A TW 100108855 A TW100108855 A TW 100108855A TW I456673 B TWI456673 B TW I456673B
Authority
TW
Taiwan
Prior art keywords
solder bumps
flux
manufacturing
solder
substrate
Prior art date
Application number
TW100108855A
Other languages
English (en)
Other versions
TW201201295A (en
Inventor
Takeshi Fujiwara
Tatsunori Murase
Takuya Hando
Hajime Saiki
Motonobu Kurahashi
Original Assignee
Ngk Spark Plug Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ngk Spark Plug Co filed Critical Ngk Spark Plug Co
Publication of TW201201295A publication Critical patent/TW201201295A/zh
Application granted granted Critical
Publication of TWI456673B publication Critical patent/TWI456673B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/146—Mixed devices
    • H01L2924/1461—MEMS
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
    • H01L2924/191—Disposition
    • H01L2924/19101—Disposition of discrete passive components
    • H01L2924/19105—Disposition of discrete passive components in a side-by-side arrangement on a common die mounting substrate

Landscapes

  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Wire Bonding (AREA)

Claims (6)

  1. 一種具有銲接凸塊之配線基板的製造方法，係包含基板準備製程、銲球搭載製程及回流製程之配線基板的製造方法，該基板準備製程係準備在基板主面上的凸塊形成區域內配置有複數個銲墊的基板，該銲球搭載製程係使銲球搭載於該複數個銲墊上，該回流製程係使所搭載的該銲球加熱熔化而形成複數個銲接凸塊，該配線基板的製造方法之特徵在於：於該回流製程後，進行以下製程：助熔劑(flux)供給製程，係將助熔劑供給於該複數個銲接凸塊的表面；及表面狀態改善製程，係藉由使已供給助熔劑的該複數個銲接凸塊加熱，改善該複數個銲接凸塊的表面狀態；及於該表面狀態改善製程後，進行以下製程：再次供給助熔劑製程，係對構成該複數個銲接凸塊的複數個第1銲接凸塊供給助熔劑；及零件搭載製程，係將配置於零件底面側的複數個連接端子，使其對應於與該複數個第1銲接凸塊不同的複數個第2銲接凸塊而配置，在此狀態下，藉由加熱熔化該複數個第2銲接凸塊而接合該複數個第2銲接凸塊與該複數個連接端子，將該零件搭載於該基板上。
  2. 如申請專利範圍第1項之具有銲接凸塊之配線基板的製造方法，其中該表面狀態改善製程為使該複數個銲接凸 塊加熱熔化的再回流製程。
  3. 如申請專利範圍第1項之具有銲接凸塊之配線基板的製造方法，其中在該助熔劑供給製程中，將助熔劑噴塗於該複數個銲接凸塊的表面。
  4. 如申請專利範圍第1項之具有銲接凸塊之配線基板的製造方法，其中在該助熔劑供給製程中，將助熔劑印刷或轉印於該複數個銲接凸塊的表面。
  5. 如申請專利範圍第1至4項中任一項之具有銲接凸塊之配線基板的製造方法，其中該銲球為直徑200μm以下的微球。
  6. 如申請專利範圍第1至4項中任一項之具有銲接凸塊之配線基板的製造方法，其中於該表面狀態改善製程後，進行檢查該複數個銲接凸塊高度的檢查製程。
TW100108855A 2010-03-31 2011-03-16 具有銲接凸塊之配線基板的製造方法 TWI456673B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2010083203A JP5479979B2 (ja) 2010-03-31 2010-03-31 はんだバンプを有する配線基板の製造方法

Publications (2)

Publication Number Publication Date
TW201201295A TW201201295A (en) 2012-01-01
TWI456673B true TWI456673B (zh) 2014-10-11

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
TW100108855A TWI456673B (zh) 2010-03-31 2011-03-16 具有銲接凸塊之配線基板的製造方法

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JP (1) JP5479979B2 (zh)
TW (1) TWI456673B (zh)

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203902A (ja) * 1995-01-20 1996-08-09 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH1032222A (ja) * 1996-07-12 1998-02-03 Sony Corp 電子部品の製造方法
US6156635A (en) * 1998-02-17 2000-12-05 Mitsubishi Denki Kabushiki Kaisha Method of correcting solder bumps
US20010025874A1 (en) * 2000-03-28 2001-10-04 Nec Corporation Method of forming solder bumps, method of mounting flip chips, and a mounting structure
JP2005347673A (ja) * 2004-06-07 2005-12-15 Hitachi Metals Ltd 導電性ボールの搭載方法および搭載装置
JP2008166468A (ja) * 2006-12-28 2008-07-17 Nidec-Read Corp 基板処理装置
TW200919605A (en) * 2007-09-25 2009-05-01 Ngk Spark Plug Co Method for manufacturing wiring substrate having solder bumps

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08203902A (ja) * 1995-01-20 1996-08-09 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
JPH1032222A (ja) * 1996-07-12 1998-02-03 Sony Corp 電子部品の製造方法
US6156635A (en) * 1998-02-17 2000-12-05 Mitsubishi Denki Kabushiki Kaisha Method of correcting solder bumps
US20010025874A1 (en) * 2000-03-28 2001-10-04 Nec Corporation Method of forming solder bumps, method of mounting flip chips, and a mounting structure
JP2005347673A (ja) * 2004-06-07 2005-12-15 Hitachi Metals Ltd 導電性ボールの搭載方法および搭載装置
JP2008166468A (ja) * 2006-12-28 2008-07-17 Nidec-Read Corp 基板処理装置
TW200919605A (en) * 2007-09-25 2009-05-01 Ngk Spark Plug Co Method for manufacturing wiring substrate having solder bumps

Also Published As

Publication number Publication date
JP5479979B2 (ja) 2014-04-23
JP2011216660A (ja) 2011-10-27
TW201201295A (en) 2012-01-01

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