TWI450349B - 覆晶球柵式陣列封裝之底膠缺陷之檢測方法 - Google Patents

覆晶球柵式陣列封裝之底膠缺陷之檢測方法 Download PDF

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TWI450349B
TWI450349B TW099129198A TW99129198A TWI450349B TW I450349 B TWI450349 B TW I450349B TW 099129198 A TW099129198 A TW 099129198A TW 99129198 A TW99129198 A TW 99129198A TW I450349 B TWI450349 B TW I450349B
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wafer
substrate
active surface
connecting elements
ball grid
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TW201209942A (en
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Chien Wen Chen
Chia Jen Kao
Jui Cheng Chuang
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Global Unichip Corp
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Description

覆晶球柵式陣列封裝之底膠缺陷之檢測方法
本發明主要是揭露一種覆晶球柵封裝結構之形成方法,特別地是一種覆晶球柵封裝結構之底膠缺陷之檢測方法。
球柵陣列(BGA)為一積體電路封裝技術之先進類型,其特徵為使用一有機基底,該基底之上表面與一半導體晶片鑲嵌,而其下表面則鑲嵌於一柵陣列焊錫球上。於一表面鑲嵌技術製程中,舉例來說,該BGA封裝可藉由這些焊錫球之手段,以機械式地鍵結及電性上地耦合至一印刷電路板(PCB)上。
覆晶球柵陣列為一種先進的BGA技術,其係使用覆晶技術,以上下翻轉之手段將晶片的主動面端鑲嵌於基底上,且將已黏著至其輸入/輸出墊(I/O pad)之複數焊錫凸塊連接至基底上。由於該覆晶球柵陣列(FCBGA)封裝各零組件間之既有熱膨脹係數(CTE)不相容,例如晶片、基底、填充物(設置於晶片與基底間流動之黏著劑),因此,封裝翹曲(peeling)現象以及熱應力會頻繁地發生於覆晶球柵陣列封裝中。這些頻繁的熱應力及翹曲現象不但造成晶片裡的低介電內連線層分層,進而導致焊錫凸塊破裂,甚至產生導致封裝失敗的情事,使得長時期的覆晶球柵陣列封裝之可靠度操作降低。更甚者,黏著覆晶之基底可為一單層結構,或基底可以包括兩個或多層材質。這些材質之組成及結構通常是相當多樣化的。這些不同層的熱膨脹係數被認為是有差異的,且導致無法控制之彎曲或由熱引起基底表面的變形。這樣的變形可造成覆晶或基底之其他零組件的失敗。
為了覆晶球柵陣列封裝,新零組件及材料即被導入,例如,無機基底(如陶瓷),但由於這些零組件間熱膨脹係數不相容,而使得上述問題更形顯著。
由於這些因素及根據下列詳細的描述可推得之其他因素可得知:因為這些零組件間熱膨脹係數不相容,故尋得一可降低及/消除傳統覆晶球柵陣列封裝中零組件及/或層板之可靠度問題的改良之覆晶球柵陣列封裝結構是必要的。
此外,如第1A圖所示之一種加強型具有高性能覆晶球柵陣列封裝結構,且其具有一金屬環,用以墊高覆蓋用的散熱片。在第1A圖中,習知的覆晶球柵陣列封裝構造包含一基板100、設於基板100上表面的晶片110、環繞晶片110設於基板100上表面周緣之金屬環130以及設於晶片110與金屬環130上方的散熱片140。一般來說,晶片110係藉由錫球112與基板100電性連接,錫球112則被底膠114所包覆。基板100下表面設有複數個錫球150,以使封裝結構能與外界裝置電性連接。
為封裝上述封裝構造,通常需要進行多道高溫處理製程步驟,例如進行回焊或是填充底膠114之步驟時,需要將封裝構造置入高溫的環境中。但是,當基板100處於高溫的環境下,很可能因為過熱而產生基板100撓曲的現象,此時,配置於基板100上的金屬環130則可增加基板100的強度,避免基板100產生過大的撓曲。
然而,由於習知封裝構造係僅於基板100的上表面設置於金屬環130,當基板100之撓曲度過大時,極可能使金屬環130產生剝離的現象。
除此之外,當底膠114填充於該晶片110與基板100之間時,同時晶片110會貼附至基板100,而晶片110主動面(未在圖中表示)的錫球112的高度不夠,造成填充材料114與晶片110表面之錫球112之間有空隙120(如第1B圖所示),甚至晶片110的連接元件短路,使得整個封裝晶片無法操作。
根據以上問題,本發明的主要的目的係在晶片設置在基板之後利用紅外線回焊的方式,使晶片上的連接元件固接於基板,故在底膠填充之後,使得底膠可以完全包覆在晶片之主動面與基板之間而不會產生空隙。
本發明之另一目的係利用x光繞射的方式檢測晶片之主動面與基板之間有無空隙存在。
根據上述之目的,本發明係提供一種形成覆晶球柵陣列封裝結構之方法,其包含,提供一基板,且具有一內連線結構及複數個中介層;提供一晶片,其具有主動面及一背面,且於主動面上具有複數個第一連接元件;將晶片設置在基板上,係將晶片上下反轉,使得晶片的主動面朝下,且晶片之複數個第一連接元件與基板透過中介層與內連線結構電性連接;至少執行一次紅外線回焊步驟,使得晶片上之複數個第一連接元件與基板固接;填充封膠材料以包覆晶片之主動面及複數個第一連接元件;執行檢測步驟,以檢測封膠材料包覆複數個第一連接元件與晶片之主動面之間否具有空隙存在;及形成複數個第二連接元件在基板之該背面,以完成一覆晶球柵陣列封裝結構。
接著,本發明還提供另一形成覆晶球柵陣列封裝結構之方法,包含:提供一基板,且具有一內連線結構及複數個中介層;提供一晶片,其具有一主動面及一背面且於該主動面上具有複數個第一連接元件;設置該晶片於該基板上,係將晶片上下反轉,使得晶片之主動面朝下,且晶片之複數個第一連接元件與基板透過中介層與內連線結構電性連接;至少執行一次紅外線回焊,使得晶片之複數個第一連接元件固接於基板上;預先填充一封膠材料以包覆晶片之主動面及複數個第一連接元件;執行一檢測步驟,以檢測封膠材料包覆複數個第一連接元件與晶片之主動面之間是否具有空隙存在;再執行一填充步驟,以繼續填充封膠材料直至複數個第一連接元件與晶片之主動面之間沒有空隙存在為止;形成複數個支撐元件在基板上且鄰近於晶片,但與該晶片電性隔離;及形成複數個第二連接元件在基板之背面,以完成覆晶球柵陣列封裝結構。
故而,關於本發明之優點與精神可以藉由以下發明詳述及所附圖式得到進一步的瞭解。
本發明在此所探討的方向為一種檢測覆晶球柵封裝結構之底膠缺陷的方法。為了能徹底地瞭解本發明,將在下列的描述中提出詳盡的檢測底膠缺陷之方法。顯然地,本發明的實行並未限定此覆晶球柵封裝結構之技藝者所熟習的特殊細節,然而,對於本發明的較佳實施例,則會詳細描述如下。
首先請參考第2A圖係表示本發明所揭露之覆晶球柵封裝結構之示意圖。在第2A圖中,其覆晶球柵封裝結構包含:一基板10,且在基板10內具有中介層14及內連線結構16且在基板10之上表面10A及下表面10B分別佈設有線路圖案(未在圖中表示),其中在基板10內的中介層(interposer)14及內連線結構(interconnect structure)16係用以電性連接基板10之上下表面10A、10B;一晶片20,其具有主動面(未在圖中表示)及一背面(未在圖中表示),且在主動面上具有複數個第一連接元件22,係將晶片20上、下反轉,使得晶片20之主動面朝下,且藉由複數個第一連接元件22設置於基板10之上表面10A;一封膠材料30,係包覆晶片20之主動面及複數個第一連接元件22;及在基板10之下表面10B具有複數個第二連接元件60,以得到一覆晶球柵陣列封裝結構。在此,晶片20可以是定制靜態動態存取記憶體(Custom Static RAM,CSRAM),及封膠材料30可以是環氧樹脂(epoxy resin)。
接著,請參考第3A圖,係表示本發明所揭露之覆晶球柵封裝結構之另一較佳實施例之結構示意圖。在第3A圖中,其覆晶球柵封裝結構包含:一基板10,且在基板10內具有中介層(interposer)14及內連線結構16且在基板10之上表面10A及下表面10B分別佈設有線路圖案(未在圖中表示),其中在基板10內的中介層14及內連線結構(interconnect structure)16係用以電性連接基板10之上、下表面10A、10B。一晶片20,其具有主動面(未在圖中表示)及一背面(未在圖中表示),且在主動面上具有複數個第一連接元件22,係將晶片20上、下反轉,使得晶片20之主動面朝下,且藉由複數個第一連接元件22設置於基板10之上表面10A。而一封膠材料30,係包覆晶片20之主動面及複數個第一連接元件22。複數個支撐元件40設置在基板10之上表面10A,且鄰近於晶片20,但是與晶片20電性隔離,其中這些支撐元件40的材料可以是銅、銅碳、銅鎢、碳化矽鋁、鋁、不銹鋼、鎳及鍍鎳之銅等等。接著,設置一散熱元件在複數個支撐元件40及晶片20之背面(未在圖中表示)上。以及在基板10之下表面10B具有複數個第二連接元件60,以得到一覆晶球柵陣列封裝結構。同樣地,在本實施例中,晶片20可以是定制靜態動態存取記憶體(Custom Static RAM,CSRAM),且封膠材料30可以是環氧樹脂(epoxy resin)。
另外,複數個支撐元件40係用以增加基板10的強度,以達到減少基板10撓曲的效果,且在支撐元件40與基板10之間更包含一黏著層(未在圖中表示),係將支撐元件40固著於基板10上。另外,為了散熱的目的,係在支撐元件40及晶片20的背面上設置一散熱元件50,用以移除由覆晶球柵封裝結構在操作時,由晶片20所產生的熱量。同樣地,在散熱元件50與支撐元件40及晶片20之背面之間更包含另一黏著層(未在圖中表示),係將散熱元件50緊密貼附在支撐元件40及晶片20之背面(未在圖中表示)上。
因此,根據第2A圖及第3A圖所述,在填充封膠材料30之前,係先執行紅外線回焊(IR reflow)步驟,使得晶片20之主動面(未在圖中表示)上之複數個第一連接元件22固接於基板10之上表面10A的焊墊12,在此,可以執行一次或多次的紅外線回焊步驟,其目的是紅外線回焊具有良好的穿透力,可以控制揮發物排出的同時,讓錫膏均勻地升溫,使得設置在晶片20之主動面(未在圖中表示)上的複數個第一連接元件22可以均勻受熱,且使得第一連接元件22在晶片20之主動面(未在圖中表示)上之形狀不會有一缺角(如第1B圖中之參考標號120所示),而藉由第一連接元件22將晶片20固接於基板20之上表面10A。接著,係將封膠材料30藉由底膠填充(under-fill)的方式填入晶片20之主動面(未在圖中表示)之複數個第一連接元件22與基板10之上表面10A之間。接著,執行一檢測步驟,係利用x光繞射(x-ray)的方式,偵測在晶片20之主動面與第一連接元件22之間是否未被封膠材料完全包覆而產生空隙(如第1B圖中表示之參考標號120)。然而在先前,由於紅外線回焊具有均勻加熱的特性,因此在第一連接元件22均勻受熱,而與晶片20之主動面連接界面之間不會產生微小空隙(即直線(晶片20)與弧線(第一連接元件22)接觸界面所構成之缺口),而使得底膠填充封膠材料30時,可以完全包覆第一連接元件30及覆蓋住晶片20之主動面(未在圖中表示)。接著,再繼續進行填充步驟,將封膠材料30繼續填充並完全包覆晶片20之主動面及複數個第一連接元件22。
因此,根據以上所述,在第2B圖及第3B圖中,很明顯的得到,在經過一次或是多次紅外線回焊步驟之後,在晶片20之主動面(未在圖中表示)與複數個第一連接元件22之間係由封膠材料30完全填充並包覆,而不會產生晶片20的連接元件短路。
參考第4圖,係根據第2A圖及第2B圖,表示本發明所揭露之檢測覆晶球柵封裝結構之方法之流程圖。步驟70,提供一基板,在基板的上下表面分別具有複數個焊墊(pad)及在基板內具有中介層(interposer)及內連線結構(interconnect structure);步驟72,提供一晶片,且於主動面上具有複數個第一連接元件(connecting element);步驟74,設置晶片在基板之表面上,係將晶片上下反轉,使得主動面朝下且在晶片之主動面上的複數個第一連接元件與基板透過中介層與內連線結構電性連接;步驟76,至少執行一次紅外線回焊(IR reflow)步驟,使得晶片之主動面上之複數個第一連接元件固接於基板上;步驟78,填充一封膠材料以包覆晶片之主動面及複數個第一連接元件;步驟80,執行一檢測步驟,以檢測封膠材料包覆複數個第一連接元件與晶片之主動面之間是否具有空隙存在;及步驟82,形成複數個第二連接元件在基板之背面,以完成一覆晶球柵陣列封裝結構。
參考第5圖,係根據以第3A圖及第3B圖,表示本發明所揭露之檢測覆晶球柵封裝結構之另一方法之流程圖。步驟70,提供一基板,在基板的上下表面分別具有複數個焊墊(pad)及在基板內具有中介層(interposer)及內連線結構(interconnect structure);步驟72,提供一晶片,且於主動面上具有複數個第一連接元件(connecting element);步驟74,設置晶片在基板之表面上,係將晶片上下反轉,使得主動面朝下且在晶片之主動面上的複數個第一連接元件與基板透過中介層與內連線結構電性連接;步驟76,至少執行一次紅外線回焊(IR reflow)步驟,使得晶片之主動面上之複數個第一連接元件固接於基板上;步驟78,填充一封膠材料以包覆晶片之主動面及複數個第一連接元件;步驟80,執行一檢測步驟,以檢測封膠材料包覆複數個第一連接元件與晶片之主動面之間是否具有空隙存在。在此,步驟70至步驟82係與第4圖相同,其差異性在於步驟90,係形成複數個支撐元件在基板之上表面,且鄰近於晶片但與晶片電性隔離;步驟92,係設置散熱元件在支撐元件及晶片之背面上;及步驟94,形成複數個第二連接元件在基板之另一表面上以完成一覆晶球柵陣列封裝結構。
因此,綜合以上所述,為了避免在底膠填充時,封膠材料無法完整覆蓋住晶片之主動面及複數個第一連接元件之間因結構所造成之空隙,在本發明中係執行一次或多次的紅外線回焊步驟,藉由紅外線回焊可以均勻加熱之優點,使得複數個第一連接元件可均勻受熱,而使得原本存在於晶片之主動面及複數個第一連接元件之間的空隙可以被偵測出來,使得在底膠填充時,可以將封膠材料完全覆蓋並包覆於晶片之主動面及第一連接元件,不會產生連接元件的短路,也消除了習知技術中底膠缺陷的問題。
以上所述僅為本發明之較佳實施例而已,並非用以限定本發明之申請專利範圍;凡其它未脫離本發明所揭示之精神下所完成之等效改變或修飾,均應包含在下述之申請專利範圍內。
10...基板
10A...上表面
10B...下表面
12...焊墊
14...中介層
16...內連線結構
20...晶片
22...第一連接元件
30...封膠材料
40...支撐元件
50...散熱元件
60...第二連接元件
100...基板
110...晶片
112...錫球
114...底膠
120...空隙
130...金屬環
140...散熱片
150...錫球
70...提供具有內連接層及中介層之基板
72...提供一晶片,於主動面上具有複數個第一連接元件
74...設置晶片在基板上且藉由複數個第一連接元件與基板電性連接
76...至少執行一次紅外線迴焊使得複數個第一連接元件固接於基板上
78...填充一封裝材料以包覆晶片及複數個第一連接元件
80...執行檢測步驟,以檢測封膠材料完整包覆複數個第一連接元件與該晶片之該主動面之間且不具有空隙
82...繼續填充一封裝材料以包覆晶片及複數個第一連接元件
84...形成複數個第二連接元件在基板之另一表面上以完成一覆晶球柵陣列封裝結構
90...形成複數個支撐元件在基板上且鄰近於晶片但與晶片電性隔離
92...設置散熱元件在支撐元件及晶片之背面上
94...形成複數個第二連接元件在基板之另一表面上以完成一覆晶球柵陣列封裝結構
第1A圖係表示習知之覆晶球柵陣列封裝結構之示意圖;
第IB圖係表示習知技術中在覆晶球柵陣列封裝結構中之底膠缺陷之放大示意圖;
第2A圖係根據本發明所揭露之技術,表示形成不具有底膠缺陷之覆晶球柵陣列封裝結構;
第2B圖係根據本發明所揭露之技術,表示在覆晶球柵陣列封裝結構中之無底膠缺陷之放大示意圖;
第3A圖係根據本發明所揭露之技術,表示形成不具有底膠缺陷之具有支撐元件及散熱元件之覆晶球柵陣列封裝結構;及
第3B圖係根據本發明所揭露之技術,表示在具有支撐元件及散熱元件之覆晶球柵陣列封裝結構中之無底膠缺陷之放大示意圖;
第4圖係根據第2A圖至第2B圖之覆晶球柵陣列封裝結構之表示檢測底膠缺陷之步驟流程圖;及
第5圖係根據第3A圖至第3B圖之具有支撐元件及散熱元件之覆晶球柵陣列封裝結構之表示檢測底膠缺陷之步驟流程圖。
10...基板
10A...上表面
10B...下表面
12...焊墊
14...中介層
16...內連線結構
20...晶片
22...第一連接元件
30...封膠材料
40...支撐元件
50...散熱元件
60...第二連接元件

Claims (16)

  1. 一種形成覆晶球柵陣列封裝結構之方法,包含:提供一基板,且具有一內連線結構及複數個中介層;提供一晶片,具有一主動面及一背面且於該主動面上具有複數個第一連接元件;設置該晶片於該基板上,係將該晶片上下反轉,使得該晶片之該主動面朝下,且該晶片之該些第一連接元件與該基板透過該中介層與該內連線結構電性連接;執行一次紅外線回焊步驟,使得該些第一連接元件與該基板固接;填充一封膠材料以包覆該晶片之該主動面及該些第一連接元件;形成複數個第二連接元件在該基板之該背面,以完成一覆晶球柵陣列封裝結構;以及執行一檢測步驟,以檢測該些第一連接元件與該晶片之該主動面之間是否具有空隙存在,其中執行該檢測步驟係在填充該封膠材料步驟之後,以及在形成該些第二連接元件之間。
  2. 如申請專利範圍第1項所述之方法,更包含設置複數個焊墊在該基板與該晶片之該複數個第一連接元件之間。
  3. 如申請專利範圍第1項所述之方法,其中該晶片包含定制靜態動態存取記憶體。
  4. 如申請專利範圍第1項所述之方法,其中該封膠材料包含環氧樹脂。
  5. 如申請專利範圍第1項所述之方法,其中該檢測方法包含x光繞射法。
  6. 如申請專利範圍第1項所述之方法,更包含於該檢測步驟之後,再執行一填充步驟。
  7. 如申請專利範圍第1項所述之方法,其中該些第一連接元件及該些第二連接元件為錫球。
  8. 一種形成覆晶球柵陣列封裝結構之方法,包含:提供一基板,且具有一內連線結構及複數個中介層;提供一晶片,具有一主動面及一背面且於該主動面上具有複數個第一連接元件;設置該晶片於該基板上,係將該晶片上下反轉,使得該晶片之該主動面朝下,且該晶片之該些第一連接元件與該基板透過該些中介層與該內連線結構電性連接;執行一次紅外線回焊,使得該晶片之該些第一連接元件固接於該基板上;預先填充一封膠材料以包覆該晶片之該主動面及該些第一連接元件;執行一填充步驟,係繼續填充該封膠材料以完全包覆該些第一連接元件與該晶片之該主動面;執行一檢測步驟,以檢測該些第一連接元件與該晶片之該主動面之間是否具有空隙存在,其中執行該檢測步驟係在預先填充該封膠材料步驟之後,以及在該填充步驟之間; 形成複數個支撐元件在該基板上且鄰近於該晶片但與該晶片電性隔離;設置一散熱元件在該些支撐元件及該晶片之該背面上;以及形成複數個第二連接元件在該基板之一背面,以完成一覆晶球柵陣列封裝結構。
  9. 如申請專利範圍第8項所述之方法,更包含設置複數個焊墊在該基板與該晶片之該些第一連接元件之間。
  10. 如申請專利範圍第8項所述之方法,其中該晶片包含定制靜態動態存取記憶體。
  11. 如申請專利範圍第8項所述之方法,其中該封膠材料為環氧樹脂。
  12. 如申請專利範圍第8項所述之方法,其中該檢測方法包含x光繞射法。
  13. 如申請專利範圍第8項所述之方法,更包含形成一黏著層在該些支撐元件與該基板之間。
  14. 如申請專利範圍第8項所述之方法,其中該些支撐元件的材料包含銅、銅碳、銅鎢、碳化矽鋁、鋁、不銹鋼、鎳及鍍鎳之銅。
  15. 如申請專利範圍第8項所述之方法,更包含形成一黏著層在該散熱元件與該些支撐元件及該晶片之該背面之間。
  16. 如申請專利範圍第8項所述之方法,其中該些第一連接元件及該些第二連接元件為錫球。
TW099129198A 2010-08-31 2010-08-31 覆晶球柵式陣列封裝之底膠缺陷之檢測方法 TWI450349B (zh)

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US9245773B2 (en) 2011-09-02 2016-01-26 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device packaging methods and structures thereof
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Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200400591A (en) * 2002-01-18 2004-01-01 Ibm High density raised stud microjoining system and methods of fabricating the same
TW200427019A (en) * 2003-05-26 2004-12-01 Thin Film Module Inc Flip chip BGA
TW200512906A (en) * 2003-09-23 2005-04-01 Advanced Semiconductor Eng Method for mounting passive component on wafer
TWI233672B (en) * 2003-05-26 2005-06-01 Subtron Technology Co Ltd High density substrate for flip chip
TWI260792B (en) * 2005-07-26 2006-08-21 United Microelectronics Corp Flip chip package with reduced thermal stress
TW200901406A (en) * 2007-06-22 2009-01-01 Phoenix Prec Technology Corp Electrically connection element structure of packaging substrate

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW525274B (en) * 2001-03-05 2003-03-21 Samsung Electronics Co Ltd Ultra thin semiconductor package having different thickness of die pad and leads, and method for manufacturing the same
US6861750B2 (en) * 2002-02-01 2005-03-01 Broadcom Corporation Ball grid array package with multiple interposers

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200400591A (en) * 2002-01-18 2004-01-01 Ibm High density raised stud microjoining system and methods of fabricating the same
TW200427019A (en) * 2003-05-26 2004-12-01 Thin Film Module Inc Flip chip BGA
TWI233672B (en) * 2003-05-26 2005-06-01 Subtron Technology Co Ltd High density substrate for flip chip
TW200512906A (en) * 2003-09-23 2005-04-01 Advanced Semiconductor Eng Method for mounting passive component on wafer
TWI260792B (en) * 2005-07-26 2006-08-21 United Microelectronics Corp Flip chip package with reduced thermal stress
TW200901406A (en) * 2007-06-22 2009-01-01 Phoenix Prec Technology Corp Electrically connection element structure of packaging substrate

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