TW200427019A - Flip chip BGA - Google Patents

Abstract

A flip chip BGA package is provided with a metal substrate 200, a thin film interconnect layer 202, a built-up structure layer 208, a flip chip 260, a solder mask layer 220, an underfill 270 and solder balls 280. A chip placement opening 250 formed with a placement region, a dispensing region, and a vacuum region is arranged in the metal substrate 200. The flip chip 260 is placed in the chip placement opening 250 to electrically connect with the thin film interconnect layer 202. The solder mask layer 220 is formed over the built-up structure layer 208 and exposes partial of the trace layer 216 that is most far away from the metal substrate 200. The gaps between the bumps 262 are filled with the underfill 270. Solder balls 280 are electrically connected with the trace layer 216 exposed by the solder mask layer 220.

Description

200427019 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a F 1 ip Chip Ball Grid Array Package and its manufacturing process. A high-density flip-chip ball grid array package and its manufacturing process. [Previous Technology] The development trend of chip packaging technology is toward reduction in size and increase in input / output contacts, so flip-chip (f 1 i p c h i p) technology has become one of the mainstream. The flip-chip technology mainly forms long bumps on external contacts (usually metal pads) on the wafer, and is electrically connected to the substrate through the bumps. With flip-chip technology, I / O contacts can be connected at high density, and low-inductance connections can be established. The structure of the conventional package substrate is made by a laminated method or a build-up method, so the flatness (u n i f 0 r m i t y) of the outer layer is gradually deteriorated, so accuracy control is difficult. Therefore, when the package substrate is applied to the requirements of high density and fine pitch of a flip-chip package, the manufacturing difficulty is high and the yield is affected. In addition, when the conventional high-density substrate is applied to the flip-chip technology, in order to achieve the stability of the inter-layer alignment, a thicker inner substrate must be used, so the total thickness of the substrate is high, resulting in poor telecommunication performance. Due to the high hardness of conventional high-density substrates, the stress and strain caused by the difference in thermal expansion coefficients between the substrate and the wafer during operation will cause damage to the insulating layer on the wafer after implantation. [Summary of the Invention] In order to solve the conventional problems, one object of the present invention is to propose

10392twf.ptd Page 6 200427019 V. Description of the invention (2) A flip-chip ball grid array package and its process can achieve high telecommunication performance through a thin package. One of the objects of the present invention is to provide a flip-chip ball grid array package and a manufacturing process thereof, which can be applied to package a flip-chip wafer with micro-pitch bumps. One of the objectives of the present invention is to provide a flip-chip ball grid array package and a manufacturing process thereof, which can reduce the stress and strain to which the wafer is subjected, so as to improve the package yield and reliability. In order to achieve the above and other objectives, the present invention proposes a flip-chip ball grid array package, including: a metal substrate, a thin film interconnect layer, a laminated structure layer, a flip-chip wafer, a solder mask layer, and a primer. , And multiple solder balls. The metal substrate has a wafer placement opening, and the wafer placement opening has a wafer placement area, a glue area, and an evacuation area, and the dispensing is covered along the wafer placement area on the metal substrate. The flip-chip wafer is electrically connected to the thin film to expose the laminated structure. The adhesive is filled in the wires exposed by the bumps. It further includes a dielectric layer penetrating and interconnecting the substrate with the thin film, the conductive layer of the board, the gold area and the vacuum The area is connected to the wafer placement area and is a pair of areas extending diagonally outward. The surface of a thin film interconnector. The laminated structure layer is covered on the interconnections of the film and attached to the opening for placing the chip. The interconnections are interconnected by a plurality of bumps. The solder mask layer is a layer on the laminated structure layer, and a part of the layer is the wire layer farthest from the metal substrate. The gap between the bottom. The solder balls are electrically connected to the solder mask layer. In the flip chip lattice package package of the present invention, the holes are located outside the wafer placement area of the metal substrate, the dielectric layer of the through-layer, and the closest layer of the laminated structure layer make the through-hole contact the closest to the laminated structure layer. Metal base

10392twf.ptd Page 7 200427019 V. Description of the invention (3) It belongs to the substrate and at the same time contacts the wire layer in the interconnection layer of the film. The invention further provides a flip-chip ball grid array packaging method, which includes providing a metal substrate with a first surface and a second surface. An interconnecting layer is formed by a thin film deposition method and covers the first surface of the metal substrate. A lamination structure layer is formed by the lamination method, and the interconnection layer is covered. A solder resist layer is formed, covering the laminated structure layer, and exposing a part of the wiring layer of the laminated structure layer farthest from the metal substrate. A wafer placement opening is formed on the second surface of the metal substrate to expose a part of the interconnected dielectric layer. The wafer placement opening has a wafer placement area, a glue area, and a vacuum area. The glue area and the evacuation area are connected to the wafer placement area and are a pair of areas extending outward along the diagonal of the wafer placement area. A plurality of bump openings are formed in the exposed dielectric layer of the interconnect to expose a portion of the interconnect layer of the interconnect layer. Attaching a flip-chip wafer to the wafer placement opening 'This flip-chip wafer has a plurality of bumps, so that the bumps are electrically connected to the conductor layer of the interconnecting layer exposed by the bump openings. A primer filling step is performed. The glue is dispensed in the dispensing area where the wafer is placed, and the vacuum is evacuated to fill a gap between the bumps with a primer. A ball-planting step is performed to electrically connect a plurality of solder balls to the conductive layer of the laminated structure layer farthest from the metal substrate in the exposed portion of the solder mask. The circuit pattern of each of the above-mentioned wire layers is wavy at the edge corresponding to the opening where the wafer is placed. According to the features of the present invention, a pair of dispensing areas and vacuum-extracting areas extend diagonally across the wafer placement area. Therefore, the present invention performs dispensing on one side of the wafer placement area and vacuuming on the opposite side. Way 'may

10392twf.ptd Page 8 200427019 V. Description of the invention (4) Shorten the time for filling the bottom glue, and can effectively prevent the occurrence of air bubbles. The same as above, because the dispensing area and the vacuum area have been set in the wafer placement opening, the wafer placement area can be minimized, and the reliability of the package can be improved. According to the features of the present invention, a through hole is used to make the second wire layer of the laminated structure layer closest to the metal substrate contact the metal substrate, and at the same time contact the first wire layer of the film interconnect layer, and then ground the metal substrate, which is good. Effect of current delivery. According to the features of the present invention, each wire layer is wavy at the edge corresponding to the opening on which the wafer is placed, and has a buffering effect when the substrate is deformed, thereby improving the substrate's ability to withstand strain. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: [Embodiment] Please refer to the 1 to 11 are cross-sectional views showing a process flow of a flip-chip ball grid array package according to a preferred embodiment of the present invention. Referring to FIG. 1, a metal substrate 200 is provided, which has a first surface 200a and a second surface 200b. Referring to FIG. 2, a thin film deposition method is used to form an interconnecting layer 2 0 2 and cover the first surface 2 0 a of the metal substrate 2 0 0. For example, a first dielectric layer 204 is formed in a coating manner, and a first wire layer 206 is formed, for example, by a sputtering method and a semi-additive method. The first dielectric layer 204 covers the first surface 200a of the metal substrate 200. The first wire layer 206 is overlying the first dielectric layer

10392twf.ptd Page 9 200427019 V. Description of the invention (5) 2 0 4 〇 ♦ Please refer to Figures 3 to 5 to form a multilayer structure layer 2 0 8 (see Figure 5) by the bui 1 tup method. It is formed alternately with a dielectric layer and a wire layer, and covers the interconnect layer 202. As shown in FIG. 3, a patterned second dielectric layer 2 1 0 is formed, covering the interconnect layer 2 02. Next, as shown in FIG. 4, a patterned second wiring layer 212 is formed, and is covered on the second dielectric layer 210. In the process of forming the multilayer structure 208, the following steps have been added to improve the current delivery effect of the wafer (see Figure 4). As exemplified in Figure 4, a through hole 2 1 8 is formed by means of laser drilling (Figure 3) and electroplating (Figure 4), and the wafer placement opening 2 500 on the metal substrate 2 500 is placed. Area 2 50 a (see details in FIG. 11 described later), penetrates the first dielectric layer 204 and the adjacent second dielectric layer 210 to contact the second closest to the metal substrate 2 0 0 The wire layer 21 2 and the metal substrate 200 are in contact with the first wire layer 206 at the same time. Here, the metal substrate 200 can be connected to the ground, and in accordance with the structural characteristics of the through-hole 2 18 described above, a short and wide ground connection can be formed, thereby greatly improving the current transmission efficiency of the chip. As shown in FIG. 5, a patterned second dielectric layer 2 1 4 is continuously formed, covering the second wiring layer 212, and then a patterned second wiring layer 216 is formed, covering the second dielectric layer. 212. Next, referring to FIG. 6, a solder resist layer 2 2 0 is formed and covered with the laminated structure layer 2 0 8. This solder resist layer has a plurality of openings 2 2 0 a to expose a part farthest from the metal substrate 2000. Of the second wire layer 216. A solder ball pad 22 is formed on the second guide layer 216 exposed by the opening 220a.

10392twf.ptd Page 10 200427019 V. Description of the invention (6) Please refer to Figure 7 to form a wafer placement opening 2 50 on the second surface 200b of the metal substrate 200 to expose a portion of the first dielectric layer 204. Please refer to FIG. 11 at the same time. The wafer placement opening 2 50 has a wafer placement area 2 5 0 a, a little glue area 2 5 0 b, and a vacuum area 2 5 0 c. The reference numeral 2 6 0 indicates this. The flip chip to be attached in the area (see Figure 9 for details). The shape of the wafer placement opening 2 50 is as follows. The wafer placement area 2 50 a is slightly larger than the flip-chip wafer 2 60. The dispensing area 2 5 0 a and the vacuum area 2 50 0 b are placed on the wafer. Regions 250a are connected 'and extend a pair of regions outwardly along the diagonal of the wafer placement region 250a. Referring to FIG. 8, a plurality of bump openings 252 are formed in the exposed first dielectric layer 204 to expose a portion of the first wire layer 206. Methods of forming bump openings include, for example, laser drilling. Please refer to FIG. 9 and attach a flip-chip wafer 2 60 to a wafer placement area 250 a in the wafer placement opening 250. The flip-chip wafer 260 has an active surface 260a, and a plurality of bumps 262 are formed on the active surface 260a. Through a re-soldering step, the bumps 2 6 2 and the first wire layer 2 0 6 exposed by the bump openings 2 5 2 are electrically connected. Next, a primer filling step is performed, the glue is dispensed in the dispensing area 250b of the opening 250 where the wafer is placed, and the vacuum is evacuated in the evacuation area 250c to fill a bump 2 7 0 into the bump 2 6 2 Gap between. According to the spirit of the present invention, it is not necessary to limit the shape of the wafer placement opening 250. The key is that the wafer placement area 250a is close to and slightly larger than the shape of the flip-chip wafer 260. The dispensing area 2 50 a and the evacuation area 2 5 0 b are connected to the wafer placement area 2 50 0 a and are respectively located opposite to the wafer placement area 2 50 0 a.

10392rwf.ptd Page 11 200427019 V. Description of the invention (7) side to facilitate vacuuming operation. Then, a glue step is performed, and a wafer material 2 900 is filled into the wafer placement opening 2 50 to cover the bottom glue 2 7 0 to surround the flip-chip wafer 2 600 and a part of the flip-chip wafer is exposed. 2 6 0. Please refer to FIG. 10, and perform a ball-planting step. A plurality of solder balls 2 8 0 are electrically connected to the solder mask 2 2 0 through the solder ball pad 2 2 2 as far away from the metal substrate 2 as possible. 0 0 of the second wire layer 2 1 6, thus completing the flip-chip ball grid array package. Please refer to FIG. 12, which shows an example of a wiring pattern corresponding to the periphery of the chip placement opening of each wire layer. The first wire layer is taken as an example in the figure. It is worth noting here that when forming the above-mentioned wire layer (206, 21, 2, 16), each wire layer is at the edge of the corresponding chip placement opening 2 50 (as shown by the dashed line 2 4 8 in the figure) Wavy line pattern. The reason for forming the wavy line pattern at the side corresponding to the opening where the wafer is placed is as follows: According to the features of the present invention, in the flip-chip ball grid array package of the present invention, the portion outside the wafer placement opening, All include metal substrates, thin-film interconnect layers, and laminated structure layers. However, there is no part of the metal substrate in the wafer placement opening, so this packaging structure becomes weaker in the structure around the corresponding wafer placement opening. Part. According to the spirit of the present invention, the use of a wavy elongated circuit pattern at the edges of the chip placement openings 250 is a buffering effect when the substrate is deformed (such as thermal expansion), so that the wires are not deformed and deformed. Damage, which can increase the reliability of the product. It can be seen that the present invention does not need to be limited to this wave shape, in short, such as a sawtooth shape, or other bent shapes are all

I0392twf.ptd Page 12 200427019 V. Description of Invention (8). It can be known from the disclosure of the embodiment (1) that the present invention is in the empty area of the wafer placement area. Therefore, the present invention is to vacuum the opposite side of the wafer, and can effectively prevent the occurrence of air bubbles (2). The same as above, Because in the wafer vacuum area, the wafer placement area can be maximized (3). The present invention uses through holes to make the laminated two conductor layers contact the metal substrate, and the conductor layer, and then the metal substrate is grounded and conveyed. (4). Each wire layer of the present invention is in the opposite shape, and has the ability to slow the strain when the substrate is deformed, thereby improving the yield. Although the present invention has been better defined to limit the present invention, anyone familiar with this god and scope, when The scope of protection can be a little. When the attached patent is applied, the invention has at least the following advantages: Diagonally extending a pair of dispensing areas and a stack of real placement areas for dispensing, and in this way, the bottom filling can be shortened When the glue is placed, the dispensing area has been set and the size is reduced, which improves the reliability of the package. The structure layer closest to the metal substrate and the first contacting the film interconnect layer at the same time, can make the flip-chip wafer obtain a good electro-response. The placement of the wafer is wave impulse, so the reliability of the substrate can be improved. . The embodiment is disclosed as above, but it is not an artist, and it does not deviate from the refinement and retouching of the present invention. Therefore, what is defined by the scope of the present invention shall prevail.

10392twf.ptd Page 13 200427019 Brief Description of the Drawings Figures 1 to 10 are cross-sectional views of a flip-chip ball grid array packaging process according to a preferred embodiment of the present invention; Figure 11 shows a comparison according to the present invention. An exemplary plan view of a wafer placement opening of the preferred embodiment; and FIG. 12 illustrates an exemplary plan view of a wiring pattern of each wire layer according to a preferred embodiment of the present invention. [Illustration of Graphical Symbol] 2 00 metal substrate 2 0 2: interconnecting layer (thin film interconnecting layer) 2 04 first dielectric layer 2 0 6: first wiring layer 208 laminated structure layer 210 ′ 214: second Dielectric layers 212, 2 16: Second: lead layer 218: through hole f 220 solder mask 2 2 0a: opening 222 solder ball pad 2 4 8: edge of wafer placement opening 250 wafer placement opening 2 5 0 a: Wafer placement area 2 5 0 b: Dispensing area 2 5 0 c: Evacuation area 252: Bump opening 2 6 0: Chip on wafer 2 6 0 a: Active surface 2 6 2: Bump 270: Primer 2 8 0: Solder ball 2 9 0: Sealant

10392twf.ptd Page 14

Claims (1)

200427019 VI. Application Patent Scope 1. A flip-chip ball grid array package, comprising: a gold layer substrate having a first surface and a second surface, and the metal substrate has a wafer placement opening, and the wafer placement opening has A wafer placement area, a glue area, and a vacuum area, wherein the glue area and the vacuum area are connected to the wafer placement area and are a pair of areas extending outward along the diagonal of the wafer placement area; A thin film interconnect layer covers the first surface of the metal substrate. The thin film interconnect layer has a first dielectric layer and a first wire layer, and the first dielectric layer covers the metal substrate. The first surface, the first wire layer covering the first dielectric layer, wherein a plurality of bump openings are further provided in the first dielectric layer in the wafer placement opening; a laminated structure layer covering the first dielectric layer; A thin film interconnecting layer having a plurality of second dielectric layers and a plurality of second conducting layers alternately with each other, and a second dielectric layer is provided between every two adjacent second conducting layers; Wafer attached to the wafer In the opening, the flip-chip wafer has an active surface, and a plurality of bumps are formed on the active surface. The flip-chip wafer is electrically connected to the exposed portions of the bump openings through the bumps. A first wire layer; a solder mask layer covering the laminated structure layer, the solder mask layer having a plurality of openings to expose a portion of the second wire layer farthest from the metal substrate; a primer, filled in A gap between the bumps; and a plurality of solder balls, which are electrically connected to the second wire layer farthest from the metal substrate of the exposed portion of the solder mask opening. 10392twf. Ptd Page 15 200427019 6. Application for patent scope 2. The flip-chip ball grid array package described in item 1 of the patent application scope further includes a through hole located outside the wafer placement area of the metal substrate and penetrating The first dielectric layer and the second dielectric layer adjacent to the first dielectric layer to contact the second wire layer closest to the metal substrate, contact the metal substrate, and contact the first wire at the same time Floor. 3. The flip-chip lattice-lattice package as described in item 2 of the patent application scope, wherein the metal substrate is used as a ground point. 4. According to the flip-chip ball grid array package described in item 1 of the scope of patent application, the wafer placement area of the wafer placement opening is slightly larger than the shape of the flip-chip wafer. 5. The flip-chip ball grid array package according to item 1 of the scope of the patent application, wherein the circuit patterns of the first wire layer and the second wire layers are wavy at the edges corresponding to the openings where the wafer is placed. 6. The flip-chip ball grid array package as described in item 1 of the scope of patent application, further comprising a piece of glue filled in the wafer placement opening to cover the primer, surround the flip-chip wafer, and expose Part of the flip chip. 7. A chip-on-ball grid array packaging method, comprising: providing a metal substrate having a first surface and a second surface; forming an interconnect layer by a thin film deposition method, and covering the first substrate and the second substrate; A surface forming a first dielectric layer and a first wire layer, the first dielectric layer covering the first surface of the metal substrate, and the first wire layer covering the first dielectric layer; Forming a laminated structure layer by a lamination method and covering the interconnection layer includes: forming a second dielectric layer, forming a second wire layer covering the second dielectric layer; 10392twf.ptd Page 16 200427019 VI. Patent application scope Electric layer, repeat this step several times to form the laminated structure layer; form a solder mask layer, cover the laminated structure layer, the solder mask layer has a plurality of openings A portion of the second wire layer farthest from the metal substrate is exposed; a wafer placement opening is formed on the second surface of the metal substrate to expose a portion of the first dielectric layer, and the wafer is placed The opening has a wafer placement area, a glue area, and a vacuum extraction area, wherein the dispensing area and the vacuum extraction area are connected to the wafer placement area and are a pair of pairs extending outward along the diagonal of the wafer placement area. Area; forming a plurality of bump openings in the exposed first dielectric layer to expose a portion of the first wire layer; attaching a flip-chip wafer in the wafer placement opening, the flip-chip wafer An active surface is provided, and a plurality of bumps are formed on the active surface, so that the bumps are electrically connected to the first wire layer exposed by the bump openings; a primer filling step is performed at the Chip Place the dispensing area of the opening for dispensing, and perform a vacuum in the evacuation area to fill a gap between the bumps; and perform a ball-planting step to electrically connect a plurality of solder balls The portion of the solder resist layer exposed farthest from the second wire layer of the metal substrate. 8. The flip-chip ball grid array packaging method according to item 7 of the scope of the patent application, wherein in the step of forming the laminated structure layer, further comprising: forming a through hole located outside the wafer placement area of the metal substrate Through the first dielectric layer and the second dielectric adjacent to the first dielectric layer 10392twf.ptd Page 17 200427019 Substrate method mounting method, 11 mounting method, 12 mounting method, 6. Apply for a patent scope electric layer to contact the metal closest to it and contact the first guide 9 at the same time. Where the through-holes are formed 10. If the scope of the patent application is the first, the metal substrate is formed by the bump scope openings. The first guide is formed by the patent scope, which includes placing on the corresponding wafer. Open circuit pattern. 1 3. If the mounting method is within the scope of the patent application, it further includes an adhesive step for opening, so as to cover the primer and the chip-on-wafer. The second wire layer and the metal wire layer of the substrate. The flip chip array packaging method described in the item includes laser drilling and plating. The flip chip lattice array seal as described in item 9 is connected to the ground. The method of flip-chip ball grid array sealing according to item 7 includes laser drilling. The chip-on-chip lattice array type sealing wire described in item 7 and the method of the second wire layers are formed at the edges of the chip-on-chip lattice-shaped array seal of item 7 in a wave shape. Material fills the wafer to surround the flip-chip wafer and exposes a portion « 10392twf.ptd Page 18