TW200427019A - Flip chip BGA - Google Patents
Flip chip BGA Download PDFInfo
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- TW200427019A TW200427019A TW092114125A TW92114125A TW200427019A TW 200427019 A TW200427019 A TW 200427019A TW 092114125 A TW092114125 A TW 092114125A TW 92114125 A TW92114125 A TW 92114125A TW 200427019 A TW200427019 A TW 200427019A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
200427019 五、發明說明(1) [發明所屬之技術領域] 本發明是有關於一種覆晶球格陣列式封裝(F 1 i p Chip Ball Grid Array Package),及其製程,且特另丨J 是 有關於一種高密度覆晶球格陣列式封裝及其製程。 [先前技術] 晶片封裝技術的發展趨勢朝向尺寸縮小及輸入/輸出 接點增加,因而覆晶(f 1 i p c h i p )技術成為主流之一。覆 晶技術主要是在晶圓上對外的接點(通常是金屬焊墊)上成 長凸塊,並透過凸塊與基板(substrate)電性連接。運用 覆晶技術可以高密度地連接輸入/輸出接點,並可建立低 電感連接。 習知封裝基板的構成係以壓合方式(laminated)或是 積層方式(build up)製成,所以越外層的部份由於平坦度 (u n i f 〇 r m i t y )漸差,所以精度控制困難。以此封裝基板應 用於覆晶封裝之高密度(high density)及小間距(fine pitch)的需求時,製作困難度高,並對良率造成影響。 此外,習知的高密度基板應用於覆晶技術時,為達 成層間對位之穩定性,必須使用較厚之内層基板,因此基 板之總厚度高,造成電訊性能不良。 又因習知高密度基板之硬度高,植入覆晶晶片之 後,在運作時由於基板與晶片熱膨脹係數之差異,其所產 生的應力與應變會造成晶片上絕緣層之損害。 [發明内容] 為解決習知的問題點,本發明的目的之一係,提出200427019 V. Description of the invention (1) [Technical field to which the invention belongs] The present invention relates to a F 1 ip Chip Ball Grid Array Package and its manufacturing process. A high-density flip-chip ball grid array package and its manufacturing process. [Previous Technology] The development trend of chip packaging technology is toward reduction in size and increase in input / output contacts, so flip-chip (f 1 i p c h i p) technology has become one of the mainstream. The flip-chip technology mainly forms long bumps on external contacts (usually metal pads) on the wafer, and is electrically connected to the substrate through the bumps. With flip-chip technology, I / O contacts can be connected at high density, and low-inductance connections can be established. The structure of the conventional package substrate is made by a laminated method or a build-up method, so the flatness (u n i f 0 r m i t y) of the outer layer is gradually deteriorated, so accuracy control is difficult. Therefore, when the package substrate is applied to the requirements of high density and fine pitch of a flip-chip package, the manufacturing difficulty is high and the yield is affected. In addition, when the conventional high-density substrate is applied to the flip-chip technology, in order to achieve the stability of the inter-layer alignment, a thicker inner substrate must be used, so the total thickness of the substrate is high, resulting in poor telecommunication performance. Due to the high hardness of conventional high-density substrates, the stress and strain caused by the difference in thermal expansion coefficients between the substrate and the wafer during operation will cause damage to the insulating layer on the wafer after implantation. [Summary of the Invention] In order to solve the conventional problems, one object of the present invention is to propose
10392twf.ptd 第6頁 200427019 五、發明說明(2) 一種覆晶球格陣列式封裝及其製程,可由薄型封裝達成高 電訊性能。 本發明的目的之一係,提出一種覆晶球格陣列式封 裝及其製程,可適用於封裝具微間距凸塊之覆晶晶片。 本發明的目的之一係,提出一種覆晶球格陣列式封 裝及其製程,可降低晶片所承受的應力及應變,以提高封 裝之良率及可靠度。 為達成上述及其他目的,本發明提出一種覆晶球格 陣列式封裝,包括:一金屬基板、一薄膜内連線層、一積 層結構層、一覆晶晶片、一防焊層、一底膠,以及多個焊 球。其中,金屬基板具有一晶片放置開口,此晶片放置開 口具有一晶片放置區、一點膠區及一抽真空區,其中點膠 沿晶片放置區之 係,覆於金屬基 層。覆晶晶片係 電性連接至薄膜 暴露出積層結構 膠係填入於凸塊 暴露出之導線 1更包括一貫 穿與薄膜内連線 基板之介電層, 板之導線層及金 區及抽真空區係與晶片放置區相連,並為 對角往外延伸之一對區域。薄膜内連線層 板之表面。積層結構層係覆於薄膜内連線 貼附於晶片放置開口内,藉由多個凸塊, 内連線層。防焊層係覆於積層結構層,並 層中部份之最遠離金屬基板之導線層。底 之間的間隙。焊球係電性連接至防焊層所 層。 在本發明之覆晶球格陣列式封裝中 孔,位於金屬基板之晶片放置區之外,貫 層之介電層,及積層結構層中最接近金屬 以使貫孔接觸積層結構層中最接近金屬基10392twf.ptd Page 6 200427019 V. Description of the invention (2) A flip-chip ball grid array package and its process can achieve high telecommunication performance through a thin package. One of the objects of the present invention is to provide a flip-chip ball grid array package and a manufacturing process thereof, which can be applied to package a flip-chip wafer with micro-pitch bumps. One of the objectives of the present invention is to provide a flip-chip ball grid array package and a manufacturing process thereof, which can reduce the stress and strain to which the wafer is subjected, so as to improve the package yield and reliability. In order to achieve the above and other objectives, the present invention proposes a flip-chip ball grid array package, including: a metal substrate, a thin film interconnect layer, a laminated structure layer, a flip-chip wafer, a solder mask layer, and a primer. , And multiple solder balls. The metal substrate has a wafer placement opening, and the wafer placement opening has a wafer placement area, a glue area, and an evacuation area, and the dispensing is covered along the wafer placement area on the metal substrate. The flip-chip wafer is electrically connected to the thin film to expose the laminated structure. The adhesive is filled in the wires exposed by the bumps. It further includes a dielectric layer penetrating and interconnecting the substrate with the thin film, the conductive layer of the board, the gold area and the vacuum The area is connected to the wafer placement area and is a pair of areas extending diagonally outward. The surface of a thin film interconnector. The laminated structure layer is covered on the interconnections of the film and attached to the opening for placing the chip. The interconnections are interconnected by a plurality of bumps. The solder mask layer is a layer on the laminated structure layer, and a part of the layer is the wire layer farthest from the metal substrate. The gap between the bottom. The solder balls are electrically connected to the solder mask layer. In the flip chip lattice package package of the present invention, the holes are located outside the wafer placement area of the metal substrate, the dielectric layer of the through-layer, and the closest layer of the laminated structure layer make the through-hole contact the closest to the laminated structure layer. Metal base
10392twf.ptd 第7頁 200427019 五、發明說明(3) 屬基板,而同時接觸薄膜内連線層中的導線層。 本發明更提出一種覆晶球格陣列式封裝方法,包 括··提供一金屬基板,具有一第一表面及一第二表面。以 薄膜沈積法形成一内連線層,覆於金屬基板之第一表面。 以積層法形成一積層結構層,覆於内連線層。形成一防焊 層,覆於積層結構層,並暴露出部份之最遠離金屬基板之 積層結構層之導線層。形成一晶片放置開口 ,於金屬基板 之第二表面,以暴露出部份之内連線之介電層,此晶片放 置開口具有一晶片放置區、一點膠區及一抽真空區,其中 點膠區及抽真空區係與晶片放置區相連,並為沿晶片放置 區之對角往外延伸之一對區域。形成多個凸塊開口 ,於暴 露出之内連線之介電層内,以暴露出部份之内連線層之導 線層。貼附一覆晶晶片於晶片放置開口内’此覆晶晶片具 有多個凸塊,使凸塊與凸塊開口所暴露出之該内連線層之 導線層電性連接。進行一填底膠步驟,於晶片放置開口之 點膠區進行點膠,並於抽真空區進行抽真空,以將一底膠 填入凸塊之間的間隙。進行一植球步驟,將多個焊球電性 連接至防焊層所暴露出之部份之最遠離金屬基板之積層結 構層之導線層。 上述各導線層的線路圖案在對應晶片放置開口的邊 緣處係呈波浪狀。 依照本發明的特徵,在晶片放置區的對角延伸有一 對點膠區及抽真空區,因而本發明係在晶片放置區的一隅 進行點膠,而在相對的另一隅進行抽真空,以此方式’可10392twf.ptd Page 7 200427019 V. Description of the invention (3) It belongs to the substrate and at the same time contacts the wire layer in the interconnection layer of the film. The invention further provides a flip-chip ball grid array packaging method, which includes providing a metal substrate with a first surface and a second surface. An interconnecting layer is formed by a thin film deposition method and covers the first surface of the metal substrate. A lamination structure layer is formed by the lamination method, and the interconnection layer is covered. A solder resist layer is formed, covering the laminated structure layer, and exposing a part of the wiring layer of the laminated structure layer farthest from the metal substrate. A wafer placement opening is formed on the second surface of the metal substrate to expose a part of the interconnected dielectric layer. The wafer placement opening has a wafer placement area, a glue area, and a vacuum area. The glue area and the evacuation area are connected to the wafer placement area and are a pair of areas extending outward along the diagonal of the wafer placement area. A plurality of bump openings are formed in the exposed dielectric layer of the interconnect to expose a portion of the interconnect layer of the interconnect layer. Attaching a flip-chip wafer to the wafer placement opening 'This flip-chip wafer has a plurality of bumps, so that the bumps are electrically connected to the conductor layer of the interconnecting layer exposed by the bump openings. A primer filling step is performed. The glue is dispensed in the dispensing area where the wafer is placed, and the vacuum is evacuated to fill a gap between the bumps with a primer. A ball-planting step is performed to electrically connect a plurality of solder balls to the conductive layer of the laminated structure layer farthest from the metal substrate in the exposed portion of the solder mask. The circuit pattern of each of the above-mentioned wire layers is wavy at the edge corresponding to the opening where the wafer is placed. According to the features of the present invention, a pair of dispensing areas and vacuum-extracting areas extend diagonally across the wafer placement area. Therefore, the present invention performs dispensing on one side of the wafer placement area and vacuuming on the opposite side. Way 'may
10392twf.ptd 第8頁 200427019 五、發明說明(4) 縮短填底膠的時間,且可有效防止氣泡發生。 同理如上,因為在晶片放置開口已設置了點膠區及 抽真空區,可將晶片放置區最小化,而提高封裝的可靠 度。 依照本發明的特徵,利用貫孔使積層結構層之最接 近金屬基板的第二導線層接觸金屬基板,並同時接觸薄膜 内連線層的第一導線層,再使金屬基板接地,可得良好的 電流輸送效果。 依照本發明的特徵,各導線層在對應晶片放置開口 的邊緣處係呈波浪狀,在基板形變時,具有緩衝作用,因 而可提高基板之忍受應變的能力。 為讓本發明之上述和其他目的、特徵、和優點能更 明顯易懂,下文特舉一較佳實施例,並配合所附圖式,作 詳細說明如下: [實施方式] 請依序參考第1〜1 1圖,其繪示依照本發明之較佳實 施例的覆晶球格陣列式封裝製程流程剖視圖。 請參考第1圖,提供一金屬基板2 00,具有一第一表 面200a及一第二表面200b。 請參考第2圖,以薄膜沈積法形成一内連線層2 0 2, 覆於金屬基板2 0 0之第一表面2 0 0 a。例如以塗佈的方式形 成一第一介電層2 0 4以及例如利用濺鍍並配合半加成的方 法形成一第一導線層2 0 6。第一介電層2 0 4係覆於金屬基板 200之第一表面200a。第一導線層206係覆於第一介電層10392twf.ptd Page 8 200427019 V. Description of the invention (4) Shorten the time for filling the bottom glue, and can effectively prevent the occurrence of air bubbles. The same as above, because the dispensing area and the vacuum area have been set in the wafer placement opening, the wafer placement area can be minimized, and the reliability of the package can be improved. According to the features of the present invention, a through hole is used to make the second wire layer of the laminated structure layer closest to the metal substrate contact the metal substrate, and at the same time contact the first wire layer of the film interconnect layer, and then ground the metal substrate, which is good. Effect of current delivery. According to the features of the present invention, each wire layer is wavy at the edge corresponding to the opening on which the wafer is placed, and has a buffering effect when the substrate is deformed, thereby improving the substrate's ability to withstand strain. In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is described below in detail with the accompanying drawings as follows: [Embodiment] Please refer to the 1 to 11 are cross-sectional views showing a process flow of a flip-chip ball grid array package according to a preferred embodiment of the present invention. Referring to FIG. 1, a metal substrate 200 is provided, which has a first surface 200a and a second surface 200b. Referring to FIG. 2, a thin film deposition method is used to form an interconnecting layer 2 0 2 and cover the first surface 2 0 a of the metal substrate 2 0 0. For example, a first dielectric layer 204 is formed in a coating manner, and a first wire layer 206 is formed, for example, by a sputtering method and a semi-additive method. The first dielectric layer 204 covers the first surface 200a of the metal substrate 200. The first wire layer 206 is overlying the first dielectric layer
10392twf.ptd 第9頁 200427019 五、發明說明(5) 2 0 4 〇 ♦ 請參考第3〜5圖,以積層(b u i 1 t u p )法形成一積層結 構層2 0 8 (見第5圖),其係以介電層及導線層交替形成,覆 於内連線層202 。如第3圖,形成一圖案化的第二介電層 2 1 0 ,覆於内連線層2 0 2。接著,如第4圖,形成一圖案化 的第二導線層212 ,覆於第二介電層210 。 在形成積層結構2 0 8的途中,為改善晶片的電流輸送 效果,更增列了如下的步驟(見第4圖)。 如第4圖所例示,以雷射鑽孔(第3圖)配合電鍍(第4 圖)的方式,形成一貫孔2 1 8,位於金屬基板2 0 0之晶片放 置開口 2 5 0之晶片放置區2 5 0 a (詳如後述之第1 1圖)之外, 貫穿第一介電層204及與之相鄰之第二介電層210 ,以接觸 最接近金屬基板2 0 0之第二導線層21 2及金屬基板2 0 0,而 同時接觸第一導線層2 0 6。 在此,可使金屬基板2 0 0連接至接地,配合上述貫孔 2 1 8的結構特徵,可形成路徑短且寬廣的接地連線,因而 可大大提升晶片之電流輸送效能。 如第5圖所示,續形成一圖案化的第二介電層2 1 4 , 覆於第二導線層212 ,接著,形成一圖案化的第二導線層 216 ,覆於第二介電層212。 接著,請參考第6圖,形成一防焊層2 2 0,覆於積層 結構層2 0 8 ,此防焊層具有多個開口 2 2 0 a以暴露出部份之 最遠離金屬基板2 00之第二導線層216。於開口220a所暴露 出之第二導層216上形成焊球墊2 22。10392twf.ptd Page 9 200427019 V. Description of the invention (5) 2 0 4 〇 ♦ Please refer to Figures 3 to 5 to form a multilayer structure layer 2 0 8 (see Figure 5) by the bui 1 tup method. It is formed alternately with a dielectric layer and a wire layer, and covers the interconnect layer 202. As shown in FIG. 3, a patterned second dielectric layer 2 1 0 is formed, covering the interconnect layer 2 02. Next, as shown in FIG. 4, a patterned second wiring layer 212 is formed, and is covered on the second dielectric layer 210. In the process of forming the multilayer structure 208, the following steps have been added to improve the current delivery effect of the wafer (see Figure 4). As exemplified in Figure 4, a through hole 2 1 8 is formed by means of laser drilling (Figure 3) and electroplating (Figure 4), and the wafer placement opening 2 500 on the metal substrate 2 500 is placed. Area 2 50 a (see details in FIG. 11 described later), penetrates the first dielectric layer 204 and the adjacent second dielectric layer 210 to contact the second closest to the metal substrate 2 0 0 The wire layer 21 2 and the metal substrate 200 are in contact with the first wire layer 206 at the same time. Here, the metal substrate 200 can be connected to the ground, and in accordance with the structural characteristics of the through-hole 2 18 described above, a short and wide ground connection can be formed, thereby greatly improving the current transmission efficiency of the chip. As shown in FIG. 5, a patterned second dielectric layer 2 1 4 is continuously formed, covering the second wiring layer 212, and then a patterned second wiring layer 216 is formed, covering the second dielectric layer. 212. Next, referring to FIG. 6, a solder resist layer 2 2 0 is formed and covered with the laminated structure layer 2 0 8. This solder resist layer has a plurality of openings 2 2 0 a to expose a part farthest from the metal substrate 2000. Of the second wire layer 216. A solder ball pad 22 is formed on the second guide layer 216 exposed by the opening 220a.
10392twf.ptd 第10頁 200427019 五、發明說明(6) 請參考第7圖,形成一晶片放置開口 2 5 0 ,於金屬基 板200之第二表面200b,以暴露出部份之第一介電層204。 請同時參考第1 1圖,晶片放置開口 2 5 0具有一晶片放置區 2 5 0 a、一點膠區2 5 0 b及一抽真空區2 5 0 c,其中標號2 6 0係 表示此區域中所欲貼附的覆晶晶片(詳如第9圖所示)。晶 片放置開口 2 5 0的形狀為,其中晶片放置區2 5 0 a係呈略大 於覆晶晶片2 6 0的形狀,點膠區2 5 0 a及抽真空區2 5 0 b為與 晶片放置區250a相連’並沿晶片放置區250a之對角往外延 伸之一對區域。 請參考第8圖,形成多個凸塊開口252,於暴露出之 第一介電層内204,以暴露出部份之第一導線層206。形成 凸塊開口的方法,舉例而言,包括雷射鑽孔。 請參考第9圖,貼附一覆晶晶片2 6 0於晶片放置開口 2 5 0中之晶片放置區域2 5 0 a内。覆晶晶片2 6 0具有一主動表 面260a,多個凸塊262形成於主動表面260a上。藉由一回 焊步驟,使凸塊2 6 2與凸塊開口 2 5 2所暴露出之第一導線層 2 0 6電性連接。 接著,進行一填底膠步驟,於晶片放置開口 2 5 0之點 膠區250b進行點膠,並於抽真空區250c進行抽真空,以將 一底膠2 7 0填入凸塊2 6 2之間的間隙。 依本發明之精神可知,並不需限定晶片放置開口 2 5 0 的形狀,其關鍵在於晶片放置區2 5 0 a係接近並略大於覆晶 晶片2 6 0之外形。而點膠區2 5 0 a及抽真空區2 5 0 b係與晶片 放置區2 5 0 a相連,並分別位於晶片放置區2 5 0 a之相對的兩10392twf.ptd Page 10 200427019 V. Description of the invention (6) Please refer to Figure 7 to form a wafer placement opening 2 50 on the second surface 200b of the metal substrate 200 to expose a portion of the first dielectric layer 204. Please refer to FIG. 11 at the same time. The wafer placement opening 2 50 has a wafer placement area 2 5 0 a, a little glue area 2 5 0 b, and a vacuum area 2 5 0 c. The reference numeral 2 6 0 indicates this. The flip chip to be attached in the area (see Figure 9 for details). The shape of the wafer placement opening 2 50 is as follows. The wafer placement area 2 50 a is slightly larger than the flip-chip wafer 2 60. The dispensing area 2 5 0 a and the vacuum area 2 50 0 b are placed on the wafer. Regions 250a are connected 'and extend a pair of regions outwardly along the diagonal of the wafer placement region 250a. Referring to FIG. 8, a plurality of bump openings 252 are formed in the exposed first dielectric layer 204 to expose a portion of the first wire layer 206. Methods of forming bump openings include, for example, laser drilling. Please refer to FIG. 9 and attach a flip-chip wafer 2 60 to a wafer placement area 250 a in the wafer placement opening 250. The flip-chip wafer 260 has an active surface 260a, and a plurality of bumps 262 are formed on the active surface 260a. Through a re-soldering step, the bumps 2 6 2 and the first wire layer 2 0 6 exposed by the bump openings 2 5 2 are electrically connected. Next, a primer filling step is performed, the glue is dispensed in the dispensing area 250b of the opening 250 where the wafer is placed, and the vacuum is evacuated in the evacuation area 250c to fill a bump 2 7 0 into the bump 2 6 2 Gap between. According to the spirit of the present invention, it is not necessary to limit the shape of the wafer placement opening 250. The key is that the wafer placement area 250a is close to and slightly larger than the shape of the flip-chip wafer 260. The dispensing area 2 50 a and the evacuation area 2 5 0 b are connected to the wafer placement area 2 50 0 a and are respectively located opposite to the wafer placement area 2 50 0 a.
10392rwf.ptd 第11頁 200427019 五、發明說明(7) 側,以利於抽真空作業。 接著進行一封膠步驟,以一封膠材料2 9 0填入晶片放 置開口 2 5 0 ,以包覆底膠2 7 0 ,包圍覆晶晶片2 6 0 ,並暴露 出部份之覆晶晶片2 6 0 。 請參考第1 0圖,進行一植球步驟,透過焊球墊2 2 2將 多個焊球2 8 0電性連接至防焊層2 2 0所暴露出之部份之最遠 離金屬基板2 0 0之第二導線層2 1 6,至此以完成覆晶球格陣 列式封裝。 請參考第1 2圖,其繪示各導線層對應於晶片放置開 口周圍處的線路圖案之一例示,圖中係以第一導線層為例 子。在此值得注意的是,在形成上述導線層(2 0 6、2 1 2、 2 1 6 )時,各導線層在對應晶片放置開口 2 5 0的邊緣處(如圖 中虛線2 4 8 )係呈波浪狀的線路圖案。 各導線層在對應晶片放置開口的邊處,形成此波浪 狀線圖案的原因是:依本發明的特徵,在本發明之覆晶球 格陣列式封裝中,在晶片放置開口以外的部份,皆包括了 金屬基板、薄膜内連線層及積層結構層,然而,在晶片放 置開口中,並無金屬基板的部份,所以此封裝結構在對應 晶片放置開口周圍處則成為結構中較弱的部份。 依照本發明之精神,利用在晶片放置開口 2 5 0的邊緣 處2 4 8呈波浪狀拉長的線路圖案,在基板形變(例如受熱膨 脹)時,具有緩衝作用,可不致使導線因形變而被破壞, 因而可提高產品之可靠度。由此可知,本發明亦不需限定 此波浪狀,簡言之如鋸齒狀,或是其他彎摺形狀者皆屬10392rwf.ptd Page 11 200427019 V. Description of the invention (7) side to facilitate vacuuming operation. Then, a glue step is performed, and a wafer material 2 900 is filled into the wafer placement opening 2 50 to cover the bottom glue 2 7 0 to surround the flip-chip wafer 2 600 and a part of the flip-chip wafer is exposed. 2 6 0. Please refer to FIG. 10, and perform a ball-planting step. A plurality of solder balls 2 8 0 are electrically connected to the solder mask 2 2 0 through the solder ball pad 2 2 2 as far away from the metal substrate 2 as possible. 0 0 of the second wire layer 2 1 6, thus completing the flip-chip ball grid array package. Please refer to FIG. 12, which shows an example of a wiring pattern corresponding to the periphery of the chip placement opening of each wire layer. The first wire layer is taken as an example in the figure. It is worth noting here that when forming the above-mentioned wire layer (206, 21, 2, 16), each wire layer is at the edge of the corresponding chip placement opening 2 50 (as shown by the dashed line 2 4 8 in the figure) Wavy line pattern. The reason for forming the wavy line pattern at the side corresponding to the opening where the wafer is placed is as follows: According to the features of the present invention, in the flip-chip ball grid array package of the present invention, the portion outside the wafer placement opening, All include metal substrates, thin-film interconnect layers, and laminated structure layers. However, there is no part of the metal substrate in the wafer placement opening, so this packaging structure becomes weaker in the structure around the corresponding wafer placement opening. Part. According to the spirit of the present invention, the use of a wavy elongated circuit pattern at the edges of the chip placement openings 250 is a buffering effect when the substrate is deformed (such as thermal expansion), so that the wires are not deformed and deformed. Damage, which can increase the reliability of the product. It can be seen that the present invention does not need to be limited to this wave shape, in short, such as a sawtooth shape, or other bent shapes are all
I0392twf.ptd 第12頁 200427019 五、發明說明(8) 之。 由實施例之揭露可知 (1 )·本發明在晶片放置區的 空區,因而本發明係在晶片 相對的另一隅進行抽真空, 間,且可有效防止氣泡發生 (2 ).同理如上,因為在晶片 真空區,可將晶片放置區最 (3 ).本發明利用貫孔使積層 二導線層接觸金屬基板,並 導線層,再使金屬基板接地 流輸送效果。 (4 ).本發明的各導線層在對 狀,在基板形變時,具有緩 受應變的能力,因而提高產 雖然本發明已以較佳 以限定本發明,任何熟習此 神和範圍内,當可作些許之 護範圍當視後附之申請專利 本發明至少具有如下之優點: 對角延伸有一對點膠區及抽真 放置區的一隅進行點膠,而在 以此方式,可縮短填底膠的時 〇 放置開口已設置了點膠區及抽 小化,而提高封裝的可靠度。 結構層之最接近金屬基板之第 同時接觸薄膜内連線層的第一 ,可使覆晶晶片獲得良好的電 應晶片放置開口處係呈波浪 衝作用,因而可提高基板之忍 品之可靠度。 實施例揭露如上,然其並非用 技藝者,在不脫離本發明之精 更動與潤飾,因此本發明之保 範圍所界定者為準。I0392twf.ptd Page 12 200427019 V. Description of Invention (8). It can be known from the disclosure of the embodiment (1) that the present invention is in the empty area of the wafer placement area. Therefore, the present invention is to vacuum the opposite side of the wafer, and can effectively prevent the occurrence of air bubbles (2). The same as above, Because in the wafer vacuum area, the wafer placement area can be maximized (3). The present invention uses through holes to make the laminated two conductor layers contact the metal substrate, and the conductor layer, and then the metal substrate is grounded and conveyed. (4). Each wire layer of the present invention is in the opposite shape, and has the ability to slow the strain when the substrate is deformed, thereby improving the yield. Although the present invention has been better defined to limit the present invention, anyone familiar with this god and scope, when The scope of protection can be a little. When the attached patent is applied, the invention has at least the following advantages: Diagonally extending a pair of dispensing areas and a stack of real placement areas for dispensing, and in this way, the bottom filling can be shortened When the glue is placed, the dispensing area has been set and the size is reduced, which improves the reliability of the package. The structure layer closest to the metal substrate and the first contacting the film interconnect layer at the same time, can make the flip-chip wafer obtain a good electro-response. The placement of the wafer is wave impulse, so the reliability of the substrate can be improved. . The embodiment is disclosed as above, but it is not an artist, and it does not deviate from the refinement and retouching of the present invention. Therefore, what is defined by the scope of the present invention shall prevail.
10392twf.ptd 第13頁 200427019 圖式簡單說明 第1〜1 0圖繪示依照本發明之較佳實施例的一種覆晶 球格陣列封裝製程流程剖視圖; 第1 1圖繪示依照本發明之較佳實施例的晶片放置開 口之一例示的平面圖;以及 第1 2圖繪示依照本發明之較佳實施例的各導線層之 線路圖案之一例示的平面圖。 [圖式標示說明] 2 00 金屬 基板 2 0 2 : 内連線層(薄膜 内連線層) 2 04 第一 介電層 2 0 6 : 第一 導線層 208 積層 結構層 210 ' 214 : 第二介電層 212、 2 16 : 第二: 導線層 218 : 貫孔 f 220 防焊 層 2 2 0a : 開口 222 焊球 墊 2 4 8 : 晶片 放置開口 的邊緣處 250 晶片 放置開 口 2 5 0 a : 晶 片放置區 2 5 0 b : 點膠區 2 5 0 c : 抽真空區 252 :凸塊 開口 2 6 0 : 覆晶 晶片 2 6 0 a : 主動表面 2 6 2 : 凸塊 270 :底膠 2 8 0 : 焊球 2 9 0 : 封膠10392twf.ptd Page 13 200427019 Brief Description of the Drawings Figures 1 to 10 are cross-sectional views of a flip-chip ball grid array packaging process according to a preferred embodiment of the present invention; Figure 11 shows a comparison according to the present invention. An exemplary plan view of a wafer placement opening of the preferred embodiment; and FIG. 12 illustrates an exemplary plan view of a wiring pattern of each wire layer according to a preferred embodiment of the present invention. [Illustration of Graphical Symbol] 2 00 metal substrate 2 0 2: interconnecting layer (thin film interconnecting layer) 2 04 first dielectric layer 2 0 6: first wiring layer 208 laminated structure layer 210 ′ 214: second Dielectric layers 212, 2 16: Second: lead layer 218: through hole f 220 solder mask 2 2 0a: opening 222 solder ball pad 2 4 8: edge of wafer placement opening 250 wafer placement opening 2 5 0 a: Wafer placement area 2 5 0 b: Dispensing area 2 5 0 c: Evacuation area 252: Bump opening 2 6 0: Chip on wafer 2 6 0 a: Active surface 2 6 2: Bump 270: Primer 2 8 0: Solder ball 2 9 0: Sealant
10392twf.ptd 第14頁10392twf.ptd Page 14
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