TWI445141B - 藉由鈍化及聚醯亞胺圍繞之接點及其方法 - Google Patents

藉由鈍化及聚醯亞胺圍繞之接點及其方法 Download PDF

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TWI445141B
TWI445141B TW096111387A TW96111387A TWI445141B TW I445141 B TWI445141 B TW I445141B TW 096111387 A TW096111387 A TW 096111387A TW 96111387 A TW96111387 A TW 96111387A TW I445141 B TWI445141 B TW I445141B
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layer
opening
polyimide
passivation
depositing
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TW096111387A
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TW200746379A (en
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James Jen-Ho Wang
Paul T Hui
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Freescale Semiconductor Inc
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Description

藉由鈍化及聚醯亞胺圍繞之接點及其方法
本發明係關於積體電路，且更特定言之，係關於藉由一鈍化層及一聚醯亞胺層圍繞之接點。
用於高功率積體電路之接合襯墊的接點通常具有鋁界面。鋁用作最後互連層以及使金線接合至鋁接合襯墊之接合襯墊金屬。為獲得較高溫度下之較佳耐久性，金可用於接合襯墊。金接合襯墊類似於用於無需任何導線接合之捲帶式自動接合(TAB)的金凸塊。然而，在諸如高於攝氏125度之連續接面操作溫度之較高溫度下，已存在關於此方法之壽命限制。對於諸如引擎控制之應用，需要承受較高溫度為獲較長壽命。金在較高溫度下將最終擴散入鋁中，此使具有經擴散之金的鋁區域變得脆弱。當此發生時，擴散區可能破裂並引起故障。已建議諸如鈦鎢(TiW)、氮化鈦鎢(TiWN)、鉻及鉑之多個障壁金屬。儘管大體上有效，但所有該等障壁金屬在較高溫度下仍具有有限障壁壽命。
因此，需要互連層與上覆接合襯墊金屬之間的接點，該接點改良耐久性而不負面影響成本或過度增加製程複雜性。
在一態樣中，半導體裝置具有最後互連層與包括接合襯墊與最後互連層之間的障壁金屬之接合襯墊金屬之間的接點。鈍化層及聚醯亞胺層兩者分離最後互連層與接合襯墊。鈍化層經圖案化以形成用以與最後互連層接觸之第一接觸開口。聚醯亞胺層亦經圖案化以留存貫穿鈍化層而位於第一接觸開口內部並因此小於第一接觸開口之第二開口。障壁層接著經沈積而與最後互連層接觸並以聚醯亞胺層為界。接合襯墊金屬接著經形成而與障壁接觸，且接著將導線接合形成至接合襯墊金屬。參看圖式及以下描述而更好地理解此。
在圖1中展示一半導體裝置結構10，其具有一主動電路區12、一接觸區14、主動電路12及接觸區14上之一鋁層16及鋁層16上之一鈍化層18。在此實例中，以簡化形式展示之半導體裝置結構10為需要於其上置放接合襯墊之完成的積體電路。鋁層16為積體電路之最後互連層，且儘管鋁通常較佳，但該最後互連層可為另一材料。儘管如圖1中所展示之鋁層16為連續的，但鋁層16在未圖示之區域中經圖案化以達成其作為互連層之功能。鋁層16在此實例中較佳為約0.6微米但可為另一厚度。
主動電路區12為積體電路之形成電晶體及其他電路元件的部分且包括用於彼等電晶體與其他電路元件之互連。此係通常藉由用以形成電晶體之某些部分之矽基板、用作電晶體元件及互連之一或多個多晶矽層及用以提供必要互連及電源連接之位於一或多個多晶矽層上之互連金屬層來達成。最後互連層(此實例中之鋁層16)為互連層之堆疊中的最高層。亦可存在其他功能。可將靜電放電(ESD)保護電路置放於接觸區中。並非直接位於球狀接合襯墊下之接觸區亦可存在主動電路。鈍化層18較佳為約1.0微米厚之電漿氧化物/氮化物，但可為不同厚度並可由另一適合介電材料製成。因此，接觸區為至最後金屬層之接點經形成用於接合襯墊的區域。
在圖2中展示在用以於接觸區14上留存鈍化層18中之一開口20的鈍化層18之圖案化蝕刻之後的半導體裝置結構10。開口20較佳為約15乘21微米，但可為其他尺寸。
在圖3中展示在藉由固化之前為約8微米厚之聚醯亞胺層22之旋塗的沈積之後的半導體裝置結構10。
在圖4中展示在圖案化聚醯亞胺層22以在開口20內形成一開口24之後的半導體裝置結構10。開口24在鋁層16處較佳為約12乘18微米。開口24具有可為45度之實質斜率。另一方面，開口24可偏離垂線僅10度。開口24在每側與開口20間隔約2微米之聚醯亞胺。
在圖5中展示在聚醯亞胺層22上及開口24中之鋁層16上之一鈦鎢(TiW)層26、TiW層26上之金層28及金層28上之導線接合之沈積之後的半導體裝置結構10。TiW層26較佳為約0.35微米厚。金層28較佳為約9微米厚但可為另一厚度。金層28按照慣例藉由下列步驟而形成：首先濺鍍金晶種金屬之薄層以獲取金/TiW晶種層，及在於金/TiW晶種層上圖案化較厚光阻之後，接著僅在不存在金/TiW晶種層之光阻覆蓋物的位置處電鍍9微米之金。光阻及並非位於電鍍較厚金層下之較薄金/TiW晶種金屬之部分亦經化學剝離；從而留存具有至鋁互連層中之所要點之接點的圖案化且分離之金接合襯墊。金層28大體等形從而大體遵循聚醯亞胺層22之輪廓。由金層28形成之接合襯墊位於金層28及聚醯亞胺層22之平坦部分上且如圖4中所示可位於主動電路區12上。開口24中之金層28及TiW層26因此與鈍化層18之側壁間隔至少一微米之聚醯亞胺。
提供鈍化層18之側壁與金層28之間的間隔之聚醯亞胺已證明形成用於高溫應用之鋁層16與金層28之間的接點之耐久性上的顯著差異。發明人發現當TiW障壁沿著鈍化層之側壁時，金以極大速率在高溫下擴散通過TiW障壁並在此位置處進入鋁。尚不知此位置處之此高速率擴散的根本原因。一理論為當聚醯亞胺經蝕刻以曝露鋁時，存在藉由障壁金屬引起鈍化之更為困難之臺階覆蓋的在鈍化下延伸之鋁的少許底切。另一理論為TiW層並非為3個不同硬質材料三等分處的側壁之轉角之應力點處的非常優良之障壁。本發明之聚醯亞胺之使用的方法可提供鈍化上之某種形式的機械應力釋放。在任何事件中，可藉由用聚醯亞胺將鈍化側壁與TiW分離而大大改良鈍化層之側壁處之不良障壁金屬的問題。本發明之方法的結果為接點的顯著改良之耐久性。
所使用之聚醯亞胺應能夠經圖案化而達到所描述之尺寸且可能甚至更小。為此目的可使用光可成像聚醯亞胺。光可成像聚醯亞胺之另一益處為無需沈積光阻之步驟以圖案化聚醯亞胺。實際上，光可成像聚醯亞胺類似於光阻，而與光阻相比之優點在於其可在圖案化之後經留存用於聚醯亞胺之正常用途。另外，聚醯亞胺應具有較低聚醯胺酸含量，較佳大體無聚醯胺酸。某些聚醯亞胺之聚合產生接著在高濕度環境下充當腐蝕劑之殘餘酸。已發現有效的一此聚醯亞胺由Hitachi－Dupont以商標名稱PI2771銷售。
熟習此項技術者將容易想到對於為說明之目的而在本文中選擇之實施例的各種其他改變及修改。舉例而言，除所揭示之厚度外的其他厚度可為有效的。又，咸信存在關於所使用之材料的特定益處，但其他材料亦可為有效的。所描述之應用用於導線接合，但諸如TAB接合之其他應用亦可為適用的。在不脫離本發明之精神的範圍內，此等修改及變化意欲包括於僅由下列申請專利範圍之清楚詮釋所確定之本發明的範疇內。
10．．．半導體裝置結構
12．．．主動電路區
14．．．接觸區
16．．．鋁層/最後互連層
18．．．鈍化層
20．．．第一開口
22．．．聚醯亞胺層
24．．．第二開口
26．．．TiW層/障壁金屬
28．．．金層/接合襯墊
30．．．導線接合
圖1為根據本發明之一實施例的製程中之一階段處之半導體裝置的橫截面；圖2為在圖1中所展示之階段之後的製程中之一階段處之半導體裝置的橫截面；圖3為在圖2中所展示之階段之後的製程中之一階段處之半導體裝置的橫截面；圖4為在圖3中所展示之階段之後的製程中之一階段處之半導體裝置的橫截面；及圖5為在圖4中所展示之階段之後的製程中之一階段處之半導體裝置的橫截面。
10．．．半導體裝置結構
12．．．主動電路區
14．．．接觸區
16．．．鋁層/最後互連層
18．．．鈍化層
20．．．第一開口
22．．．聚醯亞胺層
24．．．第二開口
26．．．TiW層/障壁金屬
28．．．金層/接合襯墊
30．．．導線接合

Claims (15)

  1. 一種半導體裝置，其包含：一主動電路區；一接觸區；該主動電路區及該接觸區上之一最後互連層；該最後互連層上之一鈍化層，該鈍化層具有一限定為該鈍化層之一側壁的第一開口；該鈍化層上之一具有一第二開口之聚醯亞胺層，該第二開口位於該第一開口內，使得該聚醯亞胺層將該第二開口與該鈍化層之該側壁間隔開，其中該聚醯亞胺層實質上無聚醯胺酸；一障壁金屬層，其位於該聚醯亞胺層上並與該第二開口中之該最後互連層接觸；及該障壁金屬層上之一接合襯墊金屬，其中該鈍化層包含氮化物，該障壁金屬層包含鈦鎢，該接合襯墊金屬包含金，且該最後互連層包含鋁。
  2. 如請求項1之半導體裝置，其中該聚醯亞胺層包含光可成像聚醯亞胺。
  3. 如請求項1之半導體裝置，其中該鈍化層之該側壁與該接合襯墊金屬間隔至少一微米之聚醯亞胺。
  4. 如請求項1之半導體裝置，其進一步包含該主動電路區上之該接合襯墊金屬上的一導線接合。
  5. 如請求項4之半導體裝置，其中該最後互連層包含鋁，該障壁金屬層包含鈦鎢，且該接合襯墊金屬包含金。
  6. 一種製造半導體裝置之方法，其包含：提供一主動電路區；提供一接觸區；在該主動電路區及該接觸區上形成一最後互連層；在該最後互連層上沈積一鈍化層；在該鈍化層中蝕刻一第一開口，其中該第一開口限定為該鈍化層之一側壁；在該鈍化層上沈積一聚醯亞胺層，其中該聚醯亞胺層實質上無聚醯胺酸；在該聚醯亞胺層中蝕刻一第二開口，其中該第二開口位於該第一開口內使得該聚醯亞胺層將該第二開口與該鈍化層之該側壁間隔開；沈積一位於該聚醯亞胺層上並與該第二開口中之該最後互連層接觸之障壁金屬層；在該障壁金屬層上沈積一接合襯墊金屬；及在該主動電路區上之該接合襯墊金屬上形成一導線接合，其中：該沈積該障壁金屬層之步驟的進一步特徵在於該障壁金屬層包含鈦鎢；該沈積該接合襯墊金屬之步驟的進一步特徵在於該接合襯墊金屬包含金，且該沈積最後互連層之步驟的進一步特徵在於該最後互連層包含鋁。
  7. 如請求項6之方法，其中該沈積該聚醯亞胺層之步驟的 進一步特徵在於該聚醯亞胺層包含光可成像聚醯亞胺。
  8. 如請求項7之方法，其中：該沈積該鈍化層之步驟的進一步特徵在於該鈍化層包含氮化物；該沈積該障壁金屬層之步驟的進一步特徵在於該障壁金屬層包含鈦鎢；該沈積該接合襯墊金屬之步驟的進一步特徵在於該接合襯墊金屬包含金，且該沈積最後互連層之步驟的進一步特徵在於該最後互連層包含鋁。
  9. 如請求項6之方法，其中：該沈積該鈍化層之步驟的進一步特徵在於該鈍化層包含氮化物；該沈積該障壁金屬層之步驟的進一步特徵在於該障壁金屬層包含鈦鎢；該沈積該接合襯墊金屬之步驟的進一步特徵在於該接合襯墊金屬包含金，且該沈積最後互連層之步驟的進一步特徵在於該最後互連層包含鋁。
  10. 如請求項6之方法，其中該蝕刻該聚醯亞胺層之步驟的進一步特徵在於以自該鈍化層之該側壁所量測而留存至少一微米之一厚度的聚醯亞胺。
  11. 一種半導體裝置，其包含：一主動電路區； 一接觸區；該主動電路區及該接觸區上之一包含鋁的最後互連層；該最後互連層上之一鈍化層，該鈍化層具有一限定為該鈍化層之一側壁的第一開口；該鈍化層上之一具有一第二開口之聚醯亞胺層，該第二開口位於該第一開口內使得該聚醯亞胺層將該第二開口與該鈍化層之該側壁間隔開，其中該聚醯亞胺層實質上無聚醯胺酸；一包含鈦鎢之障壁金屬層，其位於該聚醯亞胺層上並與該第二開口中之該最後互連層接觸；及該障壁金屬層上之一包含金的接合襯墊金屬。
  12. 如請求項11之半導體裝置，其中該聚醯亞胺層包含光可成像聚醯亞胺。
  13. 如請求項12之半導體裝置，其中該鈍化層包含氮化物。
  14. 如請求項13之半導體裝置，其中該鈍化層之該側壁與該接合襯墊金屬間隔至少一微米之聚醯亞胺。
  15. 如請求項14之半導體裝置，其進一步包含該主動電路區上之該接合襯墊金屬上的一導線接合。
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US7615866B2 (en) 2009-11-10
CN101449376B (zh) 2011-04-20
KR20090009890A (ko) 2009-01-23
CN101449376A (zh) 2009-06-03
WO2007140049A3 (en) 2008-07-24
US20070275549A1 (en) 2007-11-29
WO2007140049A2 (en) 2007-12-06
JP2009538537A (ja) 2009-11-05
US20100015793A1 (en) 2010-01-21

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