TWI442534B - 晶片轉接板 - Google Patents

晶片轉接板 Download PDF

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Publication number
TWI442534B
TWI442534B TW099111271A TW99111271A TWI442534B TW I442534 B TWI442534 B TW I442534B TW 099111271 A TW099111271 A TW 099111271A TW 99111271 A TW99111271 A TW 99111271A TW I442534 B TWI442534 B TW I442534B
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Taiwan
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wafer
pads
circuit board
size
mounting area
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TW099111271A
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TW201135892A (en
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Ming Chih Hsieh
Heng Chen Kuo
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Hon Hai Prec Ind Co Ltd
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Priority to TW099111271A priority Critical patent/TWI442534B/zh
Priority to US12/770,768 priority patent/US8199519B2/en
Publication of TW201135892A publication Critical patent/TW201135892A/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/12—Mountings, e.g. non-detachable insulating substrates
    • H01L23/13—Mountings, e.g. non-detachable insulating substrates characterised by the shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49126—Assembling bases
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
    • Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49149—Assembling terminal to base by metal fusion bonding
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49147—Assembling terminal to base
    • Y10T29/49151—Assembling terminal to base by deforming or shaping
    • Y10T29/49153—Assembling terminal to base by deforming or shaping with shaping or forcing terminal into base aperture

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Combinations Of Printed Boards (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Description

晶片轉接板
本發明係關於一種轉接板，尤指一種用於轉接晶片的轉接板。
目前，電路板上都會安裝有各種各樣的晶片，但由於某種原因(如首次使用新的晶片或設計失誤)可能會造成電路板上用於安裝晶片的晶片安裝區域的尺寸與晶片不匹配，使晶片無法安裝在電路板上，如此，需重新進行電路板的佈線設計，且原來生產的電路板無法使用，大大提高了成本。
鑒於上述內容，有必要提供一種轉接板，以將晶片安裝在佈線與晶片不匹配的電路板上。
一種晶片轉接板，用於將一晶片安裝在一電路板的一第一晶片安裝區域上，且該晶片的本體的尺寸小於該第一晶片安裝區域的尺寸，該晶片轉接板為一尺寸與該第一晶片安裝區域相匹配的板體，該板體的四周設有複數與該第一晶片安裝區域上的第一焊盤一一對應的凹口，中心設有一與該晶片的本體的尺寸匹配的第二晶片安裝區域，該第二晶片安裝區域的四週設有複數用於對應焊接該晶片上引腳的第二焊盤，該等第二焊盤與該等凹口的側壁一一對應電性連接。
相較習知技術，本發明晶片轉接板透過在其上設置與該晶片的本體的尺寸匹配的第二晶片安裝區域以將晶片安裝在該第二晶片安裝區域，再將該晶片轉接板安裝在該電路板的第一晶片安裝區域，進而實現了電路板與晶片之間的連接，故無須對電路板的佈線進行重新設計，大大降低了設計成本，節約了時間，提高了效率。
請參考圖1至圖3，本發明晶片轉接板的第一較佳實施方式200用於將一晶片300安裝在一電路板100的一晶片安裝區域10上，且該晶片300的本體30與該晶片安裝區域10的尺寸不匹配。其中，該晶片安裝區域10的四週設有複數對應該晶片300上引腳32的焊盤12，該晶片轉接板200為一尺寸與該晶片安裝區域10相匹配的電路板板體，其四周設有複數與該晶片安裝區域10上的焊盤12一一對應的半圓型凹口26，每兩相鄰的凹口26之間非電連接，每一凹口26的側壁用製作印刷電路板上導通孔的方式製作。該晶片轉接板200中心設有一與該晶片300的本體30的尺寸匹配的晶片安裝區域20。該晶片安裝區域20的四週設有複數用於對應焊接該晶片300上引腳32的焊盤22，該等焊盤22與該等凹口26的側壁一一對應電性連接，如透過電路板上佈設的銅箔24電性連接。
請繼續參考圖4，當需要將該晶片300安裝在該電路板100的晶片安裝區域10上時，首先，將該晶片轉接板200對應放置在該晶片安裝區域10上，此時該等凹口26與該等焊盤12一一對應，在該等凹口26處熔入焊錫以將該等焊盤12與該等銅箔24一一電性焊接起來，由於該晶片轉接板200的四週設計了該等凹口26，故在熔錫時容易吃錫（因為設計成凹口結構可增大熔錫面積），使焊接牢固。然後，將該晶片300放在該晶片轉接板200的晶片安裝區域20上，並對應將該晶片300的引腳32焊接在該晶片轉接板200的焊盤22上。如此，該晶片300的引腳32便透過該晶片轉接板200與該電路板100上的焊盤12對應電性連接上了，該晶片300即可配合電路板100上的其他元件（未示出）進行後續工作了。由於該電路板100應用了該晶片轉接板200對晶片300進行轉接，故無須對電路板100的佈線進行重新設計，大大降低了設計成本，節約了時間，提高了效率。該晶片轉接板的第一較佳實施方式200用於將晶片300安裝在設計過大的晶片安裝區域10上。
請參考圖5至圖7，本發明晶片轉接板的第二較佳實施方式500用於將一晶片600安裝在一電路板400的一晶片安裝區域40上，且該晶片600的本體60與該晶片安裝區域40的尺寸不匹配。其中，該晶片安裝區域40的四週設有複數對應該晶片600上引腳62的焊盤42，該晶片轉接板500為一尺寸與該晶片600的本體60相匹配的電路板板體，其四周設有複數與該晶片600的引腳62一一對應的焊盤52，中心設有一與該晶片安裝區域40的尺寸匹配的開口520。該晶片轉接板500的板体上沿該開口520的四週設有複數對應該晶片安裝區域40的焊盤42的半圓型凹口56，每兩個相鄰的凹口56之間非電連接，每一凹口56的側壁用製作印刷電路板上導通孔的方式製作，該等焊盤52與該等凹口56的側壁一一對應電性連接，如透過電路板上佈設的銅箔54電性連接。
請繼續參考圖8，當需要將該晶片600安裝在該電路板400的晶片安裝區域40上時，首先，將該晶片轉接板500放置在該電路板400上，使開口520與該晶片安裝區域40正對，此時該等凹口56與該等焊盤42一一對應，在該等凹口56處熔入焊錫以將該等焊盤42與該等銅箔54一一電性焊接起來，由於該晶片轉接板200的開口520週緣設計了該等凹口56，故在熔錫時容易吃錫，使焊接牢固。然後，將該晶片600放在該晶片轉接板500上，並對應將該晶片600的引腳62焊接在該晶片轉接板500的焊盤52上。如此，該晶片600的引腳62便透過該晶片轉接板500與該電路板400上的焊盤42對應電性連接上了，該晶片600即可配合電路板400上的其他元件（未示出）進行後續工作了。該晶片轉接板的第二較佳實施方式500用於將晶片600安裝在設計過小的晶片安裝區域40上。
綜上所述，本發明符合發明專利要件，爰依法提出專利申請。惟，以上所述者僅為本發明之較佳實施例，舉凡熟悉本案技藝之人士，在爰依本發明精神所作之等效修飾或變化，皆應涵蓋於以下之申請專利範圍內。
100、400‧‧‧電路板
12、42、22、52‧‧‧焊盤
10、40、20‧‧‧晶片安裝區域
200、500‧‧‧晶片轉接板
24、54‧‧‧銅箔
26、56‧‧‧凹口
300、600‧‧‧晶片
30、60‧‧‧本體
32、62‧‧‧引腳
520‧‧‧開口
圖1係一電路板的局部示意圖。
圖2係本發明晶片轉接板的第一較佳實施方式的示意圖。
圖3係一晶片的示意圖。
圖4係圖3晶片透過圖2晶片轉接板安裝在圖1電路板上的示意圖。
圖5係一電路板的局部示意圖。
圖6係本發明晶片轉接板的第二較佳實施方式的示意圖。
圖7係一晶片的示意圖。
圖8係圖7晶片透過圖6晶片轉接板安裝在圖5電路板上的示意圖。
200‧‧‧晶片轉接板
20‧‧‧晶片安裝區域
22‧‧‧焊盤
24‧‧‧銅箔
26‧‧‧凹口

Claims (8)

  1. 一種晶片轉接板，用於將一晶片安裝在一電路板的一第一晶片安裝區域上，且該晶片的本體的尺寸小於該第一晶片安裝區域的尺寸，該晶片轉接板為一尺寸與該第一晶片安裝區域相匹配的板體，該板體的四周設有複數與該第一晶片安裝區域上的第一焊盤一一對應的凹口，中心設有一與該晶片的本體的尺寸匹配的第二晶片安裝區域，該第二晶片安裝區域的四週設有複數用於對應焊接該晶片上引腳的第二焊盤，該等第二焊盤與該等凹口的側壁一一對應電性連接。
  2. 如申請專利範圍第1項所述之晶片轉接板，其中該等第二焊盤與對應凹口之間是透過銅箔實現電性連接的。
  3. 如申請專利範圍第1項所述之晶片轉接板，其中該等凹口為半圓形。
  4. 如申請專利範圍第1項所述之晶片轉接板，其中每兩相鄰的凹口之間非電連接，每一凹口的側壁係用製作印刷電路板上導通孔的方式製作的。
  5. 一種晶片轉接板，用於將一晶片安裝在一電路板的一晶片安裝區域上，且該晶片的本體的尺寸大於該晶片安裝區域的尺寸，該晶片轉接板為一尺寸與該晶片的本體相匹配的板體，該板體的四周設有複數與該晶片的引腳一一對應的第一焊盤，中心設有一與該晶片安裝區的尺寸匹配的開口，該板體上延該開口的四週設有複數對應該晶片安裝區域的第二焊盤的凹口，該等第一焊盤與該等凹口的側壁一一對應電性連接。
  6. 如申請專利範圍第5項所述之晶片轉接板，其中該等第一焊盤與對應凹口之間是透過銅箔實現電性連接的。
  7. 如申請專利範圍第5項所述之晶片轉接板，其中該等凹口為半圓形。
  8. 如申請專利範圍第5項所述之晶片轉接板，其中每兩相鄰的凹口之間非電連接，每一凹口的側壁係用製作印刷電路板上導通孔的方式製作的。
TW099111271A 2010-04-12 2010-04-12 晶片轉接板 TWI442534B (zh)

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Application Number Priority Date Filing Date Title
TW099111271A TWI442534B (zh) 2010-04-12 2010-04-12 晶片轉接板
US12/770,768 US8199519B2 (en) 2010-04-12 2010-04-30 Chip adapter

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TW099111271A TWI442534B (zh) 2010-04-12 2010-04-12 晶片轉接板

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