TWI434512B - 用於電流模式邏輯緩衝器之共同模式移位電路 - Google Patents

用於電流模式邏輯緩衝器之共同模式移位電路 Download PDF

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Publication number
TWI434512B
TWI434512B TW094124993A TW94124993A TWI434512B TW I434512 B TWI434512 B TW I434512B TW 094124993 A TW094124993 A TW 094124993A TW 94124993 A TW94124993 A TW 94124993A TW I434512 B TWI434512 B TW I434512B
Authority
TW
Taiwan
Prior art keywords
current
circuit
output
voltage
current mode
Prior art date
Application number
TW094124993A
Other languages
English (en)
Chinese (zh)
Other versions
TW200629726A (en
Inventor
Kamran Azadet
Fu Ji Yang
Ghun Bing Guo
Original Assignee
Agere Systems Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Inc filed Critical Agere Systems Inc
Publication of TW200629726A publication Critical patent/TW200629726A/zh
Application granted granted Critical
Publication of TWI434512B publication Critical patent/TWI434512B/zh

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Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0282—Provision for current-mode coupling
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09432—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors with coupled sources or source coupled logic
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission
    • H04L25/0274—Arrangements for ensuring balanced coupling

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
TW094124993A 2004-07-23 2005-07-22 用於電流模式邏輯緩衝器之共同模式移位電路 TWI434512B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US59062404P 2004-07-23 2004-07-23
US11/141,337 US7355451B2 (en) 2004-07-23 2005-05-31 Common-mode shifting circuit for CML buffers

Publications (2)

Publication Number Publication Date
TW200629726A TW200629726A (en) 2006-08-16
TWI434512B true TWI434512B (zh) 2014-04-11

Family

ID=35656470

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094124993A TWI434512B (zh) 2004-07-23 2005-07-22 用於電流模式邏輯緩衝器之共同模式移位電路

Country Status (4)

Country Link
US (1) US7355451B2 (enExample)
JP (1) JP2006042349A (enExample)
KR (1) KR101121460B1 (enExample)
TW (1) TWI434512B (enExample)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3874733B2 (ja) * 2003-02-28 2007-01-31 富士通株式会社 高速入力信号の受信回路
US20080061837A1 (en) * 2006-08-25 2008-03-13 Parade Technologies, Ltd. Low Supply Voltage, Large Output Swing, Source-Terminated Output Driver for High Speed AC-coupled Double-Termination Serial Links
US7579881B2 (en) * 2007-11-14 2009-08-25 Infineon Technologies Ag Write driver circuit
JP5238604B2 (ja) * 2009-05-20 2013-07-17 株式会社東芝 電圧変換回路および無線通信装置
KR20130026218A (ko) * 2011-09-05 2013-03-13 삼성전기주식회사 홀 플레이트 스위칭 시스템
KR102073367B1 (ko) 2014-07-07 2020-02-05 한국전자통신연구원 버퍼 증폭기 및 버퍼 증폭기를 포함하는 트랜스 임피던스 증폭기
US9614530B2 (en) * 2014-12-12 2017-04-04 Samsung Display Co., Ltd. Fast fall and rise time current mode logic buffer
JP6399938B2 (ja) 2015-01-22 2018-10-03 株式会社メガチップス 差動出力バッファ
US9225332B1 (en) * 2015-04-08 2015-12-29 Xilinx, Inc. Adjustable buffer circuit
US10712769B2 (en) 2017-08-16 2020-07-14 Oracle International Corporation Method and apparatus for clock signal distribution

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4806796A (en) * 1988-03-28 1989-02-21 Motorola, Inc. Active load for emitter coupled logic gate
US4868423A (en) * 1988-05-02 1989-09-19 Motorola, Inc. Current mode logic gate
JPH05226950A (ja) * 1992-02-14 1993-09-03 Asahi Kasei Micro Syst Kk 全差動増幅器
US5309039A (en) * 1992-09-29 1994-05-03 Motorola, Inc. Power supply dependent input buffer
JPH08288761A (ja) * 1995-04-10 1996-11-01 Fujitsu Ltd 差動増幅＆出力オフセット回路及びこれを備えた半導体集積回路並びにノイズ除去方法
US5909127A (en) 1995-12-22 1999-06-01 International Business Machines Corporation Circuits with dynamically biased active loads
GB9707349D0 (en) 1997-04-11 1997-05-28 Univ Waterloo A dynamic current mode logic family
US5856757A (en) * 1997-06-11 1999-01-05 Philips Electronics North America Corporation gm-C cell with two stage common mode control and current boost
US5977800A (en) 1997-10-20 1999-11-02 Vlsi Technology, Inc. Differential MOS current-mode logic circuit having high gain and fast speed
US6366140B1 (en) 1999-07-01 2002-04-02 Vitesse Semiconductor Corporation High bandwidth clock buffer
JP2001339259A (ja) * 2000-05-30 2001-12-07 Oki Electric Ind Co Ltd 差動増幅回路及び半導体集積回路装置
TW518642B (en) * 2000-06-27 2003-01-21 Semiconductor Energy Lab Level shifter
US6353338B1 (en) 2000-09-28 2002-03-05 Lsi Logic Corporation Reduced-swing differential output buffer with idle function
US6677784B2 (en) 2000-12-28 2004-01-13 International Business Machines Corporation Low voltage bipolar logic and gate device
JP3714223B2 (ja) * 2001-10-16 2005-11-09 株式会社デンソー 増幅回路および波形整形回路
US6762624B2 (en) 2002-09-03 2004-07-13 Agilent Technologies, Inc. Current mode logic family with bias current compensation

Also Published As

Publication number Publication date
TW200629726A (en) 2006-08-16
US7355451B2 (en) 2008-04-08
US20060017468A1 (en) 2006-01-26
KR101121460B1 (ko) 2012-03-15
JP2006042349A (ja) 2006-02-09
KR20060092833A (ko) 2006-08-23

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MM4A Annulment or lapse of patent due to non-payment of fees