TWI434383B - Bonding pad structure and integrated cicruit comprise a pluirality of bonding pad structures - Google Patents

Bonding pad structure and integrated cicruit comprise a pluirality of bonding pad structures Download PDF

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Publication number
TWI434383B
TWI434383B TW099143454A TW99143454A TWI434383B TW I434383 B TWI434383 B TW I434383B TW 099143454 A TW099143454 A TW 099143454A TW 99143454 A TW99143454 A TW 99143454A TW I434383 B TWI434383 B TW I434383B
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Taiwan
Prior art keywords
connection pad
electrical connection
insulating layer
integrated circuit
opening
Prior art date
Application number
TW099143454A
Other languages
Chinese (zh)
Other versions
TW201225231A (en
Inventor
Yu Ju Yang
Chih Hung Lu
Original Assignee
Ili Technology Corp
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Publication date
Application filed by Ili Technology Corp filed Critical Ili Technology Corp
Priority to TW099143454A priority Critical patent/TWI434383B/en
Priority to US12/983,895 priority patent/US20120146215A1/en
Priority to CN201110009080.3A priority patent/CN102543894B/en
Publication of TW201225231A publication Critical patent/TW201225231A/en
Priority to US13/565,785 priority patent/US20120299180A1/en
Priority to US13/565,759 priority patent/US20120292761A1/en
Application granted granted Critical
Publication of TWI434383B publication Critical patent/TWI434383B/en

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    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/0132—Binary Alloys
    • H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides

Description

電性連接墊結構及包含有複數個電性連接墊結構的積體電路Electrical connection pad structure and integrated circuit including a plurality of electrical connection pad structures

本發明係有關於一種電性連接墊結構，尤指一種設置於一積體電路上且應用於玻璃覆晶(Chip on Glass,COG)以及薄膜覆晶(Chip on Film,COF)封裝中的一種電性連接墊結構。The invention relates to an electrical connection pad structure, in particular to a chip disposed on an integrated circuit and applied to a chip on glass (COG) and a chip on film (COF) package. Electrical connection pad structure.

請參考第1圖，第1圖為一玻璃覆晶結構100的示意圖。如第1圖所示，玻璃覆晶結構100包含有一驅動積體電路110、一異向性導電膜(Anisotropic Conductive Film,ACF)120以及一玻璃基板130，其中驅動積體電路110包含有複數個電性連接墊結構112，異向性導電膜120是由黏合劑122及導電粒子124所組成，且玻璃基板130上具有與複數個電性連接墊結構112相對應的複數個電極132。Please refer to FIG. 1 , which is a schematic diagram of a glass flip chip structure 100 . As shown in FIG. 1 , the glass flip chip structure 100 includes a driving integrated circuit 110 , an anisotropic conductive film (ACF) 120 and a glass substrate 130 , wherein the driving integrated circuit 110 includes a plurality of The electrical connection pad structure 112, the anisotropic conductive film 120 is composed of the adhesive 122 and the conductive particles 124, and the glass substrate 130 has a plurality of electrodes 132 corresponding to the plurality of electrical connection pads 112.

在玻璃覆晶結構壓接的過程中，首先，將異向性導電膜120貼覆於玻璃基板130上，接著，將驅動積體電路110上的電性連接墊結構112與玻璃基板130上的電極132對齊，之後在一定的溫度、速度與壓力條件下，將驅動積體電路110與玻璃基板130壓合，以使得驅動積體電路110上的電性連接墊結構112可以藉由異向性導電膜120中的導電粒子124與玻璃基板130上的電極132電性連接，並藉由黏合劑122將積體電路110與玻璃基板130黏合。壓合後的玻璃覆晶結構可參見第2圖，因為玻璃覆晶結構的製作過程係為本發明領域中具有通常知識者所習知，故相關細節在此不再贅述。In the process of crimping the glass flip-chip structure, first, the anisotropic conductive film 120 is pasted on the glass substrate 130, and then the electrical connection pad structure 112 on the integrated circuit 110 and the glass substrate 130 are driven. The electrodes 132 are aligned, and then the driving integrated circuit 110 is pressed against the glass substrate 130 under a certain temperature, speed and pressure condition, so that the electrical connection pad structure 112 on the driving integrated circuit 110 can be anisotropic. The conductive particles 124 in the conductive film 120 are electrically connected to the electrodes 132 on the glass substrate 130, and the integrated circuit 110 and the glass substrate 130 are bonded by the adhesive 122. The embossed glass flip-chip structure can be seen in Fig. 2, because the fabrication process of the glass flip-chip structure is well known to those of ordinary skill in the art, and the details are not described herein again.

此外，因為目前液晶顯示器的解析度越來越高，因此，驅動積體電路110的接腳數目也越來越多，亦即電性連接墊結構112的數量會增加，且電性連接墊結構112之間的間距也會越來越小。為了因應電性連接墊結構112之間的間距縮小的問題，異向性導電膜120會採用尺寸比較小的導電粒子124(大小約為3~4um)以避免電性連接墊結構112之間的短路。In addition, since the resolution of the liquid crystal display is higher and higher, the number of pins of the driving integrated circuit 110 is also increasing, that is, the number of the electrical connection pad structures 112 is increased, and the electrical connection pad structure is increased. The spacing between 112 will also be smaller and smaller. In order to cope with the problem of narrowing the spacing between the electrical connection pad structures 112, the anisotropic conductive film 120 uses relatively small-sized conductive particles 124 (about 3 to 4 um in size) to avoid electrical connection between the pad structures 112. Short circuit.

接著，請參考第3圖，第3圖為第1、2圖所示之電性連接墊結構112的剖面圖。如第3圖所示，連接墊結構112包含有一連接墊302、製作於連接墊302上的絕緣層304、以及製作於連接墊302及絕緣層304上的金凸塊306。然而，因為金凸塊306係形成於連接墊302及絕緣層304上，因此在金凸塊306的表面將會形成一下凹區域，如此一來，若是導電粒子124的尺寸太小，則會使得將積體電路110的電性連接墊結構112與玻璃基板130的電極132在壓合時無法確實壓破足夠的導電粒子，而影響到其電性連接效果。Next, please refer to FIG. 3, which is a cross-sectional view of the electrical connection pad structure 112 shown in FIGS. As shown in FIG. 3, the connection pad structure 112 includes a connection pad 302, an insulating layer 304 formed on the connection pad 302, and gold bumps 306 formed on the connection pad 302 and the insulating layer 304. However, since the gold bumps 306 are formed on the connection pads 302 and the insulating layer 304, a recessed region will be formed on the surface of the gold bumps 306, so that if the size of the conductive particles 124 is too small, When the electrical connection pad structure 112 of the integrated circuit 110 and the electrode 132 of the glass substrate 130 are pressed together, it is not possible to reliably crush enough conductive particles, thereby affecting the electrical connection effect.

因此，本發明的目的之一在於提供一種電性連接墊結構，其中的金凸塊具有較為平坦的表面，以使得與玻璃基板上的電極壓合後具有良好的電性連接效果。Accordingly, it is an object of the present invention to provide an electrical connection pad structure in which the gold bumps have a relatively flat surface so as to have a good electrical connection effect after being pressed against the electrodes on the glass substrate.

依據本發明一實施例，一種設置於一積體電路上的電性連接墊結構包含有一連接墊、一絕緣層以及一金凸塊，其中該連接墊設置於該積體電路上；該絕緣層設置於該連接墊上方，其中該絕緣層僅具有一開口部，且該開口部的形狀包含有至少一條狀彎折處；該金凸塊設置於該絕緣層上方，其中該金凸塊可以透過該絕緣層之該開口部與該連接墊電性連接。According to an embodiment of the present invention, an electrical connection pad structure disposed on an integrated circuit includes a connection pad, an insulating layer, and a gold bump, wherein the connection pad is disposed on the integrated circuit; the insulating layer Provided above the connection pad, wherein the insulating layer has only one opening portion, and the shape of the opening portion includes at least one bent portion; the gold bump is disposed above the insulating layer, wherein the gold bump is transparent The opening of the insulating layer is electrically connected to the connection pad.

依據本發明另一實施例，一種積體電路，包含有複數個電性連接墊結構，其中該複數個電性連接墊結構中每一個電性連接墊結構包含有一連接墊、一絕緣層以及一金凸塊，其中該連接墊設置於該積體電路上；該絕緣層設置於該連接墊上方，其中該絕緣層僅具有一開口部，且該開口部的形狀包含有至少一條狀彎折處；該金凸塊設置於該絕緣層上方，其中該金凸塊可以透過該絕緣層之該開口部與該連接墊電性連接。According to another embodiment of the present invention, an integrated circuit includes a plurality of electrical connection pad structures, wherein each of the plurality of electrical connection pad structures includes a connection pad, an insulation layer, and a a gold bump, wherein the connection pad is disposed on the integrated circuit; the insulating layer is disposed above the connection pad, wherein the insulation layer has only one opening portion, and the shape of the opening portion includes at least one bent portion The gold bump is disposed above the insulating layer, wherein the gold bump can be electrically connected to the connection pad through the opening portion of the insulating layer.

請參考第4圖，第4圖為依據本發明一實施例之一玻璃覆晶結構400的示意圖。參考第4圖，玻璃覆晶結構400包含有一驅動積體電路410、一異向性導電膜420以及一玻璃基板430，其中驅動積體電路410包含有複數個電性連接墊結構412，異向性導電膜420是由黏合劑422及導電粒子424所組成，且玻璃基板430上具有與複數個電性連接墊結構412相對應的複數個電極432，其中驅動積體電路410上的電性連接墊結構412可以藉由異向性導電膜420中的導電粒子424與玻璃基板430上的電極432電性連接，且驅動積體電路410藉由黏合劑422與玻璃基板430黏合。Please refer to FIG. 4, which is a schematic diagram of a glass flip-chip structure 400 according to an embodiment of the invention. Referring to FIG. 4, the glass flip-chip structure 400 includes a driving integrated circuit 410, an anisotropic conductive film 420, and a glass substrate 430. The driving integrated circuit 410 includes a plurality of electrical connection pads 412, which are opposite to each other. The conductive film 420 is composed of a binder 422 and conductive particles 424, and the glass substrate 430 has a plurality of electrodes 432 corresponding to the plurality of electrical connection pads 412, wherein the electrical connection on the integrated circuit 410 is driven. The pad structure 412 can be electrically connected to the electrode 432 on the glass substrate 430 by the conductive particles 424 in the anisotropic conductive film 420, and the driving integrated circuit 410 is bonded to the glass substrate 430 by the adhesive 422.

接著，請參考第5圖，第5圖為依據本發明一實施例之電性連接墊結構412的示意圖。如第5圖所示，電性連接墊結構412包含有一連接墊502、製作於連接墊502上的絕緣層504、以及製作於連接墊502及絕緣層504上的金凸塊506，其中絕緣層504僅具有一開口部，且該開口部的形狀包含有至少一條狀彎折處。舉例來說，請參考第6、7、8圖，絕緣層504之開口部602、702、802的形狀可分別為一“口”字型、一“弓”字型以及一魚骨型，而金凸塊506直接製作於絕緣層504及開口部602、702、802的上方，以使得金凸塊506可以透過絕緣層504之開口部602、702、802與連接墊502電性連接。Next, please refer to FIG. 5. FIG. 5 is a schematic diagram of an electrical connection pad structure 412 according to an embodiment of the invention. As shown in FIG. 5, the electrical connection pad structure 412 includes a connection pad 502, an insulating layer 504 formed on the connection pad 502, and gold bumps 506 formed on the connection pad 502 and the insulating layer 504, wherein the insulating layer The 504 has only one opening, and the shape of the opening includes at least one bent portion. For example, referring to Figures 6, 7, and 8, the openings 602, 702, and 802 of the insulating layer 504 may have a shape of a "mouth", a "bow", and a fishbone, respectively. The gold bumps 506 are directly formed on the insulating layer 504 and the openings 602, 702, and 802, so that the gold bumps 506 can be electrically connected to the connection pads 502 through the openings 602, 702, and 802 of the insulating layer 504.

此外，雖然第6、7、8圖僅描繪出開口部為“口”字型、“弓”字型及魚骨型，然而，本發明並不以此為限，於本發明之其他實施例中，絕緣層504之開口部的形狀可以為“口”字型、“弓”字型及魚骨型的任意組合(例如開口部同時包含“口”字型及魚骨型)或是其簡單變化(例如ㄇ字型或是反“弓”字型)，換句話說，只要開口部的形狀包含有至少一條狀彎折處，這些設計上的變化均應隸屬於本發明的範疇。此外，本發明所指之條狀彎折並非一定如第6、7、8圖所示之直角彎折，亦可以為非直角彎折或是弧形彎折。In addition, although the sixth, seventh, and eighth figures only depict the opening portion as a "mouth" type, a "bow" type, and a fishbone type, the present invention is not limited thereto, and other embodiments of the present invention. The shape of the opening of the insulating layer 504 may be any combination of a "mouth" shape, a "bow" shape, and a fishbone type (for example, the opening portion includes both a "mouth" type and a fishbone type) or is simple. Variations (e.g., ㄇ-shaped or inverted "bow"), in other words, as long as the shape of the opening contains at least one bend, these design variations are subject to the scope of the present invention. In addition, the strip bending referred to in the present invention is not necessarily a right angle bend as shown in Figs. 6, 7, and 8, and may be a non-right angle bend or a curved bend.

此外，金凸塊506的材料可以同時包含有銅、鎳、金三層金屬層，也可以僅包含銅、鎳、金三種金屬中一或兩種金屬層，或是錫鉛合金，並以電鍍的方式形成於絕緣層之上。In addition, the material of the gold bump 506 may include three layers of copper, nickel, and gold, or may include only one or two metal layers of copper, nickel, and gold, or tin-lead alloy, and be plated. The way is formed on the insulating layer.

本發明之絕緣層504的開口部形狀包含有至少一條狀彎折處，因此，以第6、7、8圖所示之實施例來說明，開口部條狀彎折的形狀可以使得金凸塊506的凹陷幅度大幅減少，以同樣面積的金凸塊來說，若是採用第3圖所示之習知電性連接墊結構的金凸塊下陷幅度為2um，則採用本發明之電性連接墊結構的金凸塊下陷幅度會小於1um，如此一來，金凸塊的表面將會較為平整，在進行玻璃覆晶結構壓合時也可以有效地壓破足夠的導電粒子424，而使得電性連接墊結構412與電極432具有良好的電性連接效果。The shape of the opening of the insulating layer 504 of the present invention includes at least one bent portion. Therefore, as illustrated in the embodiments shown in FIGS. 6, 7, and 8, the strip-shaped bent shape of the opening can make the gold bump The fading width of the 506 is greatly reduced. In the case of the gold bump of the same area, if the gold bump sag of the conventional electrical connection pad structure shown in FIG. 3 is 2 um, the electrical connection pad of the present invention is used. The gold bump of the structure will be less than 1um, so that the surface of the gold bump will be relatively flat, and the conductive particles 424 can be effectively crushed when the glass flip-chip structure is pressed, so that the electrical property is made. The connection pad structure 412 has a good electrical connection effect with the electrode 432.

因為本發明之電性連接墊結構412的金凸塊下陷幅度很小，故異向性導電膜420可以在維持良好導電性的情形下使用尺寸更小的導電粒子424，故電性連接墊結構412之間的間距便可以進一步的縮小以增加驅動積體電路410的金凸塊密度。Because the gold bump of the electrical connection pad structure 412 of the present invention has a small amplitude of sag, the anisotropic conductive film 420 can use the conductive particles 424 having a smaller size while maintaining good conductivity, so the electrical connection pad structure The spacing between 412 can be further reduced to increase the gold bump density of the drive integrated circuit 410.

此外，以上所揭露的內容均以玻璃覆晶來作說明，然而，本發明之驅動積體電路410亦可應用於薄膜覆晶(COF)封裝，亦即將第4圖所示的玻璃基板430置換為一具有多個電極的薄膜，並藉由上述壓合方式或金屬熔合共金的方式將驅動積體電路410與薄膜壓合。In addition, the above disclosure is described by glass flip-chip. However, the driving integrated circuit 410 of the present invention can also be applied to a thin film flip chip (COF) package, that is, the glass substrate 430 shown in FIG. 4 is replaced. The film is a film having a plurality of electrodes, and the driving integrated circuit 410 is pressed against the film by the above-described pressing method or metal fusion.

簡要歸納本發明，本發明之電性連接墊結構中的絕緣層僅具有一開口部，且該開口部的形狀包含有至少一條狀彎折處，如此一來，製作於絕緣層與開口部之上的金凸塊會具有平整的表面，而使得連接墊結構與玻璃基板的電極具有良好的電性連接效果。Briefly summarized in the present invention, the insulating layer in the electrical connection pad structure of the present invention has only one opening portion, and the shape of the opening portion includes at least one bent portion, and thus is formed in the insulating layer and the opening portion. The gold bumps on the surface will have a flat surface, so that the connection pad structure has a good electrical connection effect with the electrodes of the glass substrate.

以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

100、400．．．玻璃覆晶結構100, 400. . . Glass flip-chip structure

110、410．．．驅動積體電路110, 410. . . Driving integrated circuit

112、412．．．電性連接墊結構112, 412. . . Electrical connection pad structure

120、420．．．異向性導電膜120, 420. . . Anisotropic conductive film

122、422．．．黏合劑122,422. . . Adhesive

124、424．．．導電粒子124,424. . . Conductive particle

130、430．．．玻璃基板130, 430. . . glass substrate

132、432．．．電極132,432. . . electrode

302、502．．．連接墊302, 502. . . Connection pad

304、504．．．絕緣層304, 504. . . Insulation

306、506．．．金凸塊306, 506. . . Gold bump

602、702、802．．．開口部602, 702, 802. . . Opening

第1圖為一玻璃覆晶結構的示意圖。Figure 1 is a schematic view of a glass flip-chip structure.

第2圖為壓合後之玻璃覆晶結構的示意圖。Figure 2 is a schematic view of a glass flip-chip structure after pressing.

第3圖為第1、2圖所示之電性連接墊結構的剖面圖。Fig. 3 is a cross-sectional view showing the structure of the electrical connection pads shown in Figs.

第4圖為依據本發明一實施例之一玻璃覆晶結構的示意圖。4 is a schematic view showing a glass flip-chip structure according to an embodiment of the present invention.

第5圖為依據本發明一實施例之電性連接墊結構的示意圖。Fig. 5 is a schematic view showing the structure of an electrical connection pad according to an embodiment of the present invention.

第6圖為絕緣層之開口部的形狀為一“口”字型的示意圖。Fig. 6 is a schematic view showing the shape of the opening portion of the insulating layer in a "mouth" shape.

第7圖為絕緣層之開口部的形狀為一“弓”字型的示意圖。Fig. 7 is a schematic view showing the shape of the opening portion of the insulating layer in a "bow" shape.

第8圖為絕緣層之開口部的形狀為一魚骨型的示意圖。Fig. 8 is a schematic view showing the shape of the opening portion of the insulating layer in a fishbone shape.

400．．．玻璃覆晶結構400. . . Glass flip-chip structure

410．．．驅動積體電路410. . . Driving integrated circuit

412．．．電性連接墊結構412. . . Electrical connection pad structure

420．．．異向性導電膜420. . . Anisotropic conductive film

422．．．黏合劑422. . . Adhesive

424．．．導電粒子424. . . Conductive particle

430．．．玻璃基板430. . . glass substrate

432．．．電極432. . . electrode

Claims (8)

一種電性連接墊結構，設置於一玻璃覆晶結構(Chip On Glass，COG)或是一薄膜覆晶封裝(Chip On Film，COF)中的一積體電路上，包含有：一連接墊，設置於該積體電路上；一絕緣層，設置於該連接墊上方，其中該絕緣層僅具有一開口部，且該開口部的形狀包含有至少一條狀彎折處；以及一金凸塊，設置於該絕緣層上方，其中該金凸塊可以透過該絕緣層之該開口部與該連接墊電性連接。 An electrical connection pad structure is disposed on a integrated circuit of a chip on glass (COG) or a chip on chip (COF), and includes: a connection pad. Provided on the integrated circuit; an insulating layer disposed above the connection pad, wherein the insulating layer has only one opening portion, and the shape of the opening portion includes at least one bent portion; and a gold bump, The gold bump is electrically connected to the connection pad through the opening of the insulating layer. 如申請專利範圍第1項所述之電性連接墊結構，其中該開口部包含有一“口”字型開口。 The electrical connection pad structure of claim 1, wherein the opening portion comprises a "mouth" shaped opening. 如申請專利範圍第1項所述之電性連接墊結構，其中該開口部包含有一“弓”字型開口。 The electrical connection pad structure of claim 1, wherein the opening portion comprises a "bow" shaped opening. 如申請專利範圍第1項所述之電性連接墊結構，其中該開口部包含有一魚骨型開口。 The electrical connection pad structure of claim 1, wherein the opening portion comprises a fishbone type opening. 一種積體電路，設置於一玻璃覆晶結構(Chip On Glass，COG)或是一薄膜覆晶封裝(Chip On Film，COF)中，包含有複數個電性連接墊結構，其中該複數個電性連接墊結構中每一個電性連接墊結構包含有： 一連接墊，設置於該積體電路上；一絕緣層，設置於該連接墊上方，其中該絕緣層僅具有一開口部，且該開口部的形狀包含有至少一條狀彎折處；以及一金凸塊，設置於該絕緣層上方，其中該金凸塊可以透過該絕緣層之該開口部與該連接墊電性連接。 An integrated circuit disposed in a chip on glass (COG) or a chip on chip (COF), comprising a plurality of electrical connection pads, wherein the plurality of electricity Each of the electrical connection pad structures in the connection pad structure comprises: a connecting pad is disposed on the integrated circuit; an insulating layer is disposed above the connecting pad, wherein the insulating layer has only one opening portion, and the shape of the opening portion includes at least one bent portion; and The gold bump is disposed above the insulating layer, wherein the gold bump can be electrically connected to the connection pad through the opening of the insulating layer. 如申請專利範圍第5項所述之積體電路，其中該開口部包含有一“口”字型開口。 The integrated circuit of claim 5, wherein the opening portion comprises a "mouth" shaped opening. 如申請專利範圍第5項所述之積體電路，其中該開口部包含有一“弓”字型開口。 The integrated circuit of claim 5, wherein the opening portion comprises a "bow" shaped opening. 如申請專利範圍第5項所述之積體電路，其中該開口部包含有一魚骨型開口。 The integrated circuit of claim 5, wherein the opening portion comprises a fishbone type opening.
TW099143454A 2010-12-13 2010-12-13 Bonding pad structure and integrated cicruit comprise a pluirality of bonding pad structures TWI434383B (en)

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US12/983,895 US20120146215A1 (en) 2010-12-13 2011-01-04 Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures
CN201110009080.3A CN102543894B (en) 2010-12-13 2011-01-17 Electrical connection pad structure and integrated circuit comprising a plurality of electrical connection pad structures
US13/565,785 US20120299180A1 (en) 2010-12-13 2012-08-02 Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures
US13/565,759 US20120292761A1 (en) 2010-12-13 2012-08-02 Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures

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US8633588B2 (en) * 2011-12-21 2014-01-21 Mediatek Inc. Semiconductor package
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US20130214419A1 (en) * 2012-02-16 2013-08-22 Chipbond Technology Corporation Semiconductor packaging method and structure thereof
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