JP2013153034A - Bonding pad and integrated circuit having plural bonding pad structures - Google Patents

Bonding pad and integrated circuit having plural bonding pad structures Download PDF

Info

Publication number
JP2013153034A
JP2013153034A JP2012012716A JP2012012716A JP2013153034A JP 2013153034 A JP2013153034 A JP 2013153034A JP 2012012716 A JP2012012716 A JP 2012012716A JP 2012012716 A JP2012012716 A JP 2012012716A JP 2013153034 A JP2013153034 A JP 2013153034A
Authority
JP
Japan
Prior art keywords
bonding pad
opening
insulating layer
integrated circuit
gold bump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2012012716A
Other languages
Japanese (ja)
Inventor
Yu-Ru Yang
毓儒 楊
Chi Wang Lo
智宏 盧
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ILI Techonology Corp
Original Assignee
ILI Techonology Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ILI Techonology Corp filed Critical ILI Techonology Corp
Priority to JP2012012716A priority Critical patent/JP2013153034A/en
Publication of JP2013153034A publication Critical patent/JP2013153034A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83101Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus as prepeg comprising a layer connector, e.g. provided in an insulating plate member

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a structural body in which a gold bump of a bonding pad structure has a flat surface and which has better conductivity with an electrode disposed on a glass substrate after pressed together with the glass substrate.SOLUTION: A bonding pad structure 412 disposed in an integrated circuit includes a connection pad, an insulation layer and a gold bump. The connection pad is formed on the integrated circuit. The insulation layer is formed on the connection pad and has only one opening, and at least a dent is included in a shape of the opening. The gold bump is formed on the insulation layer and electrically connected to the connection pad through the opening of the insulation layer.

Description

本発明は、ボンディングパッド構造及び特に集積回路上に配置され、チップオングラス(COG)及びチップオンフィルム(TOF)パッケージに適用されるボンディングパッド構造に関する。   The present invention relates to a bonding pad structure, and more particularly to a bonding pad structure disposed on an integrated circuit and applied to chip on glass (COG) and chip on film (TOF) packages.

図1は、1つのCOG構造100を示す。図1から、前記COG構造100は、ドライバ集積回路110、異方性導電フィルム(ACF)120及びガラス基板130を含み、前記ドライバIC110は複数のボンディングパッド構造112を含み、前記ACF120は接着剤122及び導電粒子124を含み、さらに、前記ボンディングパッド構造112に対応し前記ガラス基板130上に形成される複数の電極132を含む。   FIG. 1 shows one COG structure 100. 1, the COG structure 100 includes a driver integrated circuit 110, an anisotropic conductive film (ACF) 120 and a glass substrate 130, and the driver IC 110 includes a plurality of bonding pad structures 112, and the ACF 120 includes an adhesive 122. And a plurality of electrodes 132 corresponding to the bonding pad structure 112 and formed on the glass substrate 130.

前記COGボンディング工程においては、第1に前記ACF120を前記ガラス基板130上に配置する。さらに前記ドライバIC110の前記ボンディングパッド構造112を前記ガラス基板130上に配列させ、前記ドライバIC110と前記ガラス基板130とを一緒に特定の温度、速度及び圧力でプレスして、前記ドライバIC110の前記ボンディングパッド構造112を電気的に前記ガラス基板130の前記電極へ、前記ACF120の前記導電粒子124を介して接続し、かつ前記ドライバIC110を前記接着剤122を介して前記ガラス基板130へ接着する。   In the COG bonding process, first, the ACF 120 is disposed on the glass substrate 130. Further, the bonding pad structure 112 of the driver IC 110 is arranged on the glass substrate 130, and the driver IC 110 and the glass substrate 130 are pressed together at a specific temperature, speed, and pressure, and the bonding of the driver IC 110 is performed. The pad structure 112 is electrically connected to the electrode of the glass substrate 130 via the conductive particles 124 of the ACF 120, and the driver IC 110 is bonded to the glass substrate 130 via the adhesive 122.

さらに液晶表示装置(LCD)の高解像度化により、前記ドライバICのピン数(即ち前記ボンディングパッド構造112の数)はますます増加し、2つのボンディングパッド構造間のピッチはますます小さくなっている。前記ボンディングパッド構造112のより小さいピッチを考慮して、より小さい導電粒子(約3〜4μm)を持つ前記ACF120が2つのボンディングパッド構造112間の短絡を防止するために使用される。   Furthermore, as the resolution of a liquid crystal display (LCD) is increased, the number of pins of the driver IC (that is, the number of bonding pad structures 112) is increasing and the pitch between the two bonding pad structures is becoming smaller. . In view of the smaller pitch of the bonding pad structure 112, the ACF 120 with smaller conductive particles (about 3-4 μm) is used to prevent a short circuit between the two bonding pad structures 112.

図3には図1及び図2で示されるボンディングパッド構造112の断面図が示される。図3に示されるように、前記ボンディングパッド構造112は接続パッド302、前記接続パッド上に形成される絶縁層304及び前記接続パッド302と前記絶縁層304上に形成される金バンプ306を含む。前記接続パッド302と前記絶縁層304上に形成される前記金バンプ306の形成は、前記金バンプ306の表面をへこませる。従って、前記導電粒子のサイズがあまりに小さい場合には、前記ドライバIC110の前記ボンディングパッド構造112と前記ガラス基板130の前記電極132との間の導電性に影響を与える可能性がある。というのは、前記COGパッケージが形成される際に十分な導電粒子が分配されないからである。   FIG. 3 shows a cross-sectional view of the bonding pad structure 112 shown in FIGS. As shown in FIG. 3, the bonding pad structure 112 includes a connection pad 302, an insulating layer 304 formed on the connection pad, and a gold bump 306 formed on the connection pad 302 and the insulating layer 304. The formation of the gold bump 306 formed on the connection pad 302 and the insulating layer 304 causes the surface of the gold bump 306 to be dented. Therefore, if the size of the conductive particles is too small, the conductivity between the bonding pad structure 112 of the driver IC 110 and the electrode 132 of the glass substrate 130 may be affected. This is because sufficient conductive particles are not distributed when the COG package is formed.

米国特許出願公開第2007/0045871号US Patent Application Publication No. 2007/0045871

本発明の課題は、ボンディングパッド構造を提供することであり、前記ボンディングパッド構造の金バンプが平坦表面を有し、ガラス基板と共にプレスされた後前記ガラス基板上に配置される電極とのよりよい導電性を有するものである。   It is an object of the present invention to provide a bonding pad structure, the gold bumps of the bonding pad structure having a flat surface, and better with electrodes placed on the glass substrate after being pressed together with the glass substrate It has conductivity.

本発明の1つの実施態様によれば、集積回路上に配置されるボンディングパッド構造は、接続パッド、絶縁層及び金バンプを含む。前記接続パッドは前記集積回路上に形成される。前記絶縁層は前記接続パッド上に形成され、前記絶縁層は唯1つの開口部を持ち、前記開口部の形状は少なくともへこみを含む。前記金バンプは前記絶縁層上に形成され、前記金バンプは、前記絶縁層の前記開口部を通じて前記接続パッドへ電気的に接続される。   According to one embodiment of the present invention, the bonding pad structure disposed on the integrated circuit includes a connection pad, an insulating layer, and a gold bump. The connection pad is formed on the integrated circuit. The insulating layer is formed on the connection pad, the insulating layer has only one opening, and the shape of the opening includes at least a dent. The gold bump is formed on the insulating layer, and the gold bump is electrically connected to the connection pad through the opening of the insulating layer.

本発明の他の実施態様によれば、集積回路は複数のボンディングパッド構造を含み、前記ボンディングパッド構造のそれぞれが、接続パッド、絶縁層及び金バンプを含む。前記接続パッドは前記集積回路上に形成される。前記絶縁層は前記接続パッド上に形成され、前記絶縁層は唯1つの開口部を持ち、前記開口部の形状は少なくともへこみを含む。前記金バンプは前記絶縁層上に形成され、前記絶縁層の前記開口部を通じて前記接続パッドへ電気的に接続される。   According to another embodiment of the present invention, the integrated circuit includes a plurality of bonding pad structures, each of the bonding pad structures including a connection pad, an insulating layer, and a gold bump. The connection pad is formed on the integrated circuit. The insulating layer is formed on the connection pad, the insulating layer has only one opening, and the shape of the opening includes at least a dent. The gold bump is formed on the insulating layer and electrically connected to the connection pad through the opening of the insulating layer.

当業者にとって、本発明のこれらの及び他の課題が、下の種々の図面を参照して説明される好ましい実施態様についての詳細な説明を読むことで、明らかとなることは疑う余地がない。   For those skilled in the art, these and other objects of the present invention will no doubt become apparent upon reading the detailed description of the preferred embodiments described with reference to the various figures below.

図1は、1つのCOG構造を示す。FIG. 1 shows one COG structure. 図2は、プレスされたCOG構造を示す。FIG. 2 shows a pressed COG structure. 図3は、図1及び図2のボンディングパッド構造の断面図を示す。FIG. 3 shows a cross-sectional view of the bonding pad structure of FIGS. 図4は、本発明の1つの実施態様によるCOG構造を示す図である。FIG. 4 is a diagram illustrating a COG structure according to one embodiment of the present invention. 図5は、本発明の1つの実施態様によるボンディングパッド構造を説明する図である。FIG. 5 is a diagram illustrating a bonding pad structure according to one embodiment of the present invention. 図6は、「O」形状を持つ図4に示される絶縁層の開口部を示す。6 shows an opening in the insulating layer shown in FIG. 4 having an “O” shape. 図7は、「S」形状を持つ図4に示される絶縁層の開口部を示す。FIG. 7 shows an opening in the insulating layer shown in FIG. 4 having an “S” shape. 図8は、「魚骨(fish−bone)」形状を持つ図4示される絶縁層の開口部を示す。FIG. 8 shows an opening in the insulating layer shown in FIG. 4 having a “fish-bone” shape.

図4には、本発明の1つの実施態様によるCOG構造400を説明する図が示される。図4によれば、前記COG構造400は、ドライバIC410、ACF420及びガラス基板430を含み、前記ドライバIC410は複数のボンディングパッド構造412を含み、前記ACF420は接着剤422と導電粒子424を含み、及び前記ボンディングパッド構造412に対応する複数の電極432が前記ガラス基板430上に配置されている。前記ドライバIC410の前記ボンディングパッド構造412は、前記ACF420の前記導電粒子424を介して前記ガラス基板430の前記電極432へ接続され、前記ドライバIC410は前記接着剤422により記ガラス基板430へ接着されている。   FIG. 4 shows a diagram illustrating a COG structure 400 according to one embodiment of the present invention. According to FIG. 4, the COG structure 400 includes a driver IC 410, an ACF 420 and a glass substrate 430, the driver IC 410 includes a plurality of bonding pad structures 412, the ACF 420 includes an adhesive 422 and conductive particles 424, and A plurality of electrodes 432 corresponding to the bonding pad structure 412 are disposed on the glass substrate 430. The bonding pad structure 412 of the driver IC 410 is connected to the electrode 432 of the glass substrate 430 through the conductive particles 424 of the ACF 420, and the driver IC 410 is bonded to the glass substrate 430 by the adhesive 422. Yes.

図5は、本発明の1つの実施態様によるボンディングパッド構造412を説明する図である。図5に示されるように、前記ボンディングパッド構造412は接続パッド502、前記接続パッド502上に形成される絶縁層504及び前記接続パッド502と前記絶縁層504上に形成される金バンプを含み、前記絶縁層504は唯1つの開口部を持ち、前記開口部が少なくともへこみを含む。例えば図6、7及び8に示されるように、前記絶縁層504の前記開口部602、702、802は、「O」形状、「S」形状及び「魚骨」形状を示す。さらに前記金バンプ506は前記絶縁層504及び開口部602、702、802上に直接形成され、前記金バンプ506は記開口部602、702、802を通じて前記接続パッド503へ電気的に接続される。   FIG. 5 illustrates a bonding pad structure 412 according to one embodiment of the present invention. As shown in FIG. 5, the bonding pad structure 412 includes a connection pad 502, an insulating layer 504 formed on the connection pad 502, and gold bumps formed on the connection pad 502 and the insulating layer 504. The insulating layer 504 has only one opening, and the opening includes at least a dent. For example, as shown in FIGS. 6, 7, and 8, the openings 602, 702, 802 of the insulating layer 504 exhibit an “O” shape, an “S” shape, and a “fishbone” shape. Further, the gold bump 506 is directly formed on the insulating layer 504 and the openings 602, 702, 802, and the gold bump 506 is electrically connected to the connection pad 503 through the openings 602, 702, 802.

さらに図6〜8には、「O」形状、「S」形状及び「魚骨」形状が示されているが、これらの実施態様により本発明が限定されることを意味するものではない。本発明の他の実施態様では、前記絶縁層504の開口部は、「O」形状、「S」形状及び「魚骨」形状のあらゆる組み合わせの形状が可能であり(例えば、前記開口部が、「O」と「魚骨」の形状を共に持つ)、またこれらの単純な変更であり得る(例えば、「U」形状や逆「S」形状など)。言い換えると、前記開口部がへこみを持つ限り、これらの設計上の変形は本発明の範囲に入る。さらにここで「へこみ」とは図6〜8に示される直角へこみである必要はなく、直角でないへこみ又は曲線へこみも含むものである。   Further, FIGS. 6 to 8 show an “O” shape, an “S” shape, and a “fishbone” shape, but it is not meant that the present invention is limited by these embodiments. In another embodiment of the present invention, the opening of the insulating layer 504 may have any combination of “O” shape, “S” shape, and “fishbone” shape (eg, the opening portion may be It can have both “O” and “fishbone” shapes), and can be a simple modification of these (eg, “U” shape or inverted “S” shape). In other words, these design variations are within the scope of the present invention as long as the opening has a dent. Further, the “dent” here does not need to be a right angle recess shown in FIGS. 6 to 8 and includes a non-right angle recess or a curved recess.

さらに、前記金バンプ506の材料には、銅、ニッケル、金又はこれらのすべての組み合わせ又はSn−Pb合金が含まれ、これは前記絶縁層上にめっきにより形成され得る。   Further, the material of the gold bump 506 includes copper, nickel, gold, or a combination of all of these or Sn—Pb alloy, which can be formed on the insulating layer by plating.

前記絶縁層504の開口部が図6〜8に示される開口部のようなへこみを少なくとも持つことから、前記金バンプ506の高さの落差は大きく低減される。同じ表面を持つ前記金バンプを1例とすると、図3で示される従来のボンディングパッド構造の金バンプの高さ落差が2μmである場合、本発明のボンディングパッド構造の前記金バンプの高さ落差は1μm未満である。従って前記金バンプの表面はより平坦であり、前記ドライバIC410及び前記ガラス基板430が共にプレスされる際には十分な数の導電粒子424が分配され、その結果前記ボンディングパッド構造412及び前記電極432間の導電性を改善する。   Since the opening of the insulating layer 504 has at least a dent such as the opening shown in FIGS. 6 to 8, the drop in the height of the gold bump 506 is greatly reduced. Taking the gold bump having the same surface as an example, if the height drop of the gold bump of the conventional bonding pad structure shown in FIG. 3 is 2 μm, the height drop of the gold bump of the bonding pad structure of the present invention. Is less than 1 μm. Accordingly, the surface of the gold bump is flatter, and when the driver IC 410 and the glass substrate 430 are pressed together, a sufficient number of conductive particles 424 are distributed, so that the bonding pad structure 412 and the electrode 432 are distributed. Improve the conductivity between.

前記ボンディングパッド構造412の金バンプの高さ落差が非常に小さいことから、前記ACF420は導電性を失うことなく小さな導電粒子42を選ぶことができる。従って、前記ボンディングパッド構造412のピッチはさらに低減され、前記ドライバIC410上の金バンプの密度を上げることができる。   Since the height drop of the gold bump of the bonding pad structure 412 is very small, the ACF 420 can select small conductive particles 42 without losing conductivity. Therefore, the pitch of the bonding pad structure 412 is further reduced, and the density of gold bumps on the driver IC 410 can be increased.

さらに、一例としての前記開示のCOGパッケージを説明したが、しかし本発明の前記ドライバIC410はまた、COFパッケージにも適用可能である。即ち、図4に示されるガラス基板430は複数の電極を有するフィルムと置換され、前記ドライバIC410及び前記フィルムは共にACF又は共晶接合によりプレスされ得る。   Furthermore, the disclosed COG package has been described as an example, but the driver IC 410 of the present invention is also applicable to a COF package. That is, the glass substrate 430 shown in FIG. 4 is replaced with a film having a plurality of electrodes, and both the driver IC 410 and the film can be pressed by ACF or eutectic bonding.

まとめると、前記ボンディングパッド構造の前記絶縁層は、唯1つの開口部を持ち、前記開口部は少なくともへこみを含む。従って、前記金バンプの表面はより平面となり、前記ボンディングパッド構造と電極間の導電性がさらによくなる。   In summary, the insulating layer of the bonding pad structure has only one opening, and the opening includes at least a dent. Therefore, the surface of the gold bump is flatter, and the conductivity between the bonding pad structure and the electrode is further improved.

当業者は、本発明の教示内の範囲にある多くの本装置及び方法の変形・改良につき想到することができるであろう。
Those skilled in the art will envision many variations and modifications of the present apparatus and method which are within the scope of the present teachings.

Claims (8)

集積回路上に配置されるボンディングパッド構造であり:
前記集積回路上に形成される接続パッドと;
前記接続パッド上に形成される絶縁層であり、前記絶縁層が唯1つの開口部を有し、前記開口部の形状が少なくともへこみを持つ絶縁層と:及び
前記絶縁層上に形成される金バンプであり、前記金バンプが前記絶縁層の開口部を通じて前記接続パッドへ電気的に接続される、金バンプを含む、ボンディングパッド構造。
A bonding pad structure placed on an integrated circuit:
Connection pads formed on the integrated circuit;
An insulating layer formed on the connection pad, wherein the insulating layer has only one opening, and the shape of the opening has at least a dent; and gold formed on the insulating layer A bonding pad structure including a gold bump, wherein the gold bump is electrically connected to the connection pad through an opening of the insulating layer.
請求項1に記載のボンディングパッド構造であり、前記開口部が「O」形状の開口領域を含む、ボンディングパッド構造。   The bonding pad structure according to claim 1, wherein the opening includes an opening region having an “O” shape. 請求項1に記載のボンディングパッド構造であり、前記開口部が「S」形状の開口領域を含む、ボンディングパッド構造。   The bonding pad structure according to claim 1, wherein the opening includes an “S” -shaped opening region. 請求項1に記載のボンディングパッド構造であり、前記開口部が「魚骨」形状の開口領域を含む、ボンディングパッド構造。   The bonding pad structure according to claim 1, wherein the opening includes an opening region having a “fishbone” shape. 複数のボンディングパッド構造を含む集積回路であり、前記ボンディングパッド構造のそれぞれが:
前記集積回路上に形成される接続パッドと;
前記接続パッド上に形成される絶縁層であり、前記絶縁層が唯1つの開口部を有し、前記開口部の形状が少なくとも1つのへこみを持つ絶縁層と:及び
前記絶縁層上に形成される金バンプであり、前記金バンプが前記絶縁層の開口部を通じて前記接続パッドへ電気的に接続される、金バンプを、
含む集積回路。
An integrated circuit including a plurality of bonding pad structures, each of the bonding pad structures:
Connection pads formed on the integrated circuit;
An insulating layer formed on the connection pad, wherein the insulating layer has only one opening, and the shape of the opening has at least one indentation: and formed on the insulating layer A gold bump, wherein the gold bump is electrically connected to the connection pad through an opening in the insulating layer.
Including integrated circuits.
請求項5に記載の集積回路であり、前記開口部が「O」形状の開口領域を含む、集積回路。   6. The integrated circuit of claim 5, wherein the opening includes an “O” shaped opening region. 請求項5に記載の集積回路であり、前記開口部が「S」形状の開口領域を含む、集積回路。   6. The integrated circuit of claim 5, wherein the opening includes an “S” shaped opening region. 請求項5に記載の集積回路であり、前記開口部が「魚骨」形状の開口領域を含む、集積回路。
6. The integrated circuit according to claim 5, wherein the opening includes an opening region having a “fishbone” shape.
JP2012012716A 2012-01-25 2012-01-25 Bonding pad and integrated circuit having plural bonding pad structures Pending JP2013153034A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2012012716A JP2013153034A (en) 2012-01-25 2012-01-25 Bonding pad and integrated circuit having plural bonding pad structures

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2012012716A JP2013153034A (en) 2012-01-25 2012-01-25 Bonding pad and integrated circuit having plural bonding pad structures

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP2014005598U Continuation JP3195196U (en) 2014-10-21 2014-10-21 Integrated circuit having bonding pads and a plurality of bonding pad structures

Publications (1)

Publication Number Publication Date
JP2013153034A true JP2013153034A (en) 2013-08-08

Family

ID=49049180

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2012012716A Pending JP2013153034A (en) 2012-01-25 2012-01-25 Bonding pad and integrated circuit having plural bonding pad structures

Country Status (1)

Country Link
JP (1) JP2013153034A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024032428A1 (en) * 2022-08-07 2024-02-15 铜陵国展电子有限公司 Double-layer flexible circuit board, electronic product, and conduction method

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131698A (en) * 1997-07-14 1999-02-02 Texas Instr Japan Ltd Semiconductor device and its manufacture and structure for mounting
JP2000124263A (en) * 1998-10-16 2000-04-28 Fuji Electric Co Ltd Semiconductor integrated device
JP2002252248A (en) * 2001-02-26 2002-09-06 Casio Comput Co Ltd Semiconductor device and its jointing structure
JP2003318211A (en) * 2002-04-24 2003-11-07 Sharp Corp Semiconductor device
JP2009266998A (en) * 2008-04-24 2009-11-12 Seiko Epson Corp Semiconductor device and method of manufacturing the same

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH1131698A (en) * 1997-07-14 1999-02-02 Texas Instr Japan Ltd Semiconductor device and its manufacture and structure for mounting
JP2000124263A (en) * 1998-10-16 2000-04-28 Fuji Electric Co Ltd Semiconductor integrated device
JP2002252248A (en) * 2001-02-26 2002-09-06 Casio Comput Co Ltd Semiconductor device and its jointing structure
JP2003318211A (en) * 2002-04-24 2003-11-07 Sharp Corp Semiconductor device
JP2009266998A (en) * 2008-04-24 2009-11-12 Seiko Epson Corp Semiconductor device and method of manufacturing the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2024032428A1 (en) * 2022-08-07 2024-02-15 铜陵国展电子有限公司 Double-layer flexible circuit board, electronic product, and conduction method

Similar Documents

Publication Publication Date Title
US20120299180A1 (en) Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures
JP4968665B2 (en) Flat display panel and connection structure
TWI381464B (en) The bump structure and its making method
WO2012121113A1 (en) Electronic circuit substrate, display device, and wiring substrate
TWI262347B (en) Electrical conducting structure and liquid crystal display device comprising the same
WO2021103354A1 (en) Display apparatus
TW201511214A (en) Semiconductor device
JP2017175093A (en) Electronic component, connection body, and method of designing electronic component
JP2015076486A (en) Display device
JP2006222407A (en) Structure and method for bonding ic chip
US20180114769A1 (en) Chip Packaging Structure and Related Inner Lead Bonding Method
US20150069602A1 (en) Chip-on-film device
JP2013153034A (en) Bonding pad and integrated circuit having plural bonding pad structures
JP3195196U (en) Integrated circuit having bonding pads and a plurality of bonding pad structures
JP2009295857A (en) Connecting structure of ic chip and external wiring, and ic chip
JP2014082282A (en) Semiconductor chip and display panel equipped with the same
KR101344345B1 (en) Bonding pad structure and integrated circuit comprising a plurality of bonding pad structures
TWI276212B (en) Electric connecting pad structure
JP2004134653A (en) Substrate connecting structure and fabricating process of electronic parts therewith
JP2009135447A (en) Circuit connection method
JPH10233401A (en) Semiconductor device
JP4699089B2 (en) Chip-on-film semiconductor device
TWI383460B (en) Metal bump structure and its application in package structure
JP2009032949A (en) Ic chip, and method of mounting ic chip
JP3687674B2 (en) Semiconductor device, semiconductor chip, electronic module and electronic device

Legal Events

Date Code Title Description
A977 Report on retrieval

Free format text: JAPANESE INTERMEDIATE CODE: A971007

Effective date: 20131122

A131 Notification of reasons for refusal

Free format text: JAPANESE INTERMEDIATE CODE: A131

Effective date: 20131126

A521 Written amendment

Free format text: JAPANESE INTERMEDIATE CODE: A523

Effective date: 20140123

A02 Decision of refusal

Free format text: JAPANESE INTERMEDIATE CODE: A02

Effective date: 20140708