TWI415259B - 增進型-耗損型半導體結構及其製造方法 - Google Patents

增進型-耗損型半導體結構及其製造方法 Download PDF

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TWI415259B
TWI415259B TW094146747A TW94146747A TWI415259B TW I415259 B TWI415259 B TW I415259B TW 094146747 A TW094146747 A TW 094146747A TW 94146747 A TW94146747 A TW 94146747A TW I415259 B TWI415259 B TW I415259B
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gate
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Hassan Maher
Pierre Michel Marcel Baudet
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Ommic Sas
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Description

增進型耗損型半導體結構及其製造方法
本發明相關於一半導體結構，其包括增進及耗損兩模式異質結構場效電晶體(HFET)，尤其(但不僅僅)相關於包括有數個高電子移動性電晶體(HEMT)的一結構。
在一典型HFET中，一金屬閘極接點在一通道半導體層之上形成具一蕭特基(Schottky)障壁半導體層的一蕭特基障壁，該通道半導體層以該蕭特基障壁半導體層形成一異質結構。數個源極及汲極接點設置在該閘極的任一側。在該金屬閘極接點上的電壓控制在該等源極與汲極接點間的通道中傳導。
通常，此類HFET實施成具有一高電子行動力，及因此習知為高電子移動性電晶體(HEMT)。
此類HEMT可實施為增進模式裝置，其除非施加一電壓到該閘極以導通該裝置，否則是截止的，或實施為耗損模式裝置，其是導通的直到施加一電壓到該閘極加以截止。需要使用一單一製程以實施增進及耗損兩類型FET，俾使該等增進及耗損類型FET整合起來。此類積體FET習知為增進型－耗損型高電子移動性電晶體(ED－HEMT)，其同時包括增進型及耗損型HEMT。
在此類ED－HEMT中，該通道中每一單位面積需要一高電荷，用以不僅提高固有效能，亦減低寄生串聯電阻。此要求通常藉由在接近該通道處包括一△摻雜層以提供該通道中的載子而達成。
圖1說明此一HEMT。一基板2形成該基極。
一緩衝層4設置在該基板上，及一通道層6設置在該緩衝層4上。隨後有一障壁層8，及一蓋帽層10設置在該基板上面。障壁層8中的一△摻雜層16提供數個電子至通道6。
該結構可簡單地藉由調整該閘極位置而產生一增進型FET或一耗損型FET。為產生一增進型FET，可部分地蝕刻掉該蓋帽層10及該障壁層而在該障壁層中產生一凹洞，及在該凹洞中設置一閘極12。為產生一耗損型FET，蝕刻掉該蓋帽層及在該障壁層8的頂部設置一閘極14。
不幸地，該通道中為良好效能所需的高載子密度要求該障壁層8極薄，通常是小於5 nm，不然該增進型HEMT的通道無法在零閘極－源極電壓(Vg s ＝0)夾止。橫越此薄障壁的靜電場可以極高，即使未施加閘極電壓，該靜電場可傳遞相當的漏電通過該閘極障壁，而減低最大順向閘極電壓及該閘極電壓擺動。
此外，該等E－HEMT的串聯電阻可嚴重地限制裝置效能。
因此仍需要改良式ED－HEMT及對應的製造方法。
根據本發明，揭示一種半導體結構，其包括至少一增進模式電晶體及至少一耗損模式電晶體，該半導體結構包括：一基板，其具有一第一主表面；一緩衝半導體層，其橫越該第一主表面；一通道半導體層，其在該緩衝層上；一障壁半導體層，其具有一第二能帶隙，其高於該通道層上的第一能帶隙；一第一摻雜層，其在該緩衝層中毗鄰該通道層，以提供數個載子到該通道層；及一第二摻雜層，其在該障壁層上方；其中該通道層以具一能帶隙的半導體製成，該能帶隙小於該緩衝層的半導體的能帶隙及小於該障壁層的半導體的能帶隙；該至少一增進模式電晶體包括一閘極，其延伸通過該第二摻雜層及與該障壁層接觸；及該至少一耗損模式電晶體包括一閘極，其設置在該第二摻雜層上方。
該配置能減低該增進型HEMT的串聯電阻，及傳遞較良好靜態及動態效能。可得到良好的輸出傳導力及雜訊圖形，連同寬的閘極電壓擺動。
藉由從該第一摻雜層提供數個電子到該通道，不需要在障壁層中提供一△摻雜層，其極接近該通道層，即小於5 nm。在圖1的先前技藝配置中，△摻雜層16接近通道6且通常是非一致地摻雜。此可輕易造成漏電路徑。在本發明中，可避免此情形。因此，該第二摻雜層與該通道間的障壁層厚度較佳是大於5 nm，更好是大於10 nm。
在一方法中，該第二摻雜層界定一開口以通過在該增進模式電晶體的第二摻雜層，及該增進模式電晶體的閘極延伸通過該開口到該障壁層上。
在另一方法中，該增進模式電晶體的閘極包括一閘極擴散層，其延伸通過該第二摻雜層。該閘極擴散層可由鉑製成。
該等閘極可具有一T型閘極結構，其具有一接觸區域以與第二障壁層接觸，及橫斷面大於該接觸區域的一區域位在該接觸區域上方。
較佳地，該第一摻雜層係一△摻雜層。
該第二摻雜層可為一△摻雜層。一間隔層可設置在該第二摻雜層上。
一蓋帽層可設置在該第二摻雜層上，若存在該間隔層，或在該間隔層上。該蓋帽層可界定數個開口以用於該等增進模式電晶體的數個閘極，及用於該等耗損模式電晶體的數個閘極。
在數個實施例中，該通道層由砷化鎵銦(GaInAs)製成，及該等緩衝及障壁層由砷化鋁銦(AlInAs)製成。可使用其他任何適當材料。
在另一概念中，提供一種製造一半導體結構的方法，該半導體結構包括至少一增進模式電晶體及至少一耗損模式電晶體，該方法包括：提供一基板，其具有一第一主表面；沈積一緩衝半導體層以橫越該第一主表面，及在該緩衝層中形成一第一摻雜層；在該緩衝層上沈積一通道半導體層；在該通道層上沈積一障壁半導體層，其中該通道半導體層具有一能帶隙，其小於該緩衝層的半導體的能帶隙及小於該障壁層的半導體的能帶隙；在該障壁層上方沈積一第二摻雜層；在該障壁層上沈積一閘極，以用於該至少一增進模式電晶體；及在該第二摻雜層上沈積一閘極，以用於該至少一耗損模式電晶體。
該製造方法的一特殊有利點為不需要蝕刻停止層。在傳統的ED－HEMT中，一蝕刻停止層用以確保用以形成該等增進型裝置的閘極的蝕刻準確地停止在該正確位置。然而，使用本發明，該夾止電壓僅微弱地依該增進型閘極下方的障壁層厚度而定，因此不需要蝕刻停止層，換言之，該等增進型及耗弱型電晶體的閘極可放置在相同深度。因此不需要特殊蝕刻停止層以用於該增進型電晶體。反而，使用一閘極擴散層或一閘極，其延伸通過一開口大體上到該正確深度。
在蕭特基層中缺一蝕刻停止層容許該E－HEMT有明顯改善的串聯電阻，其按次可傳遞更優於傳統上以此類型HEMT達成的動態效能。
形成該至少一增進模式電晶體的步驟可包括，蝕刻一閘極開口以通過該第二摻雜層，及在該開口中的該障壁層上沈積該閘極。
形成該至少一增進模式電晶體的步驟可包括，在該第二摻雜層上沈積一第一閘極材料，之後擴散該第一閘極材料的材料以通過該第二摻雜層到該障壁層。
形成該等閘極的步驟包括沈積一擴散閘極材料，其在該增進模式電晶體，但非該耗損模式電晶體，的第二摻雜層上擴散通過該第二摻雜層；在該增進模式電晶體的擴散閘極材料上及在該耗損模式電晶體的第二摻雜層上沈積閘極材料；及加熱該結構，使該擴散閘極材料擴散通過該第二摻雜層到該障壁層。
該擴散閘極材料可以鉑製成。
參照至圖2，本發明的一第一實施例以一磷化銦(InP)基板2開始。
在基板2上沈積一AlInAs緩衝層4，其在該實施例中以Al0 . 4 8 In0 . 5 2 As製成。使該緩衝層△摻雜以提供一第一△摻雜層18，其接近該緩衝層的頂部。該緩衝層厚度係32 nm及該緩衝層頂部下方的△摻雜層係5 nm。第一△摻雜層18的製造可藉由熟諳此藝者習知的任何方法實施，例如包括中斷該AlInAs緩衝層的成長及沈積數個雜質。
接著，一GaInAs通道層6沈積到10 nm的厚度，之後是沈積厚度15 nm的一AlInAs障壁層8。該AlInAs層的成分又是Al0 . 4 8 In0 . 5 2 As。該AlInAs障壁層8之後是一第二△摻雜層20。此第二△摻雜層之後按次是厚度大約是5 nm的一AlInAs間隔層22，。一砷化銦鎵(InGaAs)蓋帽層10設置在AlInAs間隔層22之上。
該通道層的傳導能帶低於該等障壁及緩衝層的傳導能帶，其係經由該等障壁及緩衝層使用高於該通道層的能帶隙材料而達成。
提供一增進模式HEMT 24係藉由蝕刻一開口28以通過蓋帽層10及間隔層22到障壁層8。接著在該障壁層8上，在該開口28中沈積一增進型HEMT閘極12。
提供一耗損模式HEMT 26係藉由蝕刻一開口30以通過蓋帽層10，但未通過間隔層22，及在該開口30中沈積一耗損型HEMT閘極14。
如圖2中所見，該等閘極形成所謂的"T型閘"，形狀像一"T"字，其中該"T"型的橫桿的最下部與蓋帽層10之間未有接觸。
應注意，熟諳此藝者可將以上許多細節加以變化。例如，該基板可為磷化銦(InP)、砷化鎵(GaAs)等。如熟諳此藝者所了解，該緩衝層及間隔層的厚度可不同以達成期望特性。該等雜質可視需要而沈積。
該通道層可由任何合適的半導體材料製成，雖並非要求，但最好是InGaAs等高電子行動材料。
該障壁層的材料亦可視需要而有所不同。
圖3顯示一第二實施例，其與圖2配置不同之處在於，該第二摻雜層並非如圖2配置中的一△摻雜層，而是一較重摻雜的AlInAs摻雜層32。此層意指亦不需要圖2的間隔層22。蓋帽層10直接在AlInAs摻雜層32上形成。
在此配置中，用於增進模式HEMT 24的開口28通過蓋帽層10及摻雜層32，俾使增進型閘極12又在障壁層8上形成。用於耗損模式HEMT 26的開口30通過蓋帽層10，俾使該閘極在摻雜層32的頂部形成。
圖4以能帶圖說明在個別蓋帽層下方的三個結構，以0.00 μm界定為該蓋帽層下方的位置，即在該閘極與該下層間的介面以用於一耗損模式HEMT。用於一增進模式HEMT，因該閘極在該通道中較低，因此該HEMT自5 nm以下開始，及在該HEMT中0至5 nm的範圍並無資料。增進模式HEMT以虛線顯示，第二實施例的耗損模式HEMT以點線表示，及第一實施例的耗損模式HEMT以點虛線表示。
如所見，增進模式HEMT在費米(Fermi)能階34以下未具有該通道層的任何傳導能帶，而需要施加閘極電壓以導通的一增進模式HEMT亦是如此。對照之下，耗損模式HEMT的兩能帶圖在費米能階34以下確實具有該通道層傳導能帶，因此代表正常導通的耗損模式電晶體。
此等實施例的有利點在於，由於夾止電壓幾乎與障壁層8厚度無關，因此不必精準地控制用於增進模式HEMT 24的閘極開口28。此意指障壁層8不需作為一優良蝕刻停止層，其容許一明顯改善的串聯電阻且因而提高一E－HEMT的良好動態效能，其先前在ED－HEMT中若非不可能達成，亦是極為困難。
例如，InGaAs與InAlAs間的蝕刻率中的選擇約為20。此不足以用於先前技藝配置，但在本方法中卻可接受，因此不需添加額外的蝕刻停止層。
圖5中顯示再一實施例。此實施例使用如第二實施例中的一摻雜層32，但其可調適成反而使用如第一實施例中的一△摻雜層。在此配置中，在增進及耗損模式HEMT 24、26兩者中，一相同深度的的開口30設置在蓋帽層10中。接著沈積一閘極。用於該等增進及耗損模式HEMT閘極材料是各不相同。
用於耗損模式HEMT，閘極材料40係較傳統的鈦/鉑/金複合層42。用於增進模式FET，一擴散鉑層44設置在障壁層20上，之後是如用於耗損模式HEMT的相同鈦/鉑/金複合層42。
一擴散過程在該烘烤步驟中實施，該烘烤步驟包括在該過程中的任何事件中，該擴散過程擴散鉑以通過障壁層20，俾使該鉑形成一擴散閘極46，其與該摻雜層接觸...。該擴散閘極的深度可藉由變化該擴散鉑層的厚度而加以控制。
依此，由於該增進模式FET中不需精確控制摻雜層32的蝕刻，因此可輕易地製造該埋入式增進型閘極。
在所有實施例中，本發明容許一障壁層厚度在5 nm以上，例如10 nm或更厚。
在耗損模式HEMT的閘極下方沒有圖1先前技藝配置的上摻雜層16，因而提高了該裝置特性。
可輕易使用相同半導體層順序以製造增進及耗損模式HEMT兩者。
本發明因此允許製造具良好靜態及動態效能、低串聯電阻及改良式輸出傳導力的一ED－HEMT。由於較低漏電，因此即使在較低頻率亦提高雜訊效能，及該有效障壁高度良好，其導致寬的可容許閘極電壓擺動以用於E－HEMT。
按照該等動態效能，該D－HEMT提供類似於ED－HEMT結構中傳統D模式HEMT的效能，但因較低輸出傳導力而在最大頻率中有明顯的提高。
應了解，本發明未侷限於此等實施例，尤其可視需要而使用不同材料、層厚度及摻雜濃度。
請注意，此說明書中，使用"之上"或"上方"等用詞並非用以指該電晶體結構在空間中的特殊方向。此外，此等用詞亦非用以暗示"直接在上方"，俾當說到一第一層在一第二層上方時，在該等第一與第二層之間可選擇性地有一中間層。
2．．．基板
4．．．緩衝層
6．．．通道層
8．．．障壁層
10．．．蓋帽層
12、14．．．閘極
16、18、20、32．．．摻雜層
22．．．間隔層
24．．．增進模式高電子移動性電晶體(E－HEMT)
26．．．耗損模式高電子移動性電晶體(D－HEMT)
28、30．．．開口
40．．．閘極材料
42．．．鈦/鉑/金複合層
44．．．擴散鉑層
46．．．擴散閘極
已參照至附圖，僅以舉例方式，說明本發明的數個實施例以達更了解目的，其中：圖1說明一傳統ED－HEMT結構；圖2根據本發明說明一ED－HEMT結構的一第一實施例；圖3根據本發明說明一ED－HEMT結構的一第二實施例；圖4以能帶圖說明該等第一及第二實施例的增進型及耗損型HEMT；及圖5根據本發明說明一ED－HEMT結構的一第三實施例。
該等附圖為示意圖且未按比例繪製。圖中相同或對應組件以相同參考數字表示。
2．．．基板
4．．．緩衝層
6．．．通道層
8．．．障壁層
10．．．蓋帽層
12、14．．．閘極
18、20．．．摻雜層
22．．．間隔層
24．．．增進模式高電子移動性電晶體(E－HEMT)
26．．．耗損模式高電子移動性電晶體(D－HEMT)
28、30．．．開口

Claims (17)

  1. 一種半導體結構，包括至少一增進模式電晶體及至少一耗損模式電晶體，該半導體結構包括：一基板(2)，其具有一第一主表面；一半導體緩衝層(4)，其橫越該第一主表面；一半導體通道層(6)，其在該緩衝層上；一半導體障壁層(8)，其具有一第二能帶隙，其高於該通道層上之第一能帶隙；一第一摻雜體層(18)，其在該緩衝層中毗鄰該通道層(6)，以提供數個載子至該通道層(6)；及一第二摻雜層(20、32)，其在該障壁層上方；其中該半導體通道層(6)具有一能帶隙，其小於該緩衝層(4)之半導體之能帶隙，及小於該障壁層(8)之半導體之能帶隙；該至少一增進模式電晶體(24)包括一閘極(12)，其延伸通過該第二摻雜層(20、32)且與該障壁層(8)接觸；及該至少一耗損模式電晶體(26)包括一閘極(14)，其設置在該第二摻雜層(20、32)上方，其中在該通道層及與該障壁層接觸之該閘極之間沒有摻雜層。
  2. 如請求項1之半導體結構，其中該第二摻雜層(20、32)界定一開口以通過在該增進模式電晶體中之第二摻雜層，及該增進模式電晶體之閘極(12)延伸通過該開口至該障壁層(8)上。
  3. 如請求項1之半導體結構，其中該增進模式電晶體之閘極(12)包括一閘極擴散層(40)，其延伸通過該第二摻雜層。
  4. 如請求項3之半導體結構，其中該閘極擴散層由鉑製成。
  5. 如請求項3或4之半導體結構，其中該等閘極具有一T型閘極結構，其具有一接觸區域以接觸第二障壁層，及一橫斷面大於該接觸區域之區域，其在該接觸區域上方。
  6. 如請求項1至4中任一項之半導體結構，其中該第一摻雜層(18)係一△摻雜層。
  7. 如請求項1至4中任一項之半導體結構，其中該第二摻雜層(20、32)係一△摻雜層(20)，在該第二摻雜層上尚包括一間隔層(22)，該增進模式電晶體(24)之閘極開口(28)通過該間隔層(22)及該第二摻雜層(20)。
  8. 如請求項1至4中任一項之半導體結構，在該第二摻雜層(20、32)之上尚包括一蓋帽層(10)，其中該蓋帽層界定數個開口(28、30)，以用於該增進模式電晶體(24)之閘極(12)，及用於該耗損模式電晶體(26)之閘極(14)。
  9. 一種製造一半導體結構之方法，該半導體結構包括至少一增進模式電晶體及至少一耗損模式電晶體，該方法包括：提供一基板(2)，其具有一第一主表面；沈積一半導體緩衝層(4)以橫越該第一主表面，及在該緩衝層(4)中形成一第一摻雜層(18)；在該緩衝層(4)上沈積一半導體通道層(6)；在該通道層(6)上沈積一半導體障壁層(8)，其中該半導 體通道層(6)具有一能帶隙，其小於該緩衝層(4)之半導體之能帶隙，及小於該障壁層(8)之半導體之能帶隙；在該障壁層(8)上方沈積一第二摻雜層(20、32)；在該障壁層(8)上沈積一閘極(12)，以用於該至少一增進模式電晶體(24)；及在該第二摻雜層(20、32)上沈積一閘極(14)，以用於該至少一耗損模式電晶體(26)，其中在該通道層與在該障壁層上沈積之該閘極之間沒有摻雜層。
  10. 如請求項9之方法，其中形成該至少一增進模式電晶體之步驟包括，蝕刻一閘極開口(28)以通過該第二摻雜層(20、32)，及在該開口(28)中之障壁層上沈積該閘極(12)。
  11. 如請求項9之方法，其中形成該至少一增進模式電晶體之步驟包括在該第二摻雜層(20、32)上沈積一第一閘極材料，接著擴散該第一閘極材料之材料以通過該第二摻雜層(20、32)至該障壁層(8)。
  12. 如請求項11之方法，其中形成該等閘極之步驟包括：沈積一擴散閘極材料，其在該增進模式電晶體，但並非該耗損模式電晶體，之第二摻雜層上擴散通過該第二摻雜層；在該增進模式電晶體之擴散閘極材料上及在該耗損模式電晶體之第二摻雜層(20、32)上沈積閘極材料；及加熱該結構以擴散該擴散閘極材料以通過該第二摻雜層(20、32)至該障壁層(8)。
  13. 如請求項12之方法，其中該擴散閘極材料係鉑。
  14. 如請求項9至13中任一項之製造半導體結構之方法，其包括△摻雜該緩衝層(4)以沈積該第一摻雜層(18)之步驟。
  15. 如請求項9至13中任一項之製造半導體結構之方法，其中在該障壁層上方沈積一第二摻雜層之步驟沈積一△摻雜層(20)，該方法尚包括在該△摻雜層(20)上沈積一間隔層(22)。
  16. 如請求項9至13中任一項之製造半導體結構之方法，尚包括：在該第二摻雜層(20、32)上方沈積一蓋帽層(10)；及在該蓋帽層中界定數個開口(28、30)，以用於該或各增進模式電晶體(24)之閘極(12)，及用於該或各耗損模式電晶體(26)之閘極(14)。
  17. 如請求項16之方法，其中該等閘極形成T型電極以接觸該第二摻雜層，但未接觸該蓋帽。
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WO2006070297A2 (en) 2006-07-06
JP2008527687A (ja) 2008-07-24
KR20070093074A (ko) 2007-09-17
WO2006070297A3 (en) 2006-10-05
US20090026501A1 (en) 2009-01-29
CN101095233A (zh) 2007-12-26

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