TWI414006B - 含有矽及碳之磷摻雜磊晶層的原位形成方法 - Google Patents

含有矽及碳之磷摻雜磊晶層的原位形成方法 Download PDF

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Publication number
TWI414006B
TWI414006B TW096147287A TW96147287A TWI414006B TW I414006 B TWI414006 B TW I414006B TW 096147287 A TW096147287 A TW 096147287A TW 96147287 A TW96147287 A TW 96147287A TW I414006 B TWI414006 B TW I414006B
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TW
Taiwan
Prior art keywords
carbon
substrate
source
phosphorus
epitaxial film
Prior art date
Application number
TW096147287A
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English (en)
Chinese (zh)
Other versions
TW200832529A (en
Inventor
金以寬
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應用材料股份有限公司
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Publication date
Application filed by 應用材料股份有限公司 filed Critical 應用材料股份有限公司
Publication of TW200832529A publication Critical patent/TW200832529A/zh
Application granted granted Critical
Publication of TWI414006B publication Critical patent/TWI414006B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/797—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions being in source or drain regions, e.g. SiGe source or drain
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02529—Silicon carbide
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/0257—Doping during depositing
    • H01L21/02573—Conductivity type
    • H01L21/02576—N-type
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/027—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs
    • H10D30/0275—Manufacture or treatment of FETs having insulated gates [IGFET] of lateral single-gate IGFETs forming single crystalline semiconductor source or drain regions resulting in recessed gates, e.g. forming raised source or drain regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/608—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having non-planar bodies, e.g. having recessed gate electrodes
    • H10P14/24—
    • H10P14/27—
    • H10P14/3408—
    • H10P14/3442—

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Chemical Vapour Deposition (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Recrystallisation Techniques (AREA)
  • Drying Of Semiconductors (AREA)
TW096147287A 2006-12-12 2007-12-11 含有矽及碳之磷摻雜磊晶層的原位形成方法 TWI414006B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/609,826 US8394196B2 (en) 2006-12-12 2006-12-12 Formation of in-situ phosphorus doped epitaxial layer containing silicon and carbon

Publications (2)

Publication Number Publication Date
TW200832529A TW200832529A (en) 2008-08-01
TWI414006B true TWI414006B (zh) 2013-11-01

Family

ID=39498574

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096147287A TWI414006B (zh) 2006-12-12 2007-12-11 含有矽及碳之磷摻雜磊晶層的原位形成方法

Country Status (4)

Country Link
US (1) US8394196B2 (enExample)
JP (2) JP2010512668A (enExample)
TW (1) TWI414006B (enExample)
WO (1) WO2008073894A1 (enExample)

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US8367548B2 (en) * 2007-03-16 2013-02-05 Asm America, Inc. Stable silicide films and methods for making the same
DE102008030854B4 (de) * 2008-06-30 2014-03-20 Advanced Micro Devices, Inc. MOS-Transistoren mit abgesenkten Drain- und Source-Bereichen und nicht-konformen Metallsilizidgebieten und Verfahren zum Herstellen der Transistoren
US7994015B2 (en) * 2009-04-21 2011-08-09 Applied Materials, Inc. NMOS transistor devices and methods for fabricating same
US8999798B2 (en) * 2009-12-17 2015-04-07 Applied Materials, Inc. Methods for forming NMOS EPI layers
US8598003B2 (en) 2009-12-21 2013-12-03 Intel Corporation Semiconductor device having doped epitaxial region and its methods of fabrication
WO2012102755A1 (en) * 2011-01-28 2012-08-02 Applied Materials, Inc. Carbon addition for low resistivity in situ doped silicon epitaxy
US8652945B2 (en) * 2011-02-08 2014-02-18 Applied Materials, Inc. Epitaxy of high tensile silicon alloy for tensile strain applications
KR102534730B1 (ko) 2015-04-10 2023-05-26 어플라이드 머티어리얼스, 인코포레이티드 선택적 에피택셜 성장을 위한 성장률을 증강시키기 위한 방법
KR102742581B1 (ko) 2019-09-24 2024-12-13 삼성전자주식회사 반도체 소자 및 이의 제조 방법

Citations (4)

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US20050079691A1 (en) * 2003-10-10 2005-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US20060115934A1 (en) * 2004-12-01 2006-06-01 Yihwan Kim Selective epitaxy process with alternating gas supply
US20060148151A1 (en) * 2005-01-04 2006-07-06 Anand Murthy CMOS transistor junction regions formed by a CVD etching and deposition sequence
US20060234504A1 (en) * 2005-02-04 2006-10-19 Matthias Bauer Selective deposition of silicon-containing films

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Publication number Priority date Publication date Assignee Title
US20050079691A1 (en) * 2003-10-10 2005-04-14 Applied Materials, Inc. Methods of selective deposition of heavily doped epitaxial SiGe
US20060115934A1 (en) * 2004-12-01 2006-06-01 Yihwan Kim Selective epitaxy process with alternating gas supply
US20060148151A1 (en) * 2005-01-04 2006-07-06 Anand Murthy CMOS transistor junction regions formed by a CVD etching and deposition sequence
US20060234504A1 (en) * 2005-02-04 2006-10-19 Matthias Bauer Selective deposition of silicon-containing films

Also Published As

Publication number Publication date
JP2013070055A (ja) 2013-04-18
JP5551745B2 (ja) 2014-07-16
JP2010512668A (ja) 2010-04-22
US8394196B2 (en) 2013-03-12
WO2008073894A1 (en) 2008-06-19
US20080138939A1 (en) 2008-06-12
TW200832529A (en) 2008-08-01

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