TWI393215B - 半導體裝置之製造方法 - Google Patents

半導體裝置之製造方法 Download PDF

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TWI393215B
TWI393215B TW098100644A TW98100644A TWI393215B TW I393215 B TWI393215 B TW I393215B TW 098100644 A TW098100644 A TW 098100644A TW 98100644 A TW98100644 A TW 98100644A TW I393215 B TWI393215 B TW I393215B
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Atsushi Kariya
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Description

半導體裝置之製造方法
本申請案係基於日本專利申請案第2008-118516號，將其內容以參考文獻方式併入於此。
本發明係關於半導體裝置之製造方法，該方法使用在形成於絕緣層中之孔洞內形成鎢層之程序。
接觸栓塞(contact plug)經常使用於連接一電晶體至一上部互連層或使用於連接一互連層至另一互連層。例如，如同日本公開專利公報第11-87268號、日本公開專利公報第2007-9298號、日本國家公開專利公報第2001-525491號、美國專利第6,309,966號所說明，接觸栓塞係藉由在形成於絕緣中間層中之孔洞內形成一鎢層而形成。
在專利文件中，日本公開專利公報第11-87268號揭露：為了在孔洞中選擇性地生長一鎢層，一第一鎢層在200℃至260℃之溫度下形成，然後一第二鎢層在280℃至340℃之溫度下形成。根據日本公開專利公報第11-87268號，如果溫度高於上述溫度，則電阻變大，而不可能有選擇性之生長。
日本國家公開專利公報第2001-525491號揭露：當鎢層係藉由成核步驟及塊材沉積步驟所形成時，在該成核步驟及該塊材沉積步驟之間施行一壓力增加步驟。在該壓力增加步驟中，含鎢源不包含在處理氣體中。在日本國家公開專利公報第2001-525491號中，係將基板溫度設定在325℃至450℃。
為了在維持接觸栓塞之可靠度下使接觸栓塞之電阻較低，增進鎢層對形成在絕緣層中之孔洞之填充能力及擴大鎢層之晶粒尺寸係有效的。另一方面，提升半導體裝置製造程序之生產率係重要的。
在一實施例中，提供一用於製造半導體裝置的方法，包含：在設置於一半導體基板之表面上之一絕緣層中形成一孔洞；藉由將運載至反應室內之該半導體基板，在等於或大於330℃且等於或小於400℃之溫度下加熱，及將含鎢氣體及至少乙硼烷(B2 H6 )氣體及矽甲烷(SiH4 )氣體其中之一導入該反應室內，而在該孔洞中形成一第一鎢層；將氫氣(H2 )氣體及惰性氣體至少其中之一導入該反應室內，及將該半導體基板之溫度以30秒以上之時間升高至等於或大於370℃且等於或小於410℃；及藉由將含鎢氣體導入該反應室內，而在該第一鎢層上形成一第二鎢層。
根據本發明，改善了鎢層對形成在絕緣層中之孔洞之填充能力，且擴大了鎢層之晶粒尺寸。再者，提升了半導體裝置製造程序之生產率。
現將參考例示性實施例來闡述本發明。熟習本技藝者將瞭解，利用本發明之教示可完成許多替代性之實施例，且本發明不限於為解釋目的加以說明之實施例。
以下將參考隨附圖式而說明本發明之一例示實施例。圖式中，類似參考標號表示類似零件，而不會重複說明。
圖1為說明根據本發明例示實施例之半導體裝置之製造方法流程圖。在該半導體裝置之製造方法中，首先在配置於半導體基板之表面上之絕緣層中形成一孔洞(S10)。將運載至反應室內之該半導體基板，在等於或大於330℃且等於或小於400℃之溫度下加熱(S20)。隨後，將含鎢氣體及至少乙硼烷(B2 H6 )氣體及矽甲烷(SiH4 )氣體其中之一導入該反應室內以因此在該孔洞中形成一第一鎢層(S30)。然後，將氫氣(H2 )氣體及惰性氣體至少其中之一導入該反應室內，然後將該半導體基板之溫度以30秒以上之時間升高至等於或大於370℃且等於或小於410℃(S40)。然後，將含鎢氣體導入該反應室內，藉此在該第一鎢層上形成一第二鎢層(S50)。
接下來，根據本發明之該例示實施例之半導體裝置製造方法將參考圖2至5之橫剖面圖而加以詳細說明。
首先，如圖2所示，將隔離層102及電晶體120及140形成在例如矽基板之半導體基板100上。該電晶體120及140包含在閘電極上之矽化物層122及142、及在作為源極或汲極之擴散層上之矽化物層124、126、144、及146。具有矽化物層126之擴散層不只用作電晶體120之元件，亦作為設置在電晶體120附近之電晶體140之元件。然後，將絕緣中間層200形成在電晶體120、140及隔離層102上。在圖2中，絕緣中間層200具有多層結構。
隨後，使用例如遮罩圖案及蝕刻技術，而將絕緣中間層200加以選擇性移除，俾能在絕緣中間層200中形成孔洞221、222、223、224、及225。孔洞221提供用以在擴散層上之矽化物層144上及在電晶體140之閘電極上之矽化物層142上形成接觸栓塞之空間；孔洞222提供用以在電晶體140之擴散層上之矽化物層144上形成接觸栓塞之空間；孔洞223提供用以在矽化物層126上形成接觸栓塞之空間；孔洞224提供用以在電晶體120之閘電極上之矽化物層122上形成接觸栓塞之空間；孔洞225提供用以在電晶體120之擴散層上之矽化物層124上形成接觸栓塞之空間。孔洞221至225之直徑係例如等於或大於50nm且等於或小於130nm。
然後，將半導體基板100運載至反應室內。將阻隔層230形成在孔洞221至225之底部表面及側壁及絕緣中間層200上。阻隔層230之功用在於阻止鎢之擴散。阻隔層230係由依序沉積鈦(Ti)層及氮化鈦(TiN)層之膜層或一氮化鈦層所形成。
然後，如圖3所示，將運載至反應室內之半導體基板，在等於或大於330℃且等於或小於400℃之溫度下加熱，較佳地，等於或大於330℃且等於或小於360℃。將含鎢氣體、載氣、及至少乙硼烷(B2 H6 )氣體及矽甲烷(SiH4 )氣體其中之一導入反應室內。因此，在阻隔層230上形成一第一鎢層242。此時，同樣地在絕緣中間層200之表面上形成第一鎢層242。第一鎢層242具有例如等於或大於2nm且等於或小於10nm之厚度。將第一鎢層242同樣地形成在於孔洞221至225中所形成之阻隔層230上。例如，以六氟化鎢(WF6 )作為含鎢氣體，以例如氬氣(Ar)作為載氣，但載氣可包含氮氣。含鎢氣體及至少乙硼烷氣體及矽甲烷氣體其中之一可同時或交替地導入該反應室內。前者係例如一原子層沉積(ALD，atomic layer deposition)，後者較佳地包含在導入乙硼烷氣體及矽甲烷氣體至少其中一者之程序與導入含鎢氣體之程序之間施加沖洗氣體(例如，與載氣相同之氣體)之程序。
隨後，將氫氣氣體及惰性氣體至少其中之一導入該反應室內，然後以30秒以上之時間升高半導體基板100之溫度至等於或大於370℃且等於或小於410℃。例如，可利用如氬氣之稀有氣體及氮氣作為惰性氣體。使用在上述程序中之氣體，可與使用於將說明於後之第二鎢層240之形成程序中的氣體相同，該程序未排除含鎢氣體。溫度較佳地係以等於或大於0.5℃/秒且等於或小於2.5℃/秒的速率升高。升溫花費的時間較佳地係等於或大於40秒。
隨後，如圖4所示，將含鎢氣體、氫氣氣體及載氣導入該反應室內。因此，在該第一鎢層242之上形成該第二鎢層240。此時，將第二鎢層240同樣地形成在絕緣中間層200之表面上。該第二鎢層240具有例如等於或大於100nm且等於或小於400nm之厚度。同樣地在形成於孔洞221至225中之該第一鎢層242上形成第二鎢層240。例如，利用六氟化鎢作為含鎢氣體，以例如氬氣作為載氣，但載氣可含有氮氣。在載氣含有氮氣之情況下，第二鎢層240之表面變得平滑。
之後，如圖5所示，將該絕緣層200上之該第一鎢層242及該第二鎢層240之部分移除。此移除程序係使用回蝕技術或化學機械研磨技術(CMP，chemical mechanical polishing)而實施。因此，包含該第一鎢層242及該第二鎢層240之接觸栓塞被嵌入於孔洞221至225中。在此程序中，該絕緣層200上之該阻隔層233之一部分亦可被移除。
接下來，將說明本發明之效果。當第一鎢層242形成時之基板溫度係等於或大於330℃且等於或小於400℃，較佳為等於或大於330℃且等於或小於360℃。因此，增進了第一鎢層242對於孔洞221至225之階梯覆蓋能力，且因此增進了第二鎢層240之填充能力，藉以增進接觸栓塞之可靠度。如果基板溫度升高超過上述溫度，第一鎢層242對於孔洞221至225之階梯覆蓋能力變差，且因此第二鎢層240之填充能力變差。
當第二鎢層240形成時之基板溫度較當第一鎢層242形成時之基板溫度為高，且係等於或大於370℃且等於或小於410℃。
圖6係說明第二鎢層240之沉積速率取決於基板溫度之圖式。根據該圖式，當基板溫度為330℃時，第二鎢層240之沉積速率為50nm/分；當基板溫度為410℃及450℃時，第二鎢層240之沉積速率分別為285nm/分及500nm/分。因此，吾人瞭解如果在第二鎢層240沉積之前升高基板溫度，則沉積速率提升，藉以改善半導體裝置之生產率。
在形成該第二鎢層240之前及形成該第一鎢層242之後，將氫氣氣體及惰性氣體至少其中之一導入該反應室內，然後將該半導體基板之溫度以30秒以上之時間升高至等於或大於370℃且等於或小於410℃。因此，移除了被吸收至第一鎢層242內之氣體，故第二鎢層240之晶粒尺寸擴大，藉此降低了接觸栓塞之電阻。當在形成第一鎢層242之程序中使用除了乙硼烷氣體以外之矽甲烷氣體時，此效果特別顯著。
如上述，根據本發明之例示實施例，將形成第一鎢層242時之基板溫度設定在等於或大於330℃且等於或小於400℃；將形成第二鎢層240時之基板溫度設定在等於或大於370℃且等於或小於410℃；在形成該第二鎢層240之前及形成該第一鎢層242之後，將氫氣氣體及惰性氣體至少其中之一導入該反應室內；並以30秒以上之時間升高基板溫度。因此，可降低電阻同時改善接觸栓塞之可靠度，而可提升半導體裝置之生產率。
在圖2至5中，接觸栓塞被嵌入第一層之絕緣中間層中，然而當接觸栓塞形成於第二或更上層之絕緣中間層中時，可應用上述例示實施例中所揭露之技術。
[實施例]
以上述之本發明之例示實施例中所揭露之方法，製作根據實施例1至3之樣本。在各實施例中，當形成第一鎢層242時，將矽甲烷氣體、六氟化鎢氣體、及氬氣導入該反應室內，而將基板溫度設定在350℃。在此程序中，將矽甲烷氣體及六氟化鎢氣體交替導入共六次。此外，當形成第二鎢層240時，將氫氣氣體、六氟化鎢氣體、氮氣氣體、及氬氣導入該反應室內，而將基板溫度設定在390℃。當在形成該第一鎢層242之後形成該第二鎢層240之時，升高基板溫度。升高基板溫度之時間長度，在實施例1中設定為30秒，在實施例2中為40秒及在實施例3中為50秒。
此外，製作根據比較例1及2之樣本。比較例1及2之樣本之製作條件與實施例1至3相同，除了將基板之升高溫度之時間長度分別設定在8秒及20秒以外。
圖7A至7E為掃描式電子顯微鏡(SEM，scanning electron microscope)影像，其顯示根據該比較例1及2及該實施例1至3之樣本之橫剖面。此等照片顯示形成在絕緣中間層上之第一鎢層242及第二鎢層240。當圖7A及7B與圖7C至7E作比較時，吾人瞭解在該實施例1至3中之該第二鎢層240之晶粒尺寸較該比較例1至2中之該第二鎢層240之晶粒尺寸更大。此等趨勢在實施例2及3中特別顯著，換言之，當基板之升高溫度之時間長度為40秒以上時。
表1顯示該實施例1至3及該比較例1至2之製作條件、薄片電阻(sheet resistance)、層厚度、及比電阻。
在比較例1及2之樣本中，薄片電阻分別為0.538Ω/□及0.529Ω/□。另一方面，在實施例1至3之樣本中，薄片電阻分別為0.484Ω/□、0.459Ω/□、及0.452Ω/□。其顯示：實施例之樣本之薄片電阻比比較例之樣本低約等於或大於0.04Ω/□。
此外，在比較例1及2之樣本中，比電阻分別為15.6μΩ‧cm、13.9μΩ‧cm。另一方面，在實施例1至3之樣本中，比電阻分別為12.9μΩ‧cm、11.7μΩ‧cm、及11.4μΩ‧cm。其顯示實施例之樣本之比電阻比比較例之樣本低約等於或大於1μΩ‧cm。
在上文中，已參考圖式而闡述本發明之例示實施例，但此等僅為了說明之目的，而可採用上述之外之不同結構。
吾人應瞭解，本發明並不局限於上述實施例，而在不脫離本發明之範疇及精神下可修改及變化本發明。
100．．．半導體基板
102．．．隔離層
120．．．電晶體
122．．．矽化物層
124．．．矽化物層
126．．．矽化物層
140．．．電晶體
142．．．矽化物層
144．．．矽化物層
146．．．矽化物層
200．．．絕緣中間層
221．．．孔洞
222．．．孔洞
223．．．孔洞
224．．．孔洞
225．．．孔洞
230．．．阻隔層
240．．．第二鎢層
242．．．第一鎢層
S10．．．在絕緣層中形成孔洞
S20．．．將基板溫度設定在330℃至400℃
S30．．．形成第一鎢層
S40．．．基板溫度在30秒以上之期間升高至370℃至410℃
S50．．．形成第二鎢層
由結合了附圖之上列特定較佳實施例之敘述，本發明之上述及其他目的、優點及特徵將更清晰，其中：
圖1係說明根據本發明一例示實施例之半導體裝置之製造方法流程圖；
圖2係說明根據本發明一例示實施例之半導體裝置之製造方法橫剖面圖；
圖3係說明圖2之下一程序之橫剖面圖；
圖4係說明圖3之下一程序之橫剖面圖；
圖5係說明圖4之下一程序之橫剖面圖；
圖6係說明第二鎢層之層形成速率取決於基板溫度之圖表；
圖7A至7E係掃描式電子顯微鏡(SEM，scanning electron microscope)影像，其顯示根據比較例1及2及實施例1至3之樣本之橫剖面。
S10．．．在絕緣層中形成孔洞
S20．．．將基板溫度設定在330℃至400℃
S30．．．形成第一鎢層
S40．．．基板溫度在30秒以上之期間升高至370℃至410℃
S50．．．形成第二鎢層

Claims (6)

  1. 一種半導體裝置的製造方法，包含：在設置於一半導體基板之一表面上之一絕緣層中形成一孔洞；藉由將運載至反應室內之該半導體基板，在等於或大於330℃且等於或小於400℃之溫度下加熱，並將含鎢氣體、及至少乙硼烷(B2 H6 )氣體及矽甲烷(SiH4 )氣體其中之一導入該反應室內，而在該孔洞中形成一第一鎢層；將氫氣(H2 )氣體及惰性氣體至少其中之一導入該反應室內，及將該半導體基板之溫度以30秒以上之時間升高至等於或大於370℃且等於或小於410℃，其中該氫氣氣體及該惰性氣體皆未被激發為電漿；及藉由將含鎢氣體導入該反應室內，而在該第一鎢層上形成一第二鎢層。
  2. 根據申請專利範圍第1項之半導體裝置的製造方法，其中在該形成該第一鎢層的步驟中，將該半導體基板在等於或大於330℃且等於或小於360℃之溫度下加熱。
  3. 根據申請專利範圍第1項之半導體裝置的製造方法，其中在該半導體基板之溫度中，溫度升高速率係等於或大於0.5℃/秒且等於或小於2.5℃/秒。
  4. 根據申請專利範圍第1項之半導體裝置的製造方法，其中在該升高該半導體基板之溫度之步驟中，係花費40秒以上的時間升高該半導體基板之溫度。
  5. 根據申請專利範圍第1項之半導體裝置的製造方法，其中在該形成該第一鎢層的步驟及在該形成該第二鎢層的步驟中，將該第一鎢層及該第二鎢層同樣地形成於該絕緣層之表面上，及在形成該第二鎢層之後，實施一用以移除該絕緣層之表面上之該第一鎢層及該第二鎢層之部分的步驟。
  6. 根據申請專利範圍第1項之半導體裝置的製造方法， 其中在該形成該第一鎢層的步驟中，將矽甲烷(SiH4 )氣體及含鎢氣體導入該反應室內。
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