TWI381499B - 具有增強型散熱特性之半導體封裝結構 - Google Patents

具有增強型散熱特性之半導體封裝結構 Download PDF

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TWI381499B
TWI381499B TW094137199A TW94137199A TWI381499B TW I381499 B TWI381499 B TW I381499B TW 094137199 A TW094137199 A TW 094137199A TW 94137199 A TW94137199 A TW 94137199A TW I381499 B TWI381499 B TW I381499B
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package
attachment structure
stepped
electronic
electrode
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TW094137199A
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English (en)
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TW200633170A (en
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卡尼 法蘭西斯Ｊ
塞頓 麥可Ｊ
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半導體組件工業公司
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Description

具有增強型散熱特性之半導體封裝結構
本發明一般有關半導體裝置封裝，尤其有關裝在具有改良之熱傳送特性之封裝中的半導體組件。
對於具有較高功能性與較小實體尺寸之電子系統的需求向來持續不減。為此需求，讓電子組件設計者與製造業者面臨若干挑戰。此類挑戰包括管理功率半導體裝置所產生的熱，通常在電子電路板上將這些裝置緊密地配置一起或緊鄰靈敏的邏輯電路。
在電流組態中，一般使用塑膠封裝之裝置。塑膠封裝的一個問題是封裝的導熱率通常受限於塑膠模製材料。因此，大部分由半導體裝置所產生的熱透過緊鄰印刷電路板之封裝的下方部分來傳送。由於印刷電路板的零組件設置越來越密集，於是電路板對於大量的熱無法妥善進行散熱或加以處理。當無法有效散熱時，電路板將會扭曲，因而造成電路板與電路板上的組件損壞。此外，熱本身將損壞印刷電路板上的其他組件或製成電路板的材料。
有鑑於此問題，半導體業界轉而生產具有透過封裝的頂部(取代透過印刷電路板)將熱傳送出去之能力的封裝。此類封裝亦包括附著於封裝頂部的散熱器，以進一步協助熱傳送。
一個此類封裝是如國際整流器公司(International Rectifier Corporation)於2002年1月之Board Mounting Application Note AN- 1035(電路黏著應用註解AN-1035)中所示的DirectFETTM 封裝，其標題為「DirectFETTM Technology(DirectFETTM 技術)」。在此設計中，由於已知塑膠模製化合物的熱傳送特性不佳而將其完全去除。
此設計有若干缺點。首先，由於封裝不使用模製化合物，使半導體未受到保護，因而更容易受到損壞或污染。還有，此設計利用非標準的製造技術，不但增加製造的週期時間，且增加了製造成本。此外，在特定應用中，此設計將主載流電極(如，源極電極)置於向下方向或緊鄰印刷電路板，因而降低熱傳送能力。在其他應用中，此設計將主載流電極置於向上方向或遠離印刷電路板，但卻直接接觸未鈍化的散熱器，因而在操作時有安全之虞。
因此，需要具有增強型散熱特性且有利於裝置可靠性、安全性、製造週期時間及成本的半導體封裝。
本專利申請案有關一種半導體封裝，其包含：一具有一旗標部分及一襯墊部分的導電基板；一耦合至該旗標部分的電子晶片，其中該電子晶片包括在該旗標部分對面之一表面上的一主載流電極；一耦合該主載流電極至該襯墊部分的附接結構；及一具有大於或等於約3.0 Watts/mK之一導熱率的封裝層，其中該封裝層覆蓋該電子晶片及該波浪形附接結構的至少一部分。
為了便於瞭解，圖式中的元件未必按比例繪製，及所有不同圖式中視需要使用相同的元件。雖然本發明使用QFN/DFN具體實施例進行說明，但熟習本技術者應明白，本發明一樣適用於其他類型的封裝，尤其是對增強型熱傳送特性很重要的封裝。
圖1顯示本發明具有增強型散熱或熱傳送特性之封裝半導體結構、QFN/DFN封裝、無引線封裝裝置或封裝10的放大橫截面圖。封裝裝置10包括導電基板或引線框架11，其包括旗標、薄板、或晶粒附著部分13及引線、終端、連接、或襯墊部分14。引線框架11包含如：銅、銅合金(如，TOMAC 4、TAMAC 5、2ZFROFC或CDA194)、鍍銅的鐵/鎳合金(如，鍍銅合金42)、電鍍鋁、電鍍塑膠或其類似物。電鍍材料包括：銅、銀、鎳-鈀的多層電鍍及金。旗標部分13與襯墊部分14係用來連接或耦合至如印刷電路板之下一級裝配件的焊墊。
封裝10進一步包括電子晶片或半導體裝置17，其係使用晶粒附著層19附著至旗標13。半導體裝置17包含如：功率MOSFET裝置、雙極電晶體、絕緣閘極雙極電晶體、閘流體、二極體、類比或數位積體電路、感測器、被動組件或其他電子裝置。在一項示範性具體實施例中，半導體裝置17包含功率MOSFET裝置，其包括：源極、向上源極、或主載流電極21，汲極、向下汲極、或載流電極23，及閘極或控制電極26(如圖6所示)。源極電極21包含如可焊接的頂部金屬、鋁、鋁合金或其類似物。汲極電極23通常包含可 焊接的金屬層，如TiNiAg、CrNiAu或其類似物。根據本發明，半導體晶片17係在主載流電極或源極電極之「向上」組態中。也就是說，將半導體晶片17的主發熱電極(如，電極21)定位在遠離將附著於下一級裝配件之封裝10的側面或在其對面。此定位促進從封裝10之頂面28的熱傳送，而非透過下一級裝配件或透過晶片本身進行熱傳送。
附接結構、波浪形、階梯式、或非平面附接結構或導電夾或導電帶31係耦合至源極電極21及襯墊部分14，以在半導體晶片17及襯墊部分14之間提供電路徑。導電夾31包含如：剛性銅或銅合金，並可視情況在焊劑附件或導電環氧附件上鍍銀。在所示的具體實施例中且根據本發明，導電夾31較佳是波浪形、階梯式或非平面，致使導電夾31的部分比較接近封裝10的頂面28而不接觸半導體晶片17。這和平坦或平面導電夾相比，提供減少的熱阻路徑，以改良傳導熱傳送遠離半導體晶片17。較佳是，導電夾31之至少約50%的表面積接觸電極21，及剩餘的表面積是導電夾31遠離電極21的波浪形或階梯式部分。較佳是，導電夾31具有至少2個梯級。將結合圖6與7來顯示及說明控制電極26的選擇性附件或互連方案。
使用單一腔室或過度模製程序在引線框架11、半導體晶片17、及導電夾31的至少部分之上形成封裝或鈍化層29。根據本發明，封裝層29包含高導熱率模製化合物。較佳是，封裝層29包含具有導熱率大於約3.0 Watts/MK的模製化合物。合適的高導熱率模製化合物可從加州聖塔克拉拉 的Sumitomo Plastics America(如，EME A700系列)與加州聖塔克拉拉的Hitachi Chemical(如，CEL 9000系列模製化合物)購得。
較佳是，封裝10具有小於約1.10毫米的總高度34。在較佳具體實施例中，高度34小於約0.80毫米。另外，在半導體晶片17上之封裝層29的厚度小於約0.53毫米。這些尺寸連同波浪形導電夾31、主載流電極21的定位及高導熱率模製化合物提供增強型熱傳送效應。尤其，評估可比較尺寸之封裝10和DirectFETTM 產品的熱研究顯示，本發明以具有導熱率大於或等於約3.0 Watts/mK及高度34小於約0.80毫米之模製化合物裝配的封裝10具有相等或更佳的熱阻(接合至封裝的頂部)特性。
顯示波浪形導電夾31具有一或多個選擇性模製鎖特色或刻痕39，其係用來在封裝層29及導電夾31之間提供更好的黏著性。可使用更多或更少的刻痕39。另外，封裝10包括選擇性散熱器裝置43，其係利用以下材料而附著於封裝10：如高導電率環氧材料42，如可從Hitachi Chemical購得的CEL9750 HFLO(AL3)或CEL9210 HFLO(AL2)環氧，或可從Sumitomo Plastics America購得的EMF 760a環氧。應明白，散熱器43是所述所有封裝具體實施例的選項，包括如以下圖2-5所示的具體實施例。在顧及安全性的應用中，視情況以如導熱膠的絕緣材料塗布散熱器43。
圖2顯示本發明第二具體實施例之封裝半導體結構、QFN/DFN封裝、無引線之封裝裝置、或封裝100的放大橫 截面圖。封裝100同於封裝10，但使用波浪形或非平面附接結構或帶狀黏接231取代波浪形導電夾31將半導體晶片17的主載流電極21耦合至襯墊部分14。
帶狀黏接231是指彈性矩形的導體，其中帶狀黏接231的寬度51(如圖7所示)大於帶狀黏接231的厚度52。帶狀黏接231的合適材料包括金、鋁、銀、鈀、銅或其類似物。帶狀黏接231的附件通常包括源極電極21的超音波楔形黏接端232、及襯墊部分14的楔形黏接端233。在一項具體實施例中，形成具有約25微米之厚度及約75微米之寬度的帶狀黏接231。或者，通常形成帶狀黏接231為約6微米至50微米的厚度52及約50微米至1500微米寬的寬度52。圖1與2之具體實施例的一個優點在於封裝10與100的頂側為電絕緣，因而避免和先前技術結構相關聯的安全顧慮。
圖3顯示本發明第三具體實施例之封裝半導體結構、QFN/DFN封裝、無引線之封裝裝置、或封裝110的放大橫截面圖。封裝110同於封裝10，但在封裝110中，封裝層129僅覆蓋波浪形導電夾31的一部分。也就是說，在封裝110中，將導電夾31的部分310保持曝露，以進一步增強封裝的熱傳送特性，而半導體晶片17仍為封裝層129所覆蓋或鈍化。在此具體實施例中，封裝層較佳是包含同於封裝層29的材料。
圖4顯示本發明另一具體實施例之封裝半導體結構、QFN/DFN封裝、無引線之封裝裝置或封裝200的放大橫截面圖。封裝200同於封裝100，但在封裝200中，封裝層229 僅覆蓋附接結構或帶狀黏接231的一部分。也就是說，在封裝200中，將帶狀黏接231的部分331保持曝露，以進一步增強封裝的熱傳送特性，而半導體晶片17仍為封裝層129所覆蓋或鈍化。在此具體實施例中，封裝層229較佳是包含同於封裝層29的材料。
在形成封裝110與200的較佳方法中，在形成附接結構31與231後，將裝配件置於模製設備中，致使部分310與331接觸或靠近模製腔室的表面。模製腔室的表面當作防止封裝材料129與229覆蓋部分310與331的遮罩。
圖5顯示本發明其他具體實施例之封裝半導體結構、QFN/DFN封裝、無引線之封裝裝置或封裝210的放大橫截面圖。封裝210同於封裝100，但在封裝210中，使用具有Ω或實質上Ω狀形狀的波浪形或非平面附接結構或帶狀黏接431。也就是說，帶狀黏接431在半導體晶片17之上包括基座部分432與上方部分433，其中基座部分432具有之寬度小於上方部分433的寬度。Ω形帶狀黏接431提供具有更多傳導表面積的波浪形附接結構，以提供具有增強型熱傳送特性的封裝。在替代性具體實施例中，同於如圖3與4所示的封裝曝露Ω形帶狀黏接431的部分。
圖6-9顯示在封裝步驟之前搭配本發明使用之不同附接結構方案的具體實施例。圖6除了顯示圖1的引線框架11與半導體晶片17，還有將半導體晶片17之控制電極26(如段落[0019]所提)耦合至襯墊部分114的控制電極附接結構61。在此具體實施例中，控制電極附接結構61包含帶狀黏 接。一般而言，選擇控制電極26的面積約為帶狀黏接之寬度與厚度的三倍。帶狀黏接61的一個優點是，和線路黏接所需的接觸面積相比，帶狀黏接面積較小，且不會損及可製造性、可靠性或強度。
圖7除了顯示圖2的引線框架11與半導體晶片17，還有如結合圖6所述的帶狀黏接61。圖7進一步顯示複數個或多個帶狀黏接231，且包括如段落[0025]所提的寬度51。
圖8除了顯示圖1的引線框架11與半導體晶片17，還有線路黏接71，其為將半導體晶片17之控制電極226耦合至引線框架11之襯墊部分114的附接結構。在此具體實施例中，控制電極226包含適於線路黏接的金屬，如鋁或鋁合金。線路黏接71係使用習用的線路黏接技術來形成且包含如鋁或金。在較佳的具體實施例中，線路黏接71具有小於波浪形導電夾31之高度的迴路高度，以免曝露圖3之具體實施例中的線路黏接71。
圖9除了顯示圖2的引線框架11與半導體晶片17，還有將半導體晶片17之控制電極226耦合至引線框架11之襯墊部分114的線路黏接71。在此具體實施例中，控制電極226包含適於線路黏接的金屬，如鋁或鋁合金。線路黏接71係使用習用的線路黏接技術來形成且包含如鋁或金。在較佳的具體實施例中，線路黏接71具有小於帶狀黏接231之高度的迴路高度，以免曝露圖4之具體實施例中的線路黏接71。
到目前為止，應明白，已說明具有增強型散熱或熱傳送特性的半導體封裝結構。此封裝包括定位致使發熱或主載流電極遠離封裝預定附著於下一級裝配件之側面的電子晶片。此透過封裝的頂部提供改良的熱路徑。此封裝進一步包括將附接結構之部分置放較接近封裝之頂部的波浪形附接結構，以進一步減少熱阻路徑。此外，此封裝併入高導熱率模製化合物(大於約3.0 W/mK)與薄外型(小於約1.10毫米)以進一步增強散熱。在替代性具體實施例中，曝露波浪形附接結構的部分以進一步增強散熱。在附加的具體實施例中，波浪形附接結構具有Ω狀形狀，以提供用於熱傳送之更能傳導的表面積。還有，在進一步的具體實施例中，在封裝的頂部增加散熱器裝置以進一步增強散熱。
10,100,110,200,210‧‧‧封裝
11‧‧‧引線框架
13‧‧‧旗標部分
14‧‧‧襯墊部分
17‧‧‧半導體裝置
19‧‧‧晶粒附著層
21‧‧‧源極電極
23‧‧‧汲極電極
26,226‧‧‧控制電極
28‧‧‧頂面
29,129,229‧‧‧封裝層
31‧‧‧導電夾
34‧‧‧高度
39‧‧‧刻痕
42‧‧‧鍍銅合金
43‧‧‧散熱器
51‧‧‧寬度
52‧‧‧厚度
61‧‧‧控制電極附接結構
71‧‧‧線路黏接
114‧‧‧襯墊部分
231,431‧‧‧帶狀黏接的部分
232,233‧‧‧楔形黏接端
310‧‧‧導電夾的部分
331‧‧‧帶狀黏接的部分
432‧‧‧基座部分
433‧‧‧上方部分
圖1顯示本發明具體實施例之封裝結構的放大橫截面圖；圖2顯示本發明第二具體實施例之封裝結構的放大橫截面圖；圖3顯示本發明第三具體實施例之封裝結構的放大橫截面圖；圖4顯示本發明第四具體實施例之封裝結構的放大橫截面圖；圖5顯示本發明第五具體實施例之封裝結構的放大橫截面圖；圖6顯示圖1與4之封裝結構之互連方案的具體實施例； 圖7顯示圖1與4之封裝結構之互連方案的另一項具體實施例；圖8顯示圖2與3之封裝結構之互連方案的具體實施例；及圖9顯示圖2與3之封裝結構之互連方案的另一項具體實施例。
10‧‧‧封裝
11‧‧‧引線框架
13‧‧‧旗標部分
14‧‧‧襯墊部分
17‧‧‧半導體裝置
19‧‧‧晶粒附著層
21‧‧‧源極電極
23‧‧‧汲極電極
28‧‧‧頂面
29‧‧‧封裝層
31‧‧‧導電夾
34‧‧‧高度
39‧‧‧刻痕
42‧‧‧鍍銅合金
43‧‧‧散熱器

Claims (25)

  1. 一種半導體封裝，其包含：一具有一旗標部分及一襯墊部分的導電基板；一耦合至該旗標部分的電子晶片，其中該電子晶片包括在該旗標部分對面之一表面上的一主載流電極；將該主載流電極耦合至該襯墊部分的一附接結構；及一具有大於或等於約3.0 Watts/mK之一導熱率的封裝層，其中該封裝層覆蓋該電子晶片及覆蓋該附接結構之一部分。
  2. 如請求項1之封裝，其中該附接結構包含一階梯式導電夾。
  3. 如請求項1之封裝，其中該附接結構包含一波浪型附接結構，其中該波浪型附接結構具有至少一階梯，其覆蓋該電子晶片之該表面且不延伸至該電子晶片之一邊緣上。
  4. 如請求項2之封裝，其中該階梯式導電夾具有至少兩個梯級。
  5. 如請求項1之封裝，其中該附接結構包含一波浪形帶狀黏接。
  6. 如請求項5之封裝，其中該波浪形帶狀黏接具有一實質上Ω狀形狀。
  7. 如請求項1之封裝，其中該封裝具有高度小於約1.10毫米。
  8. 如請求項1之封裝，其中該電子晶片進一步包括一控制 電極，及其中該導電基板進一步包括一第二襯墊部分，及其中一第二附接結構將該控制電極耦合至該第二襯墊部分。
  9. 如請求項8之封裝，其中該第二附接結構包括一帶狀黏接。
  10. 如請求項8之封裝，其中該第二附接結構包括一線路黏接。
  11. 如請求項1之封裝，其中該附接結構包括一模製鎖。
  12. 如請求項1之封裝，其進一步包含一附著於該半導體封裝之上表面的散熱器。
  13. 一種具有增強型散熱之無引線的半導體封裝，其包含：一包括一終端部分的引線框架；一在一表面上具有一第一電極的半導體裝置；一耦合至該第一電極及該終端部分的階梯式附接結構；及一鈍化層，其覆蓋該半導體裝置及覆蓋該階梯式附接結構之一部分。
  14. 如請求項13之無引線的半導體封裝，其中該階梯式附接結構包含一具有至少兩個梯級的階梯式導電夾。
  15. 如請求項13之無引線的半導體封裝，其中該階梯式附接結構包含一波浪形帶狀黏接。
  16. 如請求項13之無引線的半導體封裝，其中該階梯式附接結構具有至少一階梯，其覆蓋該半導體裝置之一主表面且不延伸至該半導體裝置之一邊緣上。
  17. 如請求項13之無引線的半導體封裝，其中該階梯式附接結構之部分具有實質上Ω狀之形狀。
  18. 如請求項13之無引線的半導體封裝，其中該鈍化層包含一具有一導熱率大於或等於約3.0 Watts/mK的材料。
  19. 一種電子封裝，其包含：一具有一主載流電極的半導體晶粒；一耦合至該主載流電極的階梯式附接結構；及一封裝層，其覆蓋該半導體晶粒之至少一部分且留下該階梯式附接結構之一部分為曝露。
  20. 如請求項19之電子封裝，其中該階梯式附接結構包含一階梯式導電夾。
  21. 如請求項19之電子封裝，其中該階梯式附接結構包含一波浪形帶狀黏接。
  22. 如請求項19之電子封裝，其中該半導體晶粒進一步包括一控制電極及一附著於該控制電極中的第二附接結構。
  23. 如請求項22之電子封裝，其中該第二附接結構包含一帶狀黏接。
  24. 如請求項22之電子封裝，其中該第二附接結構包含一線路黏接。
  25. 如請求項19之電子封裝，其中該封裝層包含一具有一導熱率大於或等於約3.0 Watts/mK的材料。
TW094137199A 2004-12-20 2005-10-24 具有增強型散熱特性之半導體封裝結構 TWI381499B (zh)

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