TWI369687B - Multi-wordline test control circuit and controlling method thereof - Google Patents

Multi-wordline test control circuit and controlling method thereof

Info

Publication number
TWI369687B
TWI369687B TW097105454A TW97105454A TWI369687B TW I369687 B TWI369687 B TW I369687B TW 097105454 A TW097105454 A TW 097105454A TW 97105454 A TW97105454 A TW 97105454A TW I369687 B TWI369687 B TW I369687B
Authority
TW
Taiwan
Prior art keywords
control circuit
controlling method
test control
wordline test
wordline
Prior art date
Application number
TW097105454A
Other languages
English (en)
Other versions
TW200845018A (en
Inventor
Hi-Hyun Han
Jee-Yul Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200845018A publication Critical patent/TW200845018A/zh
Application granted granted Critical
Publication of TWI369687B publication Critical patent/TWI369687B/zh

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C2029/1202—Word line control
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test
TW097105454A 2007-05-11 2008-02-15 Multi-wordline test control circuit and controlling method thereof TWI369687B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020070046228A KR100878307B1 (ko) 2007-05-11 2007-05-11 멀티 워드라인 테스트 제어 회로 및 그의 제어 방법

Publications (2)

Publication Number Publication Date
TW200845018A TW200845018A (en) 2008-11-16
TWI369687B true TWI369687B (en) 2012-08-01

Family

ID=39969380

Family Applications (1)

Application Number Title Priority Date Filing Date
TW097105454A TWI369687B (en) 2007-05-11 2008-02-15 Multi-wordline test control circuit and controlling method thereof

Country Status (3)

Country Link
US (1) US7626875B2 (zh)
KR (1) KR100878307B1 (zh)
TW (1) TWI369687B (zh)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR101188261B1 (ko) 2010-07-30 2012-10-05 에스케이하이닉스 주식회사 멀티 비트 테스트 회로
KR102017182B1 (ko) * 2012-08-30 2019-09-02 에스케이하이닉스 주식회사 반도체 메모리 장치
KR20140082173A (ko) * 2012-12-24 2014-07-02 에스케이하이닉스 주식회사 어드레스 카운팅 회로 및 이를 이용한 반도체 장치
KR20160029378A (ko) * 2014-09-05 2016-03-15 에스케이하이닉스 주식회사 반도체 장치
KR102485210B1 (ko) * 2016-08-18 2023-01-06 에스케이하이닉스 주식회사 반도체 메모리 장치
KR20180058060A (ko) 2016-11-23 2018-05-31 에스케이하이닉스 주식회사 피크 커런트 분산이 가능한 상변화 메모리 장치
KR20180124568A (ko) * 2017-05-12 2018-11-21 에스케이하이닉스 주식회사 리페어 회로 및 이를 포함하는 메모리 장치
US11605419B2 (en) * 2021-06-30 2023-03-14 Micron Technology, Inc. Semiconductor device having a test circuit

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06176598A (ja) * 1992-12-07 1994-06-24 Nec Corp ダイナミック型半導体メモリ回路
US5864565A (en) * 1993-06-15 1999-01-26 Micron Technology, Inc. Semiconductor integrated circuit having compression circuitry for compressing test data, and the test system and method for utilizing the semiconductor integrated circuit
KR980005059A (ko) * 1996-06-29 1998-03-30 김주용 반도체 메모리장치의 테스트회로
JP2921505B2 (ja) * 1996-08-09 1999-07-19 日本電気株式会社 半導体記憶装置
KR100303923B1 (ko) * 1998-05-25 2001-11-22 박종섭 싱크로너스디램에서의멀티뱅크테스트장치
US6023434A (en) * 1998-09-02 2000-02-08 Micron Technology, Inc. Method and apparatus for multiple row activation in memory devices
KR100334532B1 (ko) * 1999-04-03 2002-05-02 박종섭 워드라인 구동장치
JP3754600B2 (ja) * 2000-06-13 2006-03-15 シャープ株式会社 不揮発性半導体記憶装置およびそのテスト方法
KR100338776B1 (ko) * 2000-07-11 2002-05-31 윤종용 멀티 로우 어드레스 테스트 가능한 반도체 메모리 장치 및그 테스트 방법
ITRM20010104A1 (it) * 2001-02-27 2002-08-27 Micron Technology Inc Modo di lettura a compressione di dati per il collaudo di memorie.
US7139943B2 (en) * 2002-03-29 2006-11-21 Infineon Technologies Ag Method and apparatus for providing adjustable latency for test mode compression
KR100474510B1 (ko) * 2002-05-07 2005-03-08 주식회사 하이닉스반도체 플래시 메모리 소자의 테스트 회로
CN100592420C (zh) * 2004-08-05 2010-02-24 富士通微电子株式会社 半导体存储器
KR100551430B1 (ko) * 2004-08-11 2006-02-09 주식회사 하이닉스반도체 반도체 메모리 장치
KR100694418B1 (ko) * 2004-11-15 2007-03-12 주식회사 하이닉스반도체 메모리 장치의 병렬 압축 테스트 회로
KR100861364B1 (ko) * 2006-12-29 2008-10-01 주식회사 하이닉스반도체 반도체 메모리 소자의 워드라인 테스트 모드 회로

Also Published As

Publication number Publication date
KR20080100098A (ko) 2008-11-14
KR100878307B1 (ko) 2009-01-14
US7626875B2 (en) 2009-12-01
US20080279021A1 (en) 2008-11-13
TW200845018A (en) 2008-11-16

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