TWI363411B - Embedded chip substrate and fabrication method thereof - Google Patents

Embedded chip substrate and fabrication method thereof Download PDF

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Publication number
TWI363411B
TWI363411B TW097127864A TW97127864A TWI363411B TW I363411 B TWI363411 B TW I363411B TW 097127864 A TW097127864 A TW 097127864A TW 97127864 A TW97127864 A TW 97127864A TW I363411 B TWI363411 B TW I363411B
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TW
Taiwan
Prior art keywords
layer
insulating layer
wafer
core
wafer substrate
Prior art date
Application number
TW097127864A
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English (en)
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TW201005892A (en
Inventor
Yung Hui Wang
Ying Te Ou
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Advanced Semiconductor Eng
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Application filed by Advanced Semiconductor Eng filed Critical Advanced Semiconductor Eng
Priority to TW097127864A priority Critical patent/TWI363411B/zh
Priority to US12/500,841 priority patent/US20100018761A1/en
Publication of TW201005892A publication Critical patent/TW201005892A/zh
Application granted granted Critical
Publication of TWI363411B publication Critical patent/TWI363411B/zh
Priority to US13/564,421 priority patent/US9253887B2/en
Priority to US14/990,425 priority patent/US9768103B2/en

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    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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Description

1363411 ASEK2106-NEW-final-TW-20080722 九、發明說明： 【發明所屬之技術領域】 本發明是有關於一種基板及复制左 關於一種内埋晶片基板及其製作^法。法，且特別是有 【先前技術】 近年來，隨著電子技術的日新月異， 功能更佳的電子產品不斷地推陳^
承载許多電子元件。由於電子元件崎=板以 當電子元件的數量較多時 增加線路板的承载面積财載這㈣子元件。 ，的面積也勢必隨之增加，而這不利於電子產品的小塑 化。此外，晶片封裝用的線路板亦有類似問題。 【發明内容】
本發明提出-種内埋晶片基板，其晶片不佔用其線路 板的承載面積。 本發明另提出一種内埋晶片基板的製作方法，其所製 得的内埋晶片基板的晶片不會佔用線路板的承載面積。 本發明提出一種内埋晶片基板包括一第—絕緣層、一 核心層、一晶片、一第二絕緣層、一第一線路層以及一第 二線路層。核心層配置於第一絕緣層上，並具有一開口， 以暴露出部分第一絕緣層。晶片固著於由開口與第一絕緣 層所構成的一凹槽中。第二絕緣層配置於核心層上，以覆 蓋晶片。第一線路層配置於第一絕緣層的外側，且第一絕 5 1363411 ASEK21 〇6-NEW-final-TW-20080722 緣層位於第一線路層與核心層之間。第二線路層配置於第 二絕緣層的外侧，第二絕緣層位於第二線路層與核心層之 間’第一線路層與第二線路層電性連接，且第二線路層與 晶片電性連接。 在本發明之一實施例中，第—絕緣層的材質包括二階 段固化膠體（two-stage curable compound )。 在本發明之一實施例中，第二絕緣層的材質包括二階 段固化膠體。 在本發明之一實施例中，内埋晶片基板更包括一底部 黏著層，其配置於凹槽内的第一絕緣層上，並位於晶片與 第一絕緣層之間。 在本發明之一實施例中，内埋晶片基板更包括一側壁 黏膠層，其配置於凹槽的内侧壁（innersidew 的側壁之間。 〃 在本發明之一實施例中，内埋晶片基板更包括一側壁 黏膠層，其配置於凹槽的内侧壁與晶片的側壁之間。 在本發明之-貫施例中’第—絕緣層延伸至凹槽的内 側壁與晶片的側壁之間。 在本發明之-實施例巾基板更包括多個導 電目孔，其貫穿第二絕緣層並電性連接第二線路層鱼晶片。 在本發明之-實施射，内埋晶片基板更包括多個導 、貝孔’其貫穿第二絕緣層、核心層與第—絕緣層，並電 性連接第一線路層與第二線袼層。 在本發明之-實施例中，核心層包括一核心介電層與 6 1363411 ASEK2106-NEW-final-TW-20080722 二核心線路層，這些核心線路層分別配置於核心層的相對 兩側。 在本發明之一實施例中’内埋晶片基板更包括二增層 結構（build-up structure)，其分別配置於第二絕緣層與第 一絕緣層的外側，並分別具有多個銲墊於其外側。 在本發明之一實施例中’内埋晶片基板更包括二銲罩 層，其分別配置於增層結構的外側，並分別暴露出對應的 銲塾。 本發明提出一種内埋晶片基板的製作方法如下所 述。首先，提供一核心層，其具有一開口。接著，提供一 第一絕緣層與一第一導電層，第一導電層配置於第一絕緣 層上。然後，將核心層配置於第一絕緣層上，且第—絕緣 層位於核心層與第一導電層之間。之後，將一晶片固】於 由開口與第一絕緣層所構成的一凹槽中。接著，提供一第 二絕緣層與一第二導電層，且第二導電層配置於第二絕緣 層上。然後，將第二絕緣層配置於核心層上，且第二絕緣 層位於核心層與第二導電層之間，且蓋住凹槽。之後，壓 合第一導電層、第一絕緣層、核心層、第二絕緣層與第二 導電層。然後，分別圖案化第一導電層與第二導: 形成一第一線路層與一第二線路層，其中第一線路^與 二線路層電性連接，且第二線路層與晶片電性連接:一 在本發明之一實施例中，内埋晶片基板的製作方法 包括在圖案化第—導電層之前，喊多個貫穿第二 的導電盲孔，以電性連接晶片與第二導電層。 " 7 ASEK2106-NEW-final-TW-20080722 在本發明之一實施例中，内埋晶片基板的製作方法更 包括在圖案化第一導電層與弟·一導電層之後’形成多個貫 穿弟二絕緣層、核心層、第一絕緣層的導電貫孔，以電性 連接第一線路層與第二線路層。 在本發明之一實施例中，内埋晶片基板的製作方法更 包括在壓合第一導電層、第一絕緣層、核心層、第二絕緣 層與第二導電層的過程中，加熱第一絕緣層，以使其溢流 至晶片的侧壁與凹槽的内側壁之間。 在本發明之一實施例中，將晶片固著於凹槽中的方法 包括將一底部黏著層配置於凹槽内的第一絕緣層上，並將 晶片配置於底部黏著層上。 在本發明之一實施例中’將晶片固著於凹槽中的方法 更包括形成—侧壁黏膠層於凹槽的内側壁與晶片的側壁之 間。 在本發明之一實施例中，將晶片固著於凹槽中的方法 包括形成一側壁黏膠層於凹槽的内側壁與晶片的側壁之 間。 在本發明之一實施例中，内埋晶片基板的製作方法更 包括在第一絕緣層與第二絕緣層的外側各自形成一增層結 構’且增層結構分別具有多個銲墊於其外側。 在本發明之—實施例中，内埋晶片基板的製作方法更 I括在增層結構上各自形成-防焊層，以暴露出對應的銲 墊。 ， 在本么明之—實施例中，第一絕緣層的材質包括二階 1363411 ASEK21 〇6-NEW-final-T W-20080722 段固化膠體。 在本發明之一實施例中，第二絕緣層的材質包括二階 段固化膠體。 承上所述，在本發明中，晶片是内埋於線路板内，故 晶片不會佔據線路板上的承載面積。 為讓本發明之上述和其他特徵和優點能更明顯易 菫，下文特舉實施例，並配合所附圖式，作詳細說明如下。
【實施方式】 圖1A一〜圖1L綠示本發明—實施例之内埋晶片基板的 t程剖面示意圖。圖2A與圖2B繪示本發明另-實施例之 ^埋晶片基板的製程剖面示意圖。圖3繪示本發明又一實 轭例之内埋晶片基板的製程剖面示意圖。
緣 、、人首先’凊參照® U，提供—核^層1G，其具有一核 2電層12與分難於核心介電層12之減兩側的二導 ^ 14。核心介電層12可以是-絕緣板。此外，在其他 2示的實關中’可以—多層板取代本實關之核心介 ^ I2’夕層板可具有交錯㈣的多層線路層與多層絕 然後’請參照圖1B，分別圖案化二導電層14，以形 f二核心線路層14a。接著，請參關1C，在核心層10 ^形成—開口 16 ’而形成開Π 16的方法包括外型加工 (_ting)，例如機械鑽孔drimng)、衝孔 (punch)或是其他適合的加工方法。 之後，凊參照圖1D，提供一第一絕緣層11〇與一第 9 1363411 ASEK2106-NEW-fmal-T W-20080722 一導電層120,第一導電層i2〇配置於第一絕緣層11〇上， 且第一絕緣層110的材質例如是二階段固化膠體。於本實 施例中，可採用一背膠銅箔（resin coated copper，RCC) 作為第一絕緣層110與第一導電層120。然後，將核心層 10配置於第一絕緣層110上，而第一絕緣層11〇位於核心 層10與第-導電層120之間，且開口 16與第一絕緣層11〇 構成一凹槽R。 之後，凊參照圖1E，將一晶片13〇固著凹槽R中。 在本實施例中，將晶片130固著於凹槽R中的方法是藉由 一配置在第一絕緣層110上的底部黏著層142，將晶片;3〇 固著在第-絕緣層110上，並藉由形成在凹槽R的内側壁 與晶片130的侧壁之間的一側壁黏膠層144，將晶片^0 固著於凹槽II的内側壁。此外，在其他實施例中，將晶 130固著於凹槽R中的方法也可以是僅藉由底部黏=屛 142 (請參照圖2A)或側壁黏膠層144 (請參照圖二 晶片130。 另外，底部黏著層142的材質例如是聚亞醯 (polyimide，ΡΙ)或是其他適合的黏著材料。側壁黏膠 144的材質例如是環氧樹脂（ep〇xy resin)或是其他八二 黏著材料。 〇的 然後，請參照圖1F，提供一第二絕緣層15〇與一第一 導電層160’且第一導電層160配置於第二絕緣層上 在本實施例中，可採用一背膠銅箔（RCC)作為第二絕 層150與第二導電層160。然後，將第二絕緣層15〇配罟 1363411 ASEK2 l〇6-NEW-final-TW-2〇〇80722 » 於核心層10上，第二絕緣層150位於核心層10與第二導 電層160之間’且蓋住凹槽r。 之後，請參照圖1G，壓合第一導電層120、第一絕緣 層110、核心層1〇、第二絕緣層15〇與第二導電層16〇。 而且’在壓合的過程中，還可加熱第一絕緣層u〇。由於 第一絕緣層110的材質可為二階段固化膠體，所以部分的 第一絕緣層110溢流至晶片130的側壁與凹槽R的内侧壁 之間。 如此一來，可避免在晶片130的侧壁與凹槽R的内側 壁之間殘留有空隙及水氣，而造成爆米花效應（p〇pc〇m effect)。而且，第二絕緣層15〇的材質亦可包括二階段固 • 化膠體，以利於填滿晶片130的側壁與凹槽R的内側壁之 間的空隙。 +於其他實施例中，當晶片130僅藉由底部黏著層142 固著於凹槽R内（請參照圖2A)時，壓合第一導電層12〇、 第一絕緣層110、核心層1〇、第二絕緣層15〇與第二導電 _ 層160並加熱第一絕緣層U0可使部分的第一絕緣層11〇 填滿晶片130的侧壁與凹槽R的内側壁之間的空隙（請參 照圖2B)。如此一來，則不需在晶片130的側壁與凹槽R 的内侧壁之間的空隙另外塞入填充物以防止爆米花效應。 然後，請參照圖1H，為了電性連接晶片13〇與第二 導電層160,本實施例形成多個貫穿第二絕緣層15〇、的導 電盲孔B。然後，請參照圖u，分別圖案 與第二導電層_，以形成-第—線路層H電第層二線 11 1363411 ASEK2106-NEW-final-TW-20080722 路層162。 之後’請參照圖1J，為了電性連接第一線路層122與 第二線路層162,本實施例形成多個貫穿第二絕緣層15〇、 核心層10、第一絕緣層11〇的導電貫孔T。 然後，請參照圖1K ’本實施例還可在第一絕緣層ι1〇 與第一絕緣層150的外側各自形成一增層結構I%，且增 層結構170分別具有多個銲塾172於其外側。缺後，嗜灸 照圖，在增層結構上17G各自形成—防輝層^ ：：暴 路出，應的鮮塾172。之後，為了防止焊墊172的表面氧 化’逛可在銲墊172上形成一電性連接 鎳金複合層。 疋 έ 將針對圖1L巾的内埋晶片基板的結構部分作詳 細的掏述。 姓槿，Π5分別為圖1L之内埋晶片基板的二種變化 結構的剖面不意圖。 請參照圖1L，太訾#仓丨+ + -絕緣層11G、包括—第 一笛一姑桮、層1Q、一晶片130、一第二絕緣層 層no的ΐ質tiVf以f 一第二線路層162。第一絕緣 compound)。、疋—階段固化膠體（她-stage curabie 核心層1 〇 gp罢从杜 16,以暴露出部分第二=緣層UG上，並具有一開口 110構成一凹措R 緣層110。開ϋ 16與第一絕緣層 例中，可將一二Α而晶片13〇固著凹槽R中。在本實施 氏砕黏著層142配置於晶片130與第一絕緣 12 1363411 ASEK2106-NE W-final-TW-20080722 層110之間，並將一側壁黏膠層144配置於凹槽R的内側 壁與晶片130的側壁之間，以使晶片130固著於凹槽R中。 此外’請參照圖4 ’在其他實施例中，晶片130可僅 藉由底部黏著層142固著於凹槽R中。值得注意的是，第 一絕緣層110可延伸至凹槽R的内側壁與晶片130的側壁 之間的空隙中，故不需在此空隙中另外塞入填充物以防止 爆米花效應。此外，第二絕緣層150的材質也可包括二階 段固化膠體’且第二絕緣層150也可延伸至凹槽R的内側 壁與晶片130的側壁之間的空隙中（未繪示）。另外，請 參照圖5，在其他實施例中，晶片130還可僅藉由側壁黏 膠層144固著於凹槽R中。 第二絕緣層150配置於核心層10上，以覆蓋晶片 130。此外，第二絕緣層150的材質可包括二階段固化膠 體。第一線路層122配置於第一絕緣層110的外側，且第 一絕緣層110位於第一線路層122與核心層10之間。第二 線路層162配置於第二絕緣層150的外側，第二絕緣層150 位於第二線路層I62與核心層10之間。 於本實施例中，第一線路層122與第二線路層162可 藉由多個貫穿第二絕緣層150、核心層10與第一絕緣層110 的導電貫孔T而相互電性連接。第二線路層162與晶片130 可藉由多個貫穿第二絕緣層150的導電盲孔B而相互電性 連接。 此外，本實施例可視實際需求而在第二絕緣層150與 第一絕緣層110的外侧進行增層，本實施例是在第二絕緣 13 1363411 ASEK2106-NEW-final-TW-2008〇722 冰，太:/層結構170具有多個銲墊m於其外側。此 貝鈀例在一增層結構的外侧一 180，且各焊罩層⑽皆暴露出對應的銲墊17，。知罩層 此外為了防止轉172的表面氧化還可在各婷塾 輯接層19G，储㈣时齡複合層。 Λ ^，在本發明中，由於晶片是内埋於後路;^ 會佔據線路板上的承載面積。此外:= i壓人第if絕緣層的材質可為二階段固化膠體，因此 第二導電層時，可加=/緣層、核心層、第二絕緣層與 了加熱第一絕緣層，以使其溢流至晶片的 壁S’凹栌2内側壁之間。如此一來，可避免在晶片的侧 ^。曰側壁之間殘留有空隙及水氣，而造成爆来花 太癸昍'九本，月已以貫施例揭露如上，然其並非用以限定 明^、φΓ:所屬領域中具有通常知識者，在不脫離本發 明之二|:3内’當可作些許之更動與潤飾，因此本發 ㈣㈣^視_之ΐ請專職騎界定者為準。 【圖式簡單說明】 製程示本發明—實施例之内埋晶片基板的 圖與圖2B㈣本發明另—實關 的製程剖面示意圖。 土傲 圖3不本發明又一實施例之内埋晶片基板的製程剖 1363411 ASEK2106-NEW-final-TW-20080722 面示意圖。 圖4與圖5分別為圖1L之内埋晶片基板的二種變化 結構的剖面示意圖。 【主要元件符號說明】 10 :核心層 12 :核心介電層 14 :導電層 14a :核心線路層 • 16 :開 σ 110 :第一絕緣層 120 :第一導電層 122 :第一線路層 130 :晶片 142 :底部黏著層 144 :侧壁黏膠層 150 :第二絕緣層 160 :第二導電層 • 162:第二線路層 170 :增層結構 172 :銲墊 180 :防焊層 190 :電性連接層 200 :内埋晶片基板 Β:導電盲孔 R :凹槽 Τ:導電貫孔 15

Claims (1)

  1. /令上月/‘曰 ;修正 9 % 、 補无 101-2-16 十、1申靖專利範圍·· •〜種内埋晶片基板，包括： 一第一绝緣層； 以暴露層，配置於該第一絕緣層上，並具有一開口， ”一卩分該第一絕緣層； 凹槽中，曰^，固著於由該開口與該第一絕緣層所構成的一 片的側壁該第一絕緣層延伸至該凹槽的内側壁與該晶 第 一 絕緣層，配置於該核心層上，以覆蓋該晶片； 一锅缝Μ 一線路層，配置於該第一絕緣層的外側，且該第 _ S位於该第一線路層與該核心層之間；以及 接 絕緣;以層第二絕緣層的外側’該第二 鱼兮笛〜、該第一線路層與該核心層之間，該第一線路層 :〜線路層電性連接，且第二線路層與該晶片電性連 辞笛!申請專利範圍第1項所述之⑽晶片基板，其中 以弟邑緣層的材質包括二階段固化膠體。 •如申請專利範圍第1項所述之内埋晶片基板，其中 “ 一绝緣層的材質包括二階段固化膠體。 丄.4’如申請專利範圍第1項所述之内埋晶片基板，更包 一底部黏著層，配置於該凹槽内的該第—絕緣層上， 並位於該晶片與該第一絕緣層之間。 5.如申請專利範圍第4項所述之内埋晶片基板，更包 1363411 101-2-16 括： 壁之間 側壁黏膠層，配置於該凹槽的内側壁與該晶片的側 括： .6.如申請專利範圍第1項所述之内埋晶片基板，更包 一侧壁黏膠層，配置於該凹槽的内側壁與該晶片的側 壁之間。 7. 如申請專利範圍第1項所述之内埋晶片基板，更句 多個導電盲孔，貫穿該第二絕緣層並電性連接該第二 線路層與該晶片。 8. 如申凊專利範圍第1項所述之内埋晶片基板，更包 括. 多個導電貫孔’貫穿該第二絕緣層、該核心層與該第 -絕緣層，並紐連接該第―線路層與該第二線路層。 9. 如申請專利範圍第丨項所述之内埋晶片基板， 該核心層包括： ^ 一核心介電層；以及 二核心線路層，分別配置於該核心層的相對兩側。 10·如申請專利範圍第1項所述之内埋晶片基板，更 包括： 二增層結構’分別配置於該第二絕緣層與該第-絕緣 層的外侧，並分別具有多個銲墊於其外側。 u·如申請專利_第10項所述之内埋晶片基板，更 17 1363411 101-2-16 包括： 二銲罩層，分別配置於該些增層結構的外側，並分別 暴露出該些對應的銲墊。 12. —種内埋晶片基板的製作方法，包括： 提供一核心層，其具有一開口； 提供一第一絕緣層與一第一導電層，該第一導電層配 置於該第一絕緣層上； 將該核心層配置於該第一絕緣層上，且該第一絕緣層 位於該核心層與該第一導電層之間； 將一晶片固著於由該開口與該第一絕緣層所構成的 一凹槽中； 提供一第二絕緣層與一第二導電層，且該第二導電層 配置於該第二絕緣層上； 將該第二絕緣層配置於該核心層上，該第二絕緣層位 於該核心層與該第二導電層之間，且蓋住該凹槽； 壓合該第一導電層、該第一絕緣層、該核心層、該第 二絕緣層與該第二導電層； 分別圖案化該第一導電層與該第二導電層，以形成一 第一線路層與一第二線路層，其中該第一線路層與該第二 線路層電性連接，且第二線路層與該晶片電性連接。 13. 如申請專利範圍第12項所述之内埋晶片基板的 製作方法，更包括： 在圖案化該第一導電層之前，形成多個貫穿該第二絕 緣層的導電盲孔，以電性連接該晶片與該第二導電層。 18 1363411 101-2-16 製作=如It利範園第12項所述之内埋晶片基板的 在圖案化該第-導電層與該第 個貫穿該第二絕緣層、該核心層第電叙後’形成多 孔電，接該第一線路層與該第二線路層。 製二=糊…所述之内埋晶片基板的 第二=㈣1電導層二=層'該核•該 制作方法，ιΐ將=範圍第12項所述之内埋晶片基板的 製作方法其中將該晶片固著於該凹槽中的方法包括. 將-底部黏著層配置於該凹槽内的該第一絕緣層 上；以及 將該晶片配置於該底部黏著層上。 制二7法如!:2範圍第16項所述之内埋晶片基板的 氣作方其中將該晶片固著於該凹槽中的方法更包括： 形成-侧壁黏膠層於該凹槽的内侧壁與該晶片的側 壁之間。 18:如:叫專利範圍第12項所述之内埋晶片基板的 製作方法，〃 t_aM固著於該凹射的方法包括： 形成-側壁轉層於該凹槽㈣侧壁與該晶片的側 壁之間。 19.如申。月專利範圍第12項所述之内埋晶片基板的 19 1363411 101-2-16 製作方法，更包括： 在該第一絕緣層與該第二絕緣層的外側各自形成一 增層結構’且該些増層結構分別具有多個銲墊於其外側。 20.如申請專利範圍第19項所述之内埋晶片基板的 製作方法，更包括： 在該些增層結構上各自形成一防焊層，以暴露出該些 對應的鮮塾。 製你如中請專利範圍第12項所述之内埋晶片基板的 法’其中該第一絕緣層的材質包括二階段固化膠體。 製作方2法如2請專^範圍第12項所述之内埋晶片基板的 其中該第二絕緣層的材質包括二階段固化膠體。 20
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US20160118325A1 (en) 2016-04-28

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